1054e4c60SAlex Deucher /* 2054e4c60SAlex Deucher * BIF_4_1 Register documentation 3054e4c60SAlex Deucher * 4054e4c60SAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 5054e4c60SAlex Deucher * 6054e4c60SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7054e4c60SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8054e4c60SAlex Deucher * to deal in the Software without restriction, including without limitation 9054e4c60SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10054e4c60SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11054e4c60SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12054e4c60SAlex Deucher * 13054e4c60SAlex Deucher * The above copyright notice and this permission notice shall be included 14054e4c60SAlex Deucher * in all copies or substantial portions of the Software. 15054e4c60SAlex Deucher * 16054e4c60SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17054e4c60SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18054e4c60SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19054e4c60SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20054e4c60SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21054e4c60SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22054e4c60SAlex Deucher */ 23054e4c60SAlex Deucher 24054e4c60SAlex Deucher #ifndef BIF_4_1_D_H 25054e4c60SAlex Deucher #define BIF_4_1_D_H 26054e4c60SAlex Deucher 27054e4c60SAlex Deucher #define mmMM_INDEX 0x0 28054e4c60SAlex Deucher #define mmMM_INDEX_HI 0x6 29054e4c60SAlex Deucher #define mmMM_DATA 0x1 308763eb7aSAlex Deucher #define mmCC_BIF_BX_FUSESTRAP0 0x14D7 31054e4c60SAlex Deucher #define mmBUS_CNTL 0x1508 32054e4c60SAlex Deucher #define mmCONFIG_CNTL 0x1509 33054e4c60SAlex Deucher #define mmCONFIG_MEMSIZE 0x150a 34054e4c60SAlex Deucher #define mmCONFIG_F0_BASE 0x150b 35054e4c60SAlex Deucher #define mmCONFIG_APER_SIZE 0x150c 36054e4c60SAlex Deucher #define mmCONFIG_REG_APER_SIZE 0x150d 37054e4c60SAlex Deucher #define mmBIF_SCRATCH0 0x150e 38054e4c60SAlex Deucher #define mmBIF_SCRATCH1 0x150f 39054e4c60SAlex Deucher #define mmBX_RESET_EN 0x1514 40054e4c60SAlex Deucher #define mmMM_CFGREGS_CNTL 0x1513 41054e4c60SAlex Deucher #define mmHW_DEBUG 0x1515 42054e4c60SAlex Deucher #define mmMASTER_CREDIT_CNTL 0x1516 43054e4c60SAlex Deucher #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 44054e4c60SAlex Deucher #define mmBX_RESET_CNTL 0x1518 45054e4c60SAlex Deucher #define mmINTERRUPT_CNTL 0x151a 46054e4c60SAlex Deucher #define mmINTERRUPT_CNTL2 0x151b 47054e4c60SAlex Deucher #define mmBIF_DEBUG_CNTL 0x151c 48054e4c60SAlex Deucher #define mmBIF_DEBUG_MUX 0x151d 49054e4c60SAlex Deucher #define mmBIF_DEBUG_OUT 0x151e 50054e4c60SAlex Deucher #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 51054e4c60SAlex Deucher #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 52054e4c60SAlex Deucher #define mmCLKREQB_PAD_CNTL 0x1521 53054e4c60SAlex Deucher #define mmSMBUS_SLV_CNTL 0x14fd 54054e4c60SAlex Deucher #define mmSMBUS_SLV_CNTL1 0x14fe 55054e4c60SAlex Deucher #define mmSMBDAT_PAD_CNTL 0x1522 56054e4c60SAlex Deucher #define mmSMBCLK_PAD_CNTL 0x1523 57054e4c60SAlex Deucher #define mmBIF_XDMA_LO 0x14c0 58054e4c60SAlex Deucher #define mmBIF_XDMA_HI 0x14c1 59054e4c60SAlex Deucher #define mmBIF_FEATURES_CONTROL_MISC 0x14c2 60054e4c60SAlex Deucher #define mmBIF_DOORBELL_CNTL 0x14c3 61054e4c60SAlex Deucher #define mmBIF_SLVARB_MODE 0x14c4 62054e4c60SAlex Deucher #define mmBIF_FB_EN 0x1524 63054e4c60SAlex Deucher #define mmBIF_BUSNUM_CNTL1 0x1525 64054e4c60SAlex Deucher #define mmBIF_BUSNUM_LIST0 0x1526 65054e4c60SAlex Deucher #define mmBIF_BUSNUM_LIST1 0x1527 66054e4c60SAlex Deucher #define mmBIF_BUSNUM_CNTL2 0x152b 67054e4c60SAlex Deucher #define mmBIF_BUSY_DELAY_CNTR 0x1529 68054e4c60SAlex Deucher #define mmBIF_PERFMON_CNTL 0x152c 69054e4c60SAlex Deucher #define mmBIF_PERFCOUNTER0_RESULT 0x152d 70054e4c60SAlex Deucher #define mmBIF_PERFCOUNTER1_RESULT 0x152e 71054e4c60SAlex Deucher #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 72054e4c60SAlex Deucher #define mmGPU_HDP_FLUSH_REQ 0x1537 73054e4c60SAlex Deucher #define mmGPU_HDP_FLUSH_DONE 0x1538 74054e4c60SAlex Deucher #define mmSLAVE_HANG_ERROR 0x153b 75054e4c60SAlex Deucher #define mmCAPTURE_HOST_BUSNUM 0x153c 76054e4c60SAlex Deucher #define mmHOST_BUSNUM 0x153d 77054e4c60SAlex Deucher #define mmPEER_REG_RANGE0 0x153e 78054e4c60SAlex Deucher #define mmPEER_REG_RANGE1 0x153f 79054e4c60SAlex Deucher #define mmPEER0_FB_OFFSET_HI 0x14f3 80054e4c60SAlex Deucher #define mmPEER0_FB_OFFSET_LO 0x14f2 81054e4c60SAlex Deucher #define mmPEER1_FB_OFFSET_HI 0x14f1 82054e4c60SAlex Deucher #define mmPEER1_FB_OFFSET_LO 0x14f0 83054e4c60SAlex Deucher #define mmPEER2_FB_OFFSET_HI 0x14ef 84054e4c60SAlex Deucher #define mmPEER2_FB_OFFSET_LO 0x14ee 85054e4c60SAlex Deucher #define mmPEER3_FB_OFFSET_HI 0x14ed 86054e4c60SAlex Deucher #define mmPEER3_FB_OFFSET_LO 0x14ec 87054e4c60SAlex Deucher #define mmDBG_BYPASS_SRBM_ACCESS 0x14eb 88054e4c60SAlex Deucher #define mmSMBUS_BACO_DUMMY 0x14c6 89054e4c60SAlex Deucher #define mmBIF_DEVFUNCNUM_LIST0 0x14e8 90054e4c60SAlex Deucher #define mmBIF_DEVFUNCNUM_LIST1 0x14e7 91054e4c60SAlex Deucher #define mmBACO_CNTL 0x14e5 92054e4c60SAlex Deucher #define mmBF_ANA_ISO_CNTL 0x14c7 93054e4c60SAlex Deucher #define mmMEM_TYPE_CNTL 0x14e4 94054e4c60SAlex Deucher #define mmBIF_BACO_DEBUG 0x14df 95054e4c60SAlex Deucher #define mmBIF_BACO_DEBUG_LATCH 0x14dc 96054e4c60SAlex Deucher #define mmBACO_CNTL_MISC 0x14db 97054e4c60SAlex Deucher #define mmBIF_SSA_PWR_STATUS 0x14c8 98054e4c60SAlex Deucher #define mmBIF_SSA_GFX0_LOWER 0x14ca 99054e4c60SAlex Deucher #define mmBIF_SSA_GFX0_UPPER 0x14cb 100054e4c60SAlex Deucher #define mmBIF_SSA_GFX1_LOWER 0x14cc 101054e4c60SAlex Deucher #define mmBIF_SSA_GFX1_UPPER 0x14cd 102054e4c60SAlex Deucher #define mmBIF_SSA_GFX2_LOWER 0x14ce 103054e4c60SAlex Deucher #define mmBIF_SSA_GFX2_UPPER 0x14cf 104054e4c60SAlex Deucher #define mmBIF_SSA_GFX3_LOWER 0x14d0 105054e4c60SAlex Deucher #define mmBIF_SSA_GFX3_UPPER 0x14d1 106054e4c60SAlex Deucher #define mmBIF_SSA_DISP_LOWER 0x14d2 107054e4c60SAlex Deucher #define mmBIF_SSA_DISP_UPPER 0x14d3 108054e4c60SAlex Deucher #define mmBIF_SSA_MC_LOWER 0x14d4 109054e4c60SAlex Deucher #define mmBIF_SSA_MC_UPPER 0x14d5 110054e4c60SAlex Deucher #define mmIMPCTL_RESET 0x14f5 111054e4c60SAlex Deucher #define mmGARLIC_FLUSH_CNTL 0x1401 112054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_0 0x1402 113054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_1 0x1404 114054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_2 0x1406 115054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_3 0x1408 116054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_4 0x140a 117054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_5 0x140c 118054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_6 0x140e 119054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_7 0x1410 120054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_0 0x1403 121054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_1 0x1405 122054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_2 0x1407 123054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_3 0x1409 124054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_4 0x140b 125054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_5 0x140d 126054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_6 0x140f 127054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_7 0x1411 128054e4c60SAlex Deucher #define mmGARLIC_FLUSH_REQ 0x1412 129054e4c60SAlex Deucher #define mmGPU_GARLIC_FLUSH_REQ 0x1413 130054e4c60SAlex Deucher #define mmGPU_GARLIC_FLUSH_DONE 0x1414 131054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_RB0_WPTR 0x1415 132054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_RB1_WPTR 0x1416 133054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_RB2_WPTR 0x1417 134054e4c60SAlex Deucher #define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418 135054e4c60SAlex Deucher #define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419 136054e4c60SAlex Deucher #define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a 137054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b 138054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c 139054e4c60SAlex Deucher #define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d 140054e4c60SAlex Deucher #define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e 141054e4c60SAlex Deucher #define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f 142054e4c60SAlex Deucher #define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420 143054e4c60SAlex Deucher #define mmGARLIC_COHE_VCE_RB_WPTR 0x1421 144054e4c60SAlex Deucher #define mmBIOS_SCRATCH_0 0x5c9 145054e4c60SAlex Deucher #define mmBIOS_SCRATCH_1 0x5ca 146054e4c60SAlex Deucher #define mmBIOS_SCRATCH_2 0x5cb 147054e4c60SAlex Deucher #define mmBIOS_SCRATCH_3 0x5cc 148054e4c60SAlex Deucher #define mmBIOS_SCRATCH_4 0x5cd 149054e4c60SAlex Deucher #define mmBIOS_SCRATCH_5 0x5ce 150054e4c60SAlex Deucher #define mmBIOS_SCRATCH_6 0x5cf 151054e4c60SAlex Deucher #define mmBIOS_SCRATCH_7 0x5d0 152054e4c60SAlex Deucher #define mmBIOS_SCRATCH_8 0x5d1 153054e4c60SAlex Deucher #define mmBIOS_SCRATCH_9 0x5d2 154054e4c60SAlex Deucher #define mmBIOS_SCRATCH_10 0x5d3 155054e4c60SAlex Deucher #define mmBIOS_SCRATCH_11 0x5d4 156054e4c60SAlex Deucher #define mmBIOS_SCRATCH_12 0x5d5 157054e4c60SAlex Deucher #define mmBIOS_SCRATCH_13 0x5d6 158054e4c60SAlex Deucher #define mmBIOS_SCRATCH_14 0x5d7 159054e4c60SAlex Deucher #define mmBIOS_SCRATCH_15 0x5d8 160054e4c60SAlex Deucher #define mmVENDOR_ID 0x0 161054e4c60SAlex Deucher #define mmDEVICE_ID 0x0 162054e4c60SAlex Deucher #define mmCOMMAND 0x1 163054e4c60SAlex Deucher #define mmSTATUS 0x1 164054e4c60SAlex Deucher #define mmREVISION_ID 0x2 165054e4c60SAlex Deucher #define mmPROG_INTERFACE 0x2 166054e4c60SAlex Deucher #define mmSUB_CLASS 0x2 167054e4c60SAlex Deucher #define mmBASE_CLASS 0x2 168054e4c60SAlex Deucher #define mmCACHE_LINE 0x3 169054e4c60SAlex Deucher #define mmLATENCY 0x3 170054e4c60SAlex Deucher #define mmHEADER 0x3 171054e4c60SAlex Deucher #define mmBIST 0x3 172054e4c60SAlex Deucher #define mmBASE_ADDR_1 0x4 173054e4c60SAlex Deucher #define mmBASE_ADDR_2 0x5 174054e4c60SAlex Deucher #define mmBASE_ADDR_3 0x6 175054e4c60SAlex Deucher #define mmBASE_ADDR_4 0x7 176054e4c60SAlex Deucher #define mmBASE_ADDR_5 0x8 177054e4c60SAlex Deucher #define mmBASE_ADDR_6 0x9 178054e4c60SAlex Deucher #define mmROM_BASE_ADDR 0xc 179054e4c60SAlex Deucher #define mmCAP_PTR 0xd 180054e4c60SAlex Deucher #define mmINTERRUPT_LINE 0xf 181054e4c60SAlex Deucher #define mmINTERRUPT_PIN 0xf 182054e4c60SAlex Deucher #define mmADAPTER_ID 0xb 183054e4c60SAlex Deucher #define mmMIN_GRANT 0xf 184054e4c60SAlex Deucher #define mmMAX_LATENCY 0xf 185054e4c60SAlex Deucher #define mmVENDOR_CAP_LIST 0x12 186054e4c60SAlex Deucher #define mmADAPTER_ID_W 0x13 187054e4c60SAlex Deucher #define mmPMI_CAP_LIST 0x14 188054e4c60SAlex Deucher #define mmPMI_CAP 0x14 189054e4c60SAlex Deucher #define mmPMI_STATUS_CNTL 0x15 190054e4c60SAlex Deucher #define mmPCIE_CAP_LIST 0x16 191054e4c60SAlex Deucher #define mmPCIE_CAP 0x16 192054e4c60SAlex Deucher #define mmDEVICE_CAP 0x17 193054e4c60SAlex Deucher #define mmDEVICE_CNTL 0x18 194054e4c60SAlex Deucher #define mmDEVICE_STATUS 0x18 195054e4c60SAlex Deucher #define mmLINK_CAP 0x19 196054e4c60SAlex Deucher #define mmLINK_CNTL 0x1a 197054e4c60SAlex Deucher #define mmLINK_STATUS 0x1a 198054e4c60SAlex Deucher #define mmDEVICE_CAP2 0x1f 199054e4c60SAlex Deucher #define mmDEVICE_CNTL2 0x20 200054e4c60SAlex Deucher #define mmDEVICE_STATUS2 0x20 201054e4c60SAlex Deucher #define mmLINK_CAP2 0x21 202054e4c60SAlex Deucher #define mmLINK_CNTL2 0x22 203054e4c60SAlex Deucher #define mmLINK_STATUS2 0x22 204054e4c60SAlex Deucher #define mmMSI_CAP_LIST 0x28 205054e4c60SAlex Deucher #define mmMSI_MSG_CNTL 0x28 206054e4c60SAlex Deucher #define mmMSI_MSG_ADDR_LO 0x29 207054e4c60SAlex Deucher #define mmMSI_MSG_ADDR_HI 0x2a 208054e4c60SAlex Deucher #define mmMSI_MSG_DATA_64 0x2b 209054e4c60SAlex Deucher #define mmMSI_MSG_DATA 0x2a 210054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 211054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 212054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC1 0x42 213054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC2 0x43 214054e4c60SAlex Deucher #define mmPCIE_VC_ENH_CAP_LIST 0x44 215054e4c60SAlex Deucher #define mmPCIE_PORT_VC_CAP_REG1 0x45 216054e4c60SAlex Deucher #define mmPCIE_PORT_VC_CAP_REG2 0x46 217054e4c60SAlex Deucher #define mmPCIE_PORT_VC_CNTL 0x47 218054e4c60SAlex Deucher #define mmPCIE_PORT_VC_STATUS 0x47 219054e4c60SAlex Deucher #define mmPCIE_VC0_RESOURCE_CAP 0x48 220054e4c60SAlex Deucher #define mmPCIE_VC0_RESOURCE_CNTL 0x49 221054e4c60SAlex Deucher #define mmPCIE_VC0_RESOURCE_STATUS 0x4a 222054e4c60SAlex Deucher #define mmPCIE_VC1_RESOURCE_CAP 0x4b 223054e4c60SAlex Deucher #define mmPCIE_VC1_RESOURCE_CNTL 0x4c 224054e4c60SAlex Deucher #define mmPCIE_VC1_RESOURCE_STATUS 0x4d 225054e4c60SAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 226054e4c60SAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 227054e4c60SAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 228054e4c60SAlex Deucher #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 229054e4c60SAlex Deucher #define mmPCIE_UNCORR_ERR_STATUS 0x55 230054e4c60SAlex Deucher #define mmPCIE_UNCORR_ERR_MASK 0x56 231054e4c60SAlex Deucher #define mmPCIE_UNCORR_ERR_SEVERITY 0x57 232054e4c60SAlex Deucher #define mmPCIE_CORR_ERR_STATUS 0x58 233054e4c60SAlex Deucher #define mmPCIE_CORR_ERR_MASK 0x59 234054e4c60SAlex Deucher #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a 235054e4c60SAlex Deucher #define mmPCIE_HDR_LOG0 0x5b 236054e4c60SAlex Deucher #define mmPCIE_HDR_LOG1 0x5c 237054e4c60SAlex Deucher #define mmPCIE_HDR_LOG2 0x5d 238054e4c60SAlex Deucher #define mmPCIE_HDR_LOG3 0x5e 239054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG0 0x62 240054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG1 0x63 241054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG2 0x64 242054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG3 0x65 243054e4c60SAlex Deucher #define mmPCIE_BAR_ENH_CAP_LIST 0x80 244054e4c60SAlex Deucher #define mmPCIE_BAR1_CAP 0x81 245054e4c60SAlex Deucher #define mmPCIE_BAR1_CNTL 0x82 246054e4c60SAlex Deucher #define mmPCIE_BAR2_CAP 0x83 247054e4c60SAlex Deucher #define mmPCIE_BAR2_CNTL 0x84 248054e4c60SAlex Deucher #define mmPCIE_BAR3_CAP 0x85 249054e4c60SAlex Deucher #define mmPCIE_BAR3_CNTL 0x86 250054e4c60SAlex Deucher #define mmPCIE_BAR4_CAP 0x87 251054e4c60SAlex Deucher #define mmPCIE_BAR4_CNTL 0x88 252054e4c60SAlex Deucher #define mmPCIE_BAR5_CAP 0x89 253054e4c60SAlex Deucher #define mmPCIE_BAR5_CNTL 0x8a 254054e4c60SAlex Deucher #define mmPCIE_BAR6_CAP 0x8b 255054e4c60SAlex Deucher #define mmPCIE_BAR6_CNTL 0x8c 256054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 257054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 258054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_DATA 0x92 259054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_CAP 0x93 260054e4c60SAlex Deucher #define mmPCIE_DPA_ENH_CAP_LIST 0x94 261054e4c60SAlex Deucher #define mmPCIE_DPA_CAP 0x95 262054e4c60SAlex Deucher #define mmPCIE_DPA_LATENCY_INDICATOR 0x96 263054e4c60SAlex Deucher #define mmPCIE_DPA_STATUS 0x97 264054e4c60SAlex Deucher #define mmPCIE_DPA_CNTL 0x97 265054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 266054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 267054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 268054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 269054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 270054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 271054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 272054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 273054e4c60SAlex Deucher #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c 274054e4c60SAlex Deucher #define mmPCIE_LINK_CNTL3 0x9d 275054e4c60SAlex Deucher #define mmPCIE_LANE_ERROR_STATUS 0x9e 276054e4c60SAlex Deucher #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f 277054e4c60SAlex Deucher #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f 278054e4c60SAlex Deucher #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 279054e4c60SAlex Deucher #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 280054e4c60SAlex Deucher #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 281054e4c60SAlex Deucher #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 282054e4c60SAlex Deucher #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 283054e4c60SAlex Deucher #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 284054e4c60SAlex Deucher #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 285054e4c60SAlex Deucher #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 286054e4c60SAlex Deucher #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 287054e4c60SAlex Deucher #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 288054e4c60SAlex Deucher #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 289054e4c60SAlex Deucher #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 290054e4c60SAlex Deucher #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 291054e4c60SAlex Deucher #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 292054e4c60SAlex Deucher #define mmPCIE_ACS_ENH_CAP_LIST 0xa8 293054e4c60SAlex Deucher #define mmPCIE_ACS_CAP 0xa9 294054e4c60SAlex Deucher #define mmPCIE_ACS_CNTL 0xa9 295054e4c60SAlex Deucher #define mmPCIE_ATS_ENH_CAP_LIST 0xac 296054e4c60SAlex Deucher #define mmPCIE_ATS_CAP 0xad 297054e4c60SAlex Deucher #define mmPCIE_ATS_CNTL 0xad 298054e4c60SAlex Deucher #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 299054e4c60SAlex Deucher #define mmPCIE_PAGE_REQ_CNTL 0xb1 300054e4c60SAlex Deucher #define mmPCIE_PAGE_REQ_STATUS 0xb1 301054e4c60SAlex Deucher #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 302054e4c60SAlex Deucher #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 303054e4c60SAlex Deucher #define mmPCIE_PASID_ENH_CAP_LIST 0xb4 304054e4c60SAlex Deucher #define mmPCIE_PASID_CAP 0xb5 305054e4c60SAlex Deucher #define mmPCIE_PASID_CNTL 0xb5 306054e4c60SAlex Deucher #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 307054e4c60SAlex Deucher #define mmPCIE_TPH_REQR_CAP 0xb9 308054e4c60SAlex Deucher #define mmPCIE_TPH_REQR_CNTL 0xba 309054e4c60SAlex Deucher #define mmPCIE_MC_ENH_CAP_LIST 0xbc 310054e4c60SAlex Deucher #define mmPCIE_MC_CAP 0xbd 311054e4c60SAlex Deucher #define mmPCIE_MC_CNTL 0xbd 312054e4c60SAlex Deucher #define mmPCIE_MC_ADDR0 0xbe 313054e4c60SAlex Deucher #define mmPCIE_MC_ADDR1 0xbf 314054e4c60SAlex Deucher #define mmPCIE_MC_RCV0 0xc0 315054e4c60SAlex Deucher #define mmPCIE_MC_RCV1 0xc1 316054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_ALL0 0xc2 317054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_ALL1 0xc3 318054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 319054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 320054e4c60SAlex Deucher #define mmPCIE_LTR_ENH_CAP_LIST 0xc8 321054e4c60SAlex Deucher #define mmPCIE_LTR_CAP 0xc9 322054e4c60SAlex Deucher #define mmPCIE_INDEX 0xe 323054e4c60SAlex Deucher #define mmPCIE_DATA 0xf 324054e4c60SAlex Deucher #define mmPCIE_INDEX_2 0xc 325054e4c60SAlex Deucher #define mmPCIE_DATA_2 0xd 326054e4c60SAlex Deucher #define ixPCIE_RESERVED 0x1400000 327054e4c60SAlex Deucher #define ixPCIE_SCRATCH 0x1400001 328054e4c60SAlex Deucher #define ixPCIE_HW_DEBUG 0x1400002 329054e4c60SAlex Deucher #define ixPCIE_RX_NUM_NAK 0x140000e 330054e4c60SAlex Deucher #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f 331054e4c60SAlex Deucher #define ixPCIE_CNTL 0x1400010 332054e4c60SAlex Deucher #define ixPCIE_CONFIG_CNTL 0x1400011 333054e4c60SAlex Deucher #define ixPCIE_DEBUG_CNTL 0x1400012 334054e4c60SAlex Deucher #define ixPCIE_INT_CNTL 0x140001a 335054e4c60SAlex Deucher #define ixPCIE_INT_STATUS 0x140001b 336054e4c60SAlex Deucher #define ixPCIE_CNTL2 0x140001c 337054e4c60SAlex Deucher #define ixPCIE_RX_CNTL2 0x140001d 338054e4c60SAlex Deucher #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e 339054e4c60SAlex Deucher #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f 340054e4c60SAlex Deucher #define ixPCIE_CI_CNTL 0x1400020 341054e4c60SAlex Deucher #define ixPCIE_BUS_CNTL 0x1400021 342054e4c60SAlex Deucher #define ixPCIE_LC_STATE6 0x1400022 343054e4c60SAlex Deucher #define ixPCIE_LC_STATE7 0x1400023 344054e4c60SAlex Deucher #define ixPCIE_LC_STATE8 0x1400024 345054e4c60SAlex Deucher #define ixPCIE_LC_STATE9 0x1400025 346054e4c60SAlex Deucher #define ixPCIE_LC_STATE10 0x1400026 347054e4c60SAlex Deucher #define ixPCIE_LC_STATE11 0x1400027 348054e4c60SAlex Deucher #define ixPCIE_LC_STATUS1 0x1400028 349054e4c60SAlex Deucher #define ixPCIE_LC_STATUS2 0x1400029 350054e4c60SAlex Deucher #define ixPCIE_WPR_CNTL 0x1400030 351054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP0 0x1400031 352054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP1 0x1400032 353054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP2 0x1400033 354054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP3 0x1400034 355054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP0 0x1400035 356054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP1 0x1400036 357054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP2 0x1400037 358054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP3 0x1400038 359054e4c60SAlex Deucher #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a 360054e4c60SAlex Deucher #define ixPCIE_I2C_REG_DATA 0x140003b 361054e4c60SAlex Deucher #define ixPCIE_CFG_CNTL 0x140003c 362054e4c60SAlex Deucher #define ixPCIE_P_CNTL 0x1400040 363054e4c60SAlex Deucher #define ixPCIE_P_BUF_STATUS 0x1400041 364054e4c60SAlex Deucher #define ixPCIE_P_DECODER_STATUS 0x1400042 365054e4c60SAlex Deucher #define ixPCIE_P_MISC_STATUS 0x1400043 366054e4c60SAlex Deucher #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 367054e4c60SAlex Deucher #define ixPCIE_OBFF_CNTL 0x1400061 368054e4c60SAlex Deucher #define ixPCIE_TX_LTR_CNTL 0x1400060 369054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT_CNTL 0x1400080 370054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_TXCLK 0x1400081 371054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 372054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 373054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 374054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 375054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 376054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 377054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 378054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 379054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a 380054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b 381054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c 382054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d 383054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e 384054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f 385054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 386054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 387054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 388054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 389054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 390054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 391054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 392054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 393054e4c60SAlex Deucher #define ixPCIE_STRAP_F0 0x14000b0 394054e4c60SAlex Deucher #define ixPCIE_STRAP_F1 0x14000b1 395054e4c60SAlex Deucher #define ixPCIE_STRAP_F2 0x14000b2 396054e4c60SAlex Deucher #define ixPCIE_STRAP_F3 0x14000b3 397054e4c60SAlex Deucher #define ixPCIE_STRAP_F4 0x14000b4 398054e4c60SAlex Deucher #define ixPCIE_STRAP_F5 0x14000b5 399054e4c60SAlex Deucher #define ixPCIE_STRAP_F6 0x14000b6 400054e4c60SAlex Deucher #define ixPCIE_STRAP_F7 0x14000b7 401054e4c60SAlex Deucher #define ixPCIE_STRAP_MISC 0x14000c0 402054e4c60SAlex Deucher #define ixPCIE_STRAP_MISC2 0x14000c1 403054e4c60SAlex Deucher #define ixPCIE_STRAP_PI 0x14000c2 404054e4c60SAlex Deucher #define ixPCIE_STRAP_I2C_BD 0x14000c4 405054e4c60SAlex Deucher #define ixPCIE_PRBS_CLR 0x14000c8 406054e4c60SAlex Deucher #define ixPCIE_PRBS_STATUS1 0x14000c9 407054e4c60SAlex Deucher #define ixPCIE_PRBS_STATUS2 0x14000ca 408054e4c60SAlex Deucher #define ixPCIE_PRBS_FREERUN 0x14000cb 409054e4c60SAlex Deucher #define ixPCIE_PRBS_MISC 0x14000cc 410054e4c60SAlex Deucher #define ixPCIE_PRBS_USER_PATTERN 0x14000cd 411054e4c60SAlex Deucher #define ixPCIE_PRBS_LO_BITCNT 0x14000ce 412054e4c60SAlex Deucher #define ixPCIE_PRBS_HI_BITCNT 0x14000cf 413054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_0 0x14000d0 414054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_1 0x14000d1 415054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_2 0x14000d2 416054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_3 0x14000d3 417054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_4 0x14000d4 418054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_5 0x14000d5 419054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_6 0x14000d6 420054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_7 0x14000d7 421054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_8 0x14000d8 422054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_9 0x14000d9 423054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_10 0x14000da 424054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_11 0x14000db 425054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_12 0x14000dc 426054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_13 0x14000dd 427054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_14 0x14000de 428054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_15 0x14000df 429054e4c60SAlex Deucher #define ixPCIE_F0_DPA_CAP 0x14000e0 430054e4c60SAlex Deucher #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 431054e4c60SAlex Deucher #define ixPCIE_F0_DPA_CNTL 0x14000e5 432054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 433054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 434054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 435054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea 436054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb 437054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec 438054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed 439054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee 440054e4c60SAlex Deucher #define ixPCIEP_RESERVED 0x10010000 441054e4c60SAlex Deucher #define ixPCIEP_SCRATCH 0x10010001 442054e4c60SAlex Deucher #define ixPCIEP_HW_DEBUG 0x10010002 443054e4c60SAlex Deucher #define ixPCIEP_PORT_CNTL 0x10010010 444054e4c60SAlex Deucher #define ixPCIE_TX_CNTL 0x10010020 445054e4c60SAlex Deucher #define ixPCIE_TX_REQUESTER_ID 0x10010021 446054e4c60SAlex Deucher #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 447054e4c60SAlex Deucher #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 448054e4c60SAlex Deucher #define ixPCIE_TX_SEQ 0x10010024 449054e4c60SAlex Deucher #define ixPCIE_TX_REPLAY 0x10010025 450054e4c60SAlex Deucher #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 451054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 452054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 453054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 454054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_INIT_P 0x10010033 455054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 456054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 457054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_STATUS 0x10010036 458054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 459054e4c60SAlex Deucher #define ixPCIE_P_PORT_LANE_STATUS 0x10010050 460054e4c60SAlex Deucher #define ixPCIE_FC_P 0x10010060 461054e4c60SAlex Deucher #define ixPCIE_FC_NP 0x10010061 462054e4c60SAlex Deucher #define ixPCIE_FC_CPL 0x10010062 463054e4c60SAlex Deucher #define ixPCIE_ERR_CNTL 0x1001006a 464054e4c60SAlex Deucher #define ixPCIE_RX_CNTL 0x10010070 465054e4c60SAlex Deucher #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 466054e4c60SAlex Deucher #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 467054e4c60SAlex Deucher #define ixPCIE_RX_CNTL3 0x10010074 468054e4c60SAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 469054e4c60SAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 470054e4c60SAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 471054e4c60SAlex Deucher #define ixPCIE_LC_CNTL 0x100100a0 472054e4c60SAlex Deucher #define ixPCIE_LC_CNTL2 0x100100b1 473054e4c60SAlex Deucher #define ixPCIE_LC_CNTL3 0x100100b5 474054e4c60SAlex Deucher #define ixPCIE_LC_CNTL4 0x100100b6 475054e4c60SAlex Deucher #define ixPCIE_LC_CNTL5 0x100100b7 476054e4c60SAlex Deucher #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 477054e4c60SAlex Deucher #define ixPCIE_LC_TRAINING_CNTL 0x100100a1 478054e4c60SAlex Deucher #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 479054e4c60SAlex Deucher #define ixPCIE_LC_N_FTS_CNTL 0x100100a3 480054e4c60SAlex Deucher #define ixPCIE_LC_SPEED_CNTL 0x100100a4 481054e4c60SAlex Deucher #define ixPCIE_LC_CDR_CNTL 0x100100b3 482054e4c60SAlex Deucher #define ixPCIE_LC_LANE_CNTL 0x100100b4 483054e4c60SAlex Deucher #define ixPCIE_LC_FORCE_COEFF 0x100100b8 484054e4c60SAlex Deucher #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 485054e4c60SAlex Deucher #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba 486054e4c60SAlex Deucher #define ixPCIE_LC_STATE0 0x100100a5 487054e4c60SAlex Deucher #define ixPCIE_LC_STATE1 0x100100a6 488054e4c60SAlex Deucher #define ixPCIE_LC_STATE2 0x100100a7 489054e4c60SAlex Deucher #define ixPCIE_LC_STATE3 0x100100a8 490054e4c60SAlex Deucher #define ixPCIE_LC_STATE4 0x100100a9 491054e4c60SAlex Deucher #define ixPCIE_LC_STATE5 0x100100aa 492054e4c60SAlex Deucher #define ixPCIEP_STRAP_LC 0x100100c0 493054e4c60SAlex Deucher #define ixPCIEP_STRAP_MISC 0x100100c1 494054e4c60SAlex Deucher #define ixPCIEP_BCH_ECC_CNTL 0x100100d0 495054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG0 0x1200004 496054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG1 0x1200008 497054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG2 0x120000c 498054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG3 0x1200010 499054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG4 0x1200014 500054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG5 0x1200018 501054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c 502054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020 503054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024 504054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028 505054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c 506054e4c60SAlex Deucher #define ixPB0_GLB_OVRD_REG0 0x1200030 507054e4c60SAlex Deucher #define ixPB0_GLB_OVRD_REG1 0x1200034 508054e4c60SAlex Deucher #define ixPB0_GLB_OVRD_REG2 0x1200038 509054e4c60SAlex Deucher #define ixPB0_HW_DEBUG 0x1202004 510054e4c60SAlex Deucher #define ixPB0_STRAP_GLB_REG0 0x1202020 511054e4c60SAlex Deucher #define ixPB0_STRAP_TX_REG0 0x1202024 512054e4c60SAlex Deucher #define ixPB0_STRAP_RX_REG0 0x1202028 513054e4c60SAlex Deucher #define ixPB0_STRAP_RX_REG1 0x120202c 514054e4c60SAlex Deucher #define ixPB0_STRAP_PLL_REG0 0x1202030 515054e4c60SAlex Deucher #define ixPB0_STRAP_PIN_REG0 0x1202034 516054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_REG0 0x1203000 517054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_REG1 0x1203004 518054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_REG2 0x1203008 519054e4c60SAlex Deucher #define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c 520054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010 521054e4c60SAlex Deucher #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000 522054e4c60SAlex Deucher #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010 523054e4c60SAlex Deucher #define ixPB0_PLL_RO0_CTRL_REG0 0x1204440 524054e4c60SAlex Deucher #define ixPB0_PLL_RO0_OVRD_REG0 0x1204450 525054e4c60SAlex Deucher #define ixPB0_PLL_RO0_OVRD_REG1 0x1204454 526054e4c60SAlex Deucher #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460 527054e4c60SAlex Deucher #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464 528054e4c60SAlex Deucher #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468 529054e4c60SAlex Deucher #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c 530054e4c60SAlex Deucher #define ixPB0_PLL_LC0_CTRL_REG0 0x1204480 531054e4c60SAlex Deucher #define ixPB0_PLL_LC0_OVRD_REG0 0x1204490 532054e4c60SAlex Deucher #define ixPB0_PLL_LC0_OVRD_REG1 0x1204494 533054e4c60SAlex Deucher #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500 534054e4c60SAlex Deucher #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504 535054e4c60SAlex Deucher #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508 536054e4c60SAlex Deucher #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c 537054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG0 0x1206000 538054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG1 0x1206004 539054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG2 0x1206008 540054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG3 0x120600c 541054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG4 0x1206010 542054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG5 0x1206014 543054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG6 0x1206018 544054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG7 0x120601c 545054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG8 0x1206020 546054e4c60SAlex Deucher #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028 547054e4c60SAlex Deucher #define ixPB0_RX_GLB_OVRD_REG0 0x1206030 548054e4c60SAlex Deucher #define ixPB0_RX_GLB_OVRD_REG1 0x1206034 549054e4c60SAlex Deucher #define ixPB0_RX_LANE0_CTRL_REG0 0x1206440 550054e4c60SAlex Deucher #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448 551054e4c60SAlex Deucher #define ixPB0_RX_LANE1_CTRL_REG0 0x1206480 552054e4c60SAlex Deucher #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488 553054e4c60SAlex Deucher #define ixPB0_RX_LANE2_CTRL_REG0 0x1206500 554054e4c60SAlex Deucher #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508 555054e4c60SAlex Deucher #define ixPB0_RX_LANE3_CTRL_REG0 0x1206600 556054e4c60SAlex Deucher #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608 557054e4c60SAlex Deucher #define ixPB0_RX_LANE4_CTRL_REG0 0x1206800 558054e4c60SAlex Deucher #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848 559054e4c60SAlex Deucher #define ixPB0_RX_LANE5_CTRL_REG0 0x1206880 560054e4c60SAlex Deucher #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888 561054e4c60SAlex Deucher #define ixPB0_RX_LANE6_CTRL_REG0 0x1206900 562054e4c60SAlex Deucher #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908 563054e4c60SAlex Deucher #define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00 564054e4c60SAlex Deucher #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08 565054e4c60SAlex Deucher #define ixPB0_RX_LANE8_CTRL_REG0 0x1207440 566054e4c60SAlex Deucher #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448 567054e4c60SAlex Deucher #define ixPB0_RX_LANE9_CTRL_REG0 0x1207480 568054e4c60SAlex Deucher #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488 569054e4c60SAlex Deucher #define ixPB0_RX_LANE10_CTRL_REG0 0x1207500 570054e4c60SAlex Deucher #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508 571054e4c60SAlex Deucher #define ixPB0_RX_LANE11_CTRL_REG0 0x1207600 572054e4c60SAlex Deucher #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608 573054e4c60SAlex Deucher #define ixPB0_RX_LANE12_CTRL_REG0 0x1207840 574054e4c60SAlex Deucher #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848 575054e4c60SAlex Deucher #define ixPB0_RX_LANE13_CTRL_REG0 0x1207880 576054e4c60SAlex Deucher #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888 577054e4c60SAlex Deucher #define ixPB0_RX_LANE14_CTRL_REG0 0x1207900 578054e4c60SAlex Deucher #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908 579054e4c60SAlex Deucher #define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00 580054e4c60SAlex Deucher #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08 581054e4c60SAlex Deucher #define ixPB0_TX_GLB_CTRL_REG0 0x1208000 582054e4c60SAlex Deucher #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004 583054e4c60SAlex Deucher #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010 584054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014 585054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018 586054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c 587054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020 588054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG0 0x1208030 589054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG1 0x1208034 590054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG2 0x1208038 591054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG3 0x120803c 592054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG4 0x1208040 593054e4c60SAlex Deucher #define ixPB0_TX_LANE0_CTRL_REG0 0x1208440 594054e4c60SAlex Deucher #define ixPB0_TX_LANE0_OVRD_REG0 0x1208444 595054e4c60SAlex Deucher #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448 596054e4c60SAlex Deucher #define ixPB0_TX_LANE1_CTRL_REG0 0x1208480 597054e4c60SAlex Deucher #define ixPB0_TX_LANE1_OVRD_REG0 0x1208484 598054e4c60SAlex Deucher #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488 599054e4c60SAlex Deucher #define ixPB0_TX_LANE2_CTRL_REG0 0x1208500 600054e4c60SAlex Deucher #define ixPB0_TX_LANE2_OVRD_REG0 0x1208504 601054e4c60SAlex Deucher #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508 602054e4c60SAlex Deucher #define ixPB0_TX_LANE3_CTRL_REG0 0x1208600 603054e4c60SAlex Deucher #define ixPB0_TX_LANE3_OVRD_REG0 0x1208604 604054e4c60SAlex Deucher #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608 605054e4c60SAlex Deucher #define ixPB0_TX_LANE4_CTRL_REG0 0x1208840 606054e4c60SAlex Deucher #define ixPB0_TX_LANE4_OVRD_REG0 0x1208844 607054e4c60SAlex Deucher #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848 608054e4c60SAlex Deucher #define ixPB0_TX_LANE5_CTRL_REG0 0x1208880 609054e4c60SAlex Deucher #define ixPB0_TX_LANE5_OVRD_REG0 0x1208884 610054e4c60SAlex Deucher #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888 611054e4c60SAlex Deucher #define ixPB0_TX_LANE6_CTRL_REG0 0x1208900 612054e4c60SAlex Deucher #define ixPB0_TX_LANE6_OVRD_REG0 0x1208904 613054e4c60SAlex Deucher #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908 614054e4c60SAlex Deucher #define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00 615054e4c60SAlex Deucher #define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04 616054e4c60SAlex Deucher #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08 617054e4c60SAlex Deucher #define ixPB0_TX_LANE8_CTRL_REG0 0x1209440 618054e4c60SAlex Deucher #define ixPB0_TX_LANE8_OVRD_REG0 0x1209444 619054e4c60SAlex Deucher #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448 620054e4c60SAlex Deucher #define ixPB0_TX_LANE9_CTRL_REG0 0x1209480 621054e4c60SAlex Deucher #define ixPB0_TX_LANE9_OVRD_REG0 0x1209484 622054e4c60SAlex Deucher #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488 623054e4c60SAlex Deucher #define ixPB0_TX_LANE10_CTRL_REG0 0x1209500 624054e4c60SAlex Deucher #define ixPB0_TX_LANE10_OVRD_REG0 0x1209504 625054e4c60SAlex Deucher #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508 626054e4c60SAlex Deucher #define ixPB0_TX_LANE11_CTRL_REG0 0x1209600 627054e4c60SAlex Deucher #define ixPB0_TX_LANE11_OVRD_REG0 0x1209604 628054e4c60SAlex Deucher #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608 629054e4c60SAlex Deucher #define ixPB0_TX_LANE12_CTRL_REG0 0x1209840 630054e4c60SAlex Deucher #define ixPB0_TX_LANE12_OVRD_REG0 0x1209844 631054e4c60SAlex Deucher #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848 632054e4c60SAlex Deucher #define ixPB0_TX_LANE13_CTRL_REG0 0x1209880 633054e4c60SAlex Deucher #define ixPB0_TX_LANE13_OVRD_REG0 0x1209884 634054e4c60SAlex Deucher #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888 635054e4c60SAlex Deucher #define ixPB0_TX_LANE14_CTRL_REG0 0x1209900 636054e4c60SAlex Deucher #define ixPB0_TX_LANE14_OVRD_REG0 0x1209904 637054e4c60SAlex Deucher #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908 638054e4c60SAlex Deucher #define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00 639054e4c60SAlex Deucher #define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04 640054e4c60SAlex Deucher #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08 641054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG0 0x2200004 642054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG1 0x2200008 643054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG2 0x220000c 644054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG3 0x2200010 645054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG4 0x2200014 646054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG5 0x2200018 647054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c 648054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020 649054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024 650054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028 651054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c 652054e4c60SAlex Deucher #define ixPB1_GLB_OVRD_REG0 0x2200030 653054e4c60SAlex Deucher #define ixPB1_GLB_OVRD_REG1 0x2200034 654054e4c60SAlex Deucher #define ixPB1_GLB_OVRD_REG2 0x2200038 655054e4c60SAlex Deucher #define ixPB1_HW_DEBUG 0x2202004 656054e4c60SAlex Deucher #define ixPB1_STRAP_GLB_REG0 0x2202020 657054e4c60SAlex Deucher #define ixPB1_STRAP_TX_REG0 0x2202024 658054e4c60SAlex Deucher #define ixPB1_STRAP_RX_REG0 0x2202028 659054e4c60SAlex Deucher #define ixPB1_STRAP_RX_REG1 0x220202c 660054e4c60SAlex Deucher #define ixPB1_STRAP_PLL_REG0 0x2202030 661054e4c60SAlex Deucher #define ixPB1_STRAP_PIN_REG0 0x2202034 662054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_REG0 0x2203000 663054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_REG1 0x2203004 664054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_REG2 0x2203008 665054e4c60SAlex Deucher #define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c 666054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010 667054e4c60SAlex Deucher #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000 668054e4c60SAlex Deucher #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010 669054e4c60SAlex Deucher #define ixPB1_PLL_RO0_CTRL_REG0 0x2204440 670054e4c60SAlex Deucher #define ixPB1_PLL_RO0_OVRD_REG0 0x2204450 671054e4c60SAlex Deucher #define ixPB1_PLL_RO0_OVRD_REG1 0x2204454 672054e4c60SAlex Deucher #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460 673054e4c60SAlex Deucher #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464 674054e4c60SAlex Deucher #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468 675054e4c60SAlex Deucher #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c 676054e4c60SAlex Deucher #define ixPB1_PLL_LC0_CTRL_REG0 0x2204480 677054e4c60SAlex Deucher #define ixPB1_PLL_LC0_OVRD_REG0 0x2204490 678054e4c60SAlex Deucher #define ixPB1_PLL_LC0_OVRD_REG1 0x2204494 679054e4c60SAlex Deucher #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500 680054e4c60SAlex Deucher #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504 681054e4c60SAlex Deucher #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508 682054e4c60SAlex Deucher #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c 683054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG0 0x2206000 684054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG1 0x2206004 685054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG2 0x2206008 686054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG3 0x220600c 687054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG4 0x2206010 688054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG5 0x2206014 689054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG6 0x2206018 690054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG7 0x220601c 691054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG8 0x2206020 692054e4c60SAlex Deucher #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028 693054e4c60SAlex Deucher #define ixPB1_RX_GLB_OVRD_REG0 0x2206030 694054e4c60SAlex Deucher #define ixPB1_RX_GLB_OVRD_REG1 0x2206034 695054e4c60SAlex Deucher #define ixPB1_RX_LANE0_CTRL_REG0 0x2206440 696054e4c60SAlex Deucher #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448 697054e4c60SAlex Deucher #define ixPB1_RX_LANE1_CTRL_REG0 0x2206480 698054e4c60SAlex Deucher #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488 699054e4c60SAlex Deucher #define ixPB1_RX_LANE2_CTRL_REG0 0x2206500 700054e4c60SAlex Deucher #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508 701054e4c60SAlex Deucher #define ixPB1_RX_LANE3_CTRL_REG0 0x2206600 702054e4c60SAlex Deucher #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608 703054e4c60SAlex Deucher #define ixPB1_RX_LANE4_CTRL_REG0 0x2206800 704054e4c60SAlex Deucher #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848 705054e4c60SAlex Deucher #define ixPB1_RX_LANE5_CTRL_REG0 0x2206880 706054e4c60SAlex Deucher #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888 707054e4c60SAlex Deucher #define ixPB1_RX_LANE6_CTRL_REG0 0x2206900 708054e4c60SAlex Deucher #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908 709054e4c60SAlex Deucher #define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00 710054e4c60SAlex Deucher #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08 711054e4c60SAlex Deucher #define ixPB1_RX_LANE8_CTRL_REG0 0x2207440 712054e4c60SAlex Deucher #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448 713054e4c60SAlex Deucher #define ixPB1_RX_LANE9_CTRL_REG0 0x2207480 714054e4c60SAlex Deucher #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488 715054e4c60SAlex Deucher #define ixPB1_RX_LANE10_CTRL_REG0 0x2207500 716054e4c60SAlex Deucher #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508 717054e4c60SAlex Deucher #define ixPB1_RX_LANE11_CTRL_REG0 0x2207600 718054e4c60SAlex Deucher #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608 719054e4c60SAlex Deucher #define ixPB1_RX_LANE12_CTRL_REG0 0x2207840 720054e4c60SAlex Deucher #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848 721054e4c60SAlex Deucher #define ixPB1_RX_LANE13_CTRL_REG0 0x2207880 722054e4c60SAlex Deucher #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888 723054e4c60SAlex Deucher #define ixPB1_RX_LANE14_CTRL_REG0 0x2207900 724054e4c60SAlex Deucher #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908 725054e4c60SAlex Deucher #define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00 726054e4c60SAlex Deucher #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08 727054e4c60SAlex Deucher #define ixPB1_TX_GLB_CTRL_REG0 0x2208000 728054e4c60SAlex Deucher #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004 729054e4c60SAlex Deucher #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010 730054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014 731054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018 732054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c 733054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020 734054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG0 0x2208030 735054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG1 0x2208034 736054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG2 0x2208038 737054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG3 0x220803c 738054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG4 0x2208040 739054e4c60SAlex Deucher #define ixPB1_TX_LANE0_CTRL_REG0 0x2208440 740054e4c60SAlex Deucher #define ixPB1_TX_LANE0_OVRD_REG0 0x2208444 741054e4c60SAlex Deucher #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448 742054e4c60SAlex Deucher #define ixPB1_TX_LANE1_CTRL_REG0 0x2208480 743054e4c60SAlex Deucher #define ixPB1_TX_LANE1_OVRD_REG0 0x2208484 744054e4c60SAlex Deucher #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488 745054e4c60SAlex Deucher #define ixPB1_TX_LANE2_CTRL_REG0 0x2208500 746054e4c60SAlex Deucher #define ixPB1_TX_LANE2_OVRD_REG0 0x2208504 747054e4c60SAlex Deucher #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508 748054e4c60SAlex Deucher #define ixPB1_TX_LANE3_CTRL_REG0 0x2208600 749054e4c60SAlex Deucher #define ixPB1_TX_LANE3_OVRD_REG0 0x2208604 750054e4c60SAlex Deucher #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608 751054e4c60SAlex Deucher #define ixPB1_TX_LANE4_CTRL_REG0 0x2208840 752054e4c60SAlex Deucher #define ixPB1_TX_LANE4_OVRD_REG0 0x2208844 753054e4c60SAlex Deucher #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848 754054e4c60SAlex Deucher #define ixPB1_TX_LANE5_CTRL_REG0 0x2208880 755054e4c60SAlex Deucher #define ixPB1_TX_LANE5_OVRD_REG0 0x2208884 756054e4c60SAlex Deucher #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888 757054e4c60SAlex Deucher #define ixPB1_TX_LANE6_CTRL_REG0 0x2208900 758054e4c60SAlex Deucher #define ixPB1_TX_LANE6_OVRD_REG0 0x2208904 759054e4c60SAlex Deucher #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908 760054e4c60SAlex Deucher #define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00 761054e4c60SAlex Deucher #define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04 762054e4c60SAlex Deucher #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08 763054e4c60SAlex Deucher #define ixPB1_TX_LANE8_CTRL_REG0 0x2209440 764054e4c60SAlex Deucher #define ixPB1_TX_LANE8_OVRD_REG0 0x2209444 765054e4c60SAlex Deucher #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448 766054e4c60SAlex Deucher #define ixPB1_TX_LANE9_CTRL_REG0 0x2209480 767054e4c60SAlex Deucher #define ixPB1_TX_LANE9_OVRD_REG0 0x2209484 768054e4c60SAlex Deucher #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488 769054e4c60SAlex Deucher #define ixPB1_TX_LANE10_CTRL_REG0 0x2209500 770054e4c60SAlex Deucher #define ixPB1_TX_LANE10_OVRD_REG0 0x2209504 771054e4c60SAlex Deucher #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508 772054e4c60SAlex Deucher #define ixPB1_TX_LANE11_CTRL_REG0 0x2209600 773054e4c60SAlex Deucher #define ixPB1_TX_LANE11_OVRD_REG0 0x2209604 774054e4c60SAlex Deucher #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608 775054e4c60SAlex Deucher #define ixPB1_TX_LANE12_CTRL_REG0 0x2209840 776054e4c60SAlex Deucher #define ixPB1_TX_LANE12_OVRD_REG0 0x2209844 777054e4c60SAlex Deucher #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848 778054e4c60SAlex Deucher #define ixPB1_TX_LANE13_CTRL_REG0 0x2209880 779054e4c60SAlex Deucher #define ixPB1_TX_LANE13_OVRD_REG0 0x2209884 780054e4c60SAlex Deucher #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888 781054e4c60SAlex Deucher #define ixPB1_TX_LANE14_CTRL_REG0 0x2209900 782054e4c60SAlex Deucher #define ixPB1_TX_LANE14_OVRD_REG0 0x2209904 783054e4c60SAlex Deucher #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908 784054e4c60SAlex Deucher #define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00 785054e4c60SAlex Deucher #define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04 786054e4c60SAlex Deucher #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08 787054e4c60SAlex Deucher #define ixPB0_PIF_SCRATCH 0x1100001 788054e4c60SAlex Deucher #define ixPB0_PIF_HW_DEBUG 0x1100002 789054e4c60SAlex Deucher #define ixPB0_PIF_PRG6 0x1100003 790054e4c60SAlex Deucher #define ixPB0_PIF_PRG7 0x1100004 791054e4c60SAlex Deucher #define ixPB0_PIF_CNTL 0x1100010 792054e4c60SAlex Deucher #define ixPB0_PIF_PAIRING 0x1100011 793054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_0 0x1100012 794054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_1 0x1100013 795054e4c60SAlex Deucher #define ixPB0_PIF_CNTL2 0x1100014 796054e4c60SAlex Deucher #define ixPB0_PIF_TXPHYSTATUS 0x1100015 797054e4c60SAlex Deucher #define ixPB0_PIF_SC_CTL 0x1100016 798054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_2 0x1100017 799054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_3 0x1100018 800054e4c60SAlex Deucher #define ixPB0_PIF_SC_CTL2 0x1100019 801054e4c60SAlex Deucher #define ixPB0_PIF_PRG0 0x110001a 802054e4c60SAlex Deucher #define ixPB0_PIF_PRG1 0x110001b 803054e4c60SAlex Deucher #define ixPB0_PIF_PRG2 0x110001c 804054e4c60SAlex Deucher #define ixPB0_PIF_PRG3 0x110001d 805054e4c60SAlex Deucher #define ixPB0_PIF_PRG4 0x110001e 806054e4c60SAlex Deucher #define ixPB0_PIF_PRG5 0x110001f 807054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_0 0x1100020 808054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_1 0x1100021 809054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_2 0x1100022 810054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_3 0x1100023 811054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_4 0x1100024 812054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_5 0x1100025 813054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_6 0x1100026 814054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_7 0x1100027 815054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_0 0x1100028 816054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_1 0x1100029 817054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_2 0x110002a 818054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_3 0x110002b 819054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_4 0x110002c 820054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_5 0x110002d 821054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_6 0x110002e 822054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_7 0x110002f 823054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_8 0x1100030 824054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_9 0x1100031 825054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_10 0x1100032 826054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_11 0x1100033 827054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_12 0x1100034 828054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_13 0x1100035 829054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_14 0x1100036 830054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_15 0x1100037 831054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_8 0x1100038 832054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_9 0x1100039 833054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_10 0x110003a 834054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_11 0x110003b 835054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_12 0x110003c 836054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_13 0x110003d 837054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_14 0x110003e 838054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_15 0x110003f 839054e4c60SAlex Deucher #define ixPB1_PIF_SCRATCH 0x2100001 840054e4c60SAlex Deucher #define ixPB1_PIF_HW_DEBUG 0x2100002 841054e4c60SAlex Deucher #define ixPB1_PIF_PRG6 0x2100003 842054e4c60SAlex Deucher #define ixPB1_PIF_PRG7 0x2100004 843054e4c60SAlex Deucher #define ixPB1_PIF_CNTL 0x2100010 844054e4c60SAlex Deucher #define ixPB1_PIF_PAIRING 0x2100011 845054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_0 0x2100012 846054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_1 0x2100013 847054e4c60SAlex Deucher #define ixPB1_PIF_CNTL2 0x2100014 848054e4c60SAlex Deucher #define ixPB1_PIF_TXPHYSTATUS 0x2100015 849054e4c60SAlex Deucher #define ixPB1_PIF_SC_CTL 0x2100016 850054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_2 0x2100017 851054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_3 0x2100018 852054e4c60SAlex Deucher #define ixPB1_PIF_SC_CTL2 0x2100019 853054e4c60SAlex Deucher #define ixPB1_PIF_PRG0 0x210001a 854054e4c60SAlex Deucher #define ixPB1_PIF_PRG1 0x210001b 855054e4c60SAlex Deucher #define ixPB1_PIF_PRG2 0x210001c 856054e4c60SAlex Deucher #define ixPB1_PIF_PRG3 0x210001d 857054e4c60SAlex Deucher #define ixPB1_PIF_PRG4 0x210001e 858054e4c60SAlex Deucher #define ixPB1_PIF_PRG5 0x210001f 859054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_0 0x2100020 860054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_1 0x2100021 861054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_2 0x2100022 862054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_3 0x2100023 863054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_4 0x2100024 864054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_5 0x2100025 865054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_6 0x2100026 866054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_7 0x2100027 867054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_0 0x2100028 868054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_1 0x2100029 869054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_2 0x210002a 870054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_3 0x210002b 871054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_4 0x210002c 872054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_5 0x210002d 873054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_6 0x210002e 874054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_7 0x210002f 875054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_8 0x2100030 876054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_9 0x2100031 877054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_10 0x2100032 878054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_11 0x2100033 879054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_12 0x2100034 880054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_13 0x2100035 881054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_14 0x2100036 882054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_15 0x2100037 883054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_8 0x2100038 884054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_9 0x2100039 885054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_10 0x210003a 886054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_11 0x210003b 887054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_12 0x210003c 888054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_13 0x210003d 889054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_14 0x210003e 890054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_15 0x210003f 891054e4c60SAlex Deucher #define mmBIF_RFE_SNOOP_REG 0x27 892054e4c60SAlex Deucher #define mmBIF_RFE_WARMRST_CNTL 0x1459 893054e4c60SAlex Deucher #define mmBIF_RFE_SOFTRST_CNTL 0x1441 894054e4c60SAlex Deucher #define mmBIF_RFE_IMPRST_CNTL 0x1458 895054e4c60SAlex Deucher #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 896054e4c60SAlex Deucher #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 897054e4c60SAlex Deucher #define mmBIF_PWDN_COMMAND 0x1444 898054e4c60SAlex Deucher #define mmBIF_PWDN_STATUS 0x1445 899054e4c60SAlex Deucher #define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446 900054e4c60SAlex Deucher #define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447 901054e4c60SAlex Deucher #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448 902054e4c60SAlex Deucher #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b 903054e4c60SAlex Deucher #define mmBIF_RFE_MMCFG_CNTL 0x144c 904054e4c60SAlex Deucher #define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455 905054e4c60SAlex Deucher #define mmBIF_IMPCTL_SMPLCNTL 0x1450 906054e4c60SAlex Deucher #define mmBIF_IMPCTL_RXCNTL 0x1451 907054e4c60SAlex Deucher #define mmBIF_IMPCTL_TXCNTL_pd 0x1452 908054e4c60SAlex Deucher #define mmBIF_IMPCTL_TXCNTL_pu 0x1453 909054e4c60SAlex Deucher #define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454 910054e4c60SAlex Deucher #define mmBIF_CLOCKS_BITS 0x1489 911054e4c60SAlex Deucher #define mmBIF_LNCNT_RESET 0x1488 912054e4c60SAlex Deucher #define mmLNCNT_CONTROL 0x1487 913054e4c60SAlex Deucher #define mmNEW_REFCLKB_TIMER 0x1485 914054e4c60SAlex Deucher #define mmNEW_REFCLKB_TIMER_1 0x1484 915054e4c60SAlex Deucher #define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483 916054e4c60SAlex Deucher #define mmBIF_RESET_EN 0x1482 917054e4c60SAlex Deucher #define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481 918054e4c60SAlex Deucher #define mmBIF_BACO_MSIC 0x1480 919054e4c60SAlex Deucher #define mmBIF_RESET_CNTL 0x1486 920054e4c60SAlex Deucher #define mmBIF_RFE_CNTL_MISC 0x148c 921054e4c60SAlex Deucher 922054e4c60SAlex Deucher #endif /* BIF_4_1_D_H */ 923