1*f41c9639SHawking Zhang /* 2*f41c9639SHawking Zhang * Copyright 2021 Advanced Micro Devices, Inc. 3*f41c9639SHawking Zhang * 4*f41c9639SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*f41c9639SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*f41c9639SHawking Zhang * to deal in the Software without restriction, including without limitation 7*f41c9639SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*f41c9639SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*f41c9639SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*f41c9639SHawking Zhang * 11*f41c9639SHawking Zhang * The above copyright notice and this permission notice shall be included in 12*f41c9639SHawking Zhang * all copies or substantial portions of the Software. 13*f41c9639SHawking Zhang * 14*f41c9639SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*f41c9639SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*f41c9639SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*f41c9639SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*f41c9639SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*f41c9639SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*f41c9639SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*f41c9639SHawking Zhang * 22*f41c9639SHawking Zhang */ 23*f41c9639SHawking Zhang #ifndef _athub_3_0_0_SH_MASK_HEADER 24*f41c9639SHawking Zhang #define _athub_3_0_0_SH_MASK_HEADER 25*f41c9639SHawking Zhang 26*f41c9639SHawking Zhang 27*f41c9639SHawking Zhang // addressBlock: athub_xpbdec 28*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR0 29*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 30*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 31*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR1 32*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 33*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 34*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR2 35*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 36*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 37*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR3 38*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 39*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 40*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR4 41*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 42*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 43*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR5 44*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 45*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 46*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR6 47*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 48*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 49*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR7 50*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 51*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 52*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR8 53*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 54*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 55*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR9 56*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 57*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 58*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR10 59*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR10__BASE_ADDR__SHIFT 0x0 60*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR10__BASE_ADDR_MASK 0x7FFFFFFFL 61*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR11 62*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR11__BASE_ADDR__SHIFT 0x0 63*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR11__BASE_ADDR_MASK 0x7FFFFFFFL 64*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR12 65*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR12__BASE_ADDR__SHIFT 0x0 66*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR12__BASE_ADDR_MASK 0x7FFFFFFFL 67*f41c9639SHawking Zhang //XPB_RTR_SRC_APRTR13 68*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR13__BASE_ADDR__SHIFT 0x0 69*f41c9639SHawking Zhang #define XPB_RTR_SRC_APRTR13__BASE_ADDR_MASK 0x7FFFFFFFL 70*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP0 71*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 72*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 73*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 74*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 75*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 76*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 77*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 78*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 79*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 80*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 81*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 82*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 83*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP1 84*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 85*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 86*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 87*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 88*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 89*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 90*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 91*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 92*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 93*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 94*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 95*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 96*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP2 97*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 98*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 99*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 100*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 101*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 102*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 103*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 104*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 105*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 106*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 107*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 108*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 109*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP3 110*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 111*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 112*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 113*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 114*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 115*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 116*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 117*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 118*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 119*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 120*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 121*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 122*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP4 123*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 124*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 125*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 126*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 127*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 128*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 129*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 130*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 131*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 132*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 133*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L 134*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 135*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP5 136*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 137*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 138*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 139*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 140*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 141*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 142*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 143*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 144*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 145*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 146*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L 147*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 148*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP6 149*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 150*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 151*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 152*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 153*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 154*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 155*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 156*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 157*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 158*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 159*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L 160*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 161*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP7 162*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 163*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 164*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 165*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 166*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 167*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 168*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 169*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 170*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 171*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 172*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L 173*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 174*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP8 175*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 176*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 177*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 178*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 179*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 180*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 181*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 182*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 183*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 184*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 185*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L 186*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 187*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP9 188*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 189*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 190*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 191*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 192*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 193*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 194*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 195*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 196*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 197*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 198*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L 199*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 200*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP10 201*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__NMR__SHIFT 0x0 202*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__DEST_OFFSET__SHIFT 0x1 203*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__DEST_SEL__SHIFT 0x14 204*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB__SHIFT 0x18 205*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__SIDE_OK__SHIFT 0x19 206*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__APRTR_SIZE__SHIFT 0x1a 207*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__NMR_MASK 0x00000001L 208*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__DEST_OFFSET_MASK 0x000FFFFEL 209*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__DEST_SEL_MASK 0x00F00000L 210*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB_MASK 0x01000000L 211*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__SIDE_OK_MASK 0x02000000L 212*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP10__APRTR_SIZE_MASK 0x7C000000L 213*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP11 214*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__NMR__SHIFT 0x0 215*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__DEST_OFFSET__SHIFT 0x1 216*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__DEST_SEL__SHIFT 0x14 217*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB__SHIFT 0x18 218*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__SIDE_OK__SHIFT 0x19 219*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__APRTR_SIZE__SHIFT 0x1a 220*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__NMR_MASK 0x00000001L 221*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__DEST_OFFSET_MASK 0x000FFFFEL 222*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__DEST_SEL_MASK 0x00F00000L 223*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB_MASK 0x01000000L 224*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__SIDE_OK_MASK 0x02000000L 225*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP11__APRTR_SIZE_MASK 0x7C000000L 226*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP12 227*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__NMR__SHIFT 0x0 228*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__DEST_OFFSET__SHIFT 0x1 229*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__DEST_SEL__SHIFT 0x14 230*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB__SHIFT 0x18 231*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__SIDE_OK__SHIFT 0x19 232*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__APRTR_SIZE__SHIFT 0x1a 233*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__NMR_MASK 0x00000001L 234*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__DEST_OFFSET_MASK 0x000FFFFEL 235*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__DEST_SEL_MASK 0x00F00000L 236*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB_MASK 0x01000000L 237*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__SIDE_OK_MASK 0x02000000L 238*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP12__APRTR_SIZE_MASK 0x7C000000L 239*f41c9639SHawking Zhang //XPB_RTR_DEST_MAP13 240*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__NMR__SHIFT 0x0 241*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__DEST_OFFSET__SHIFT 0x1 242*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__DEST_SEL__SHIFT 0x14 243*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB__SHIFT 0x18 244*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__SIDE_OK__SHIFT 0x19 245*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__APRTR_SIZE__SHIFT 0x1a 246*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__NMR_MASK 0x00000001L 247*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__DEST_OFFSET_MASK 0x000FFFFEL 248*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__DEST_SEL_MASK 0x00F00000L 249*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB_MASK 0x01000000L 250*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__SIDE_OK_MASK 0x02000000L 251*f41c9639SHawking Zhang #define XPB_RTR_DEST_MAP13__APRTR_SIZE_MASK 0x7C000000L 252*f41c9639SHawking Zhang //XPB_CLG_CFG0 253*f41c9639SHawking Zhang #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 254*f41c9639SHawking Zhang #define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 255*f41c9639SHawking Zhang #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 256*f41c9639SHawking Zhang #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 257*f41c9639SHawking Zhang #define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe 258*f41c9639SHawking Zhang #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 259*f41c9639SHawking Zhang #define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L 260*f41c9639SHawking Zhang #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 261*f41c9639SHawking Zhang #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 262*f41c9639SHawking Zhang #define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L 263*f41c9639SHawking Zhang //XPB_CLG_CFG1 264*f41c9639SHawking Zhang #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 265*f41c9639SHawking Zhang #define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 266*f41c9639SHawking Zhang #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 267*f41c9639SHawking Zhang #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 268*f41c9639SHawking Zhang #define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe 269*f41c9639SHawking Zhang #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 270*f41c9639SHawking Zhang #define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L 271*f41c9639SHawking Zhang #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 272*f41c9639SHawking Zhang #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 273*f41c9639SHawking Zhang #define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L 274*f41c9639SHawking Zhang //XPB_CLG_CFG2 275*f41c9639SHawking Zhang #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 276*f41c9639SHawking Zhang #define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 277*f41c9639SHawking Zhang #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 278*f41c9639SHawking Zhang #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 279*f41c9639SHawking Zhang #define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe 280*f41c9639SHawking Zhang #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 281*f41c9639SHawking Zhang #define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L 282*f41c9639SHawking Zhang #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 283*f41c9639SHawking Zhang #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 284*f41c9639SHawking Zhang #define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L 285*f41c9639SHawking Zhang //XPB_CLG_CFG3 286*f41c9639SHawking Zhang #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 287*f41c9639SHawking Zhang #define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 288*f41c9639SHawking Zhang #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 289*f41c9639SHawking Zhang #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 290*f41c9639SHawking Zhang #define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe 291*f41c9639SHawking Zhang #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 292*f41c9639SHawking Zhang #define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L 293*f41c9639SHawking Zhang #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 294*f41c9639SHawking Zhang #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 295*f41c9639SHawking Zhang #define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L 296*f41c9639SHawking Zhang //XPB_CLG_CFG4 297*f41c9639SHawking Zhang #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 298*f41c9639SHawking Zhang #define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 299*f41c9639SHawking Zhang #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 300*f41c9639SHawking Zhang #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 301*f41c9639SHawking Zhang #define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe 302*f41c9639SHawking Zhang #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 303*f41c9639SHawking Zhang #define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L 304*f41c9639SHawking Zhang #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 305*f41c9639SHawking Zhang #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 306*f41c9639SHawking Zhang #define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L 307*f41c9639SHawking Zhang //XPB_CLG_CFG5 308*f41c9639SHawking Zhang #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 309*f41c9639SHawking Zhang #define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 310*f41c9639SHawking Zhang #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 311*f41c9639SHawking Zhang #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 312*f41c9639SHawking Zhang #define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe 313*f41c9639SHawking Zhang #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 314*f41c9639SHawking Zhang #define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L 315*f41c9639SHawking Zhang #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 316*f41c9639SHawking Zhang #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 317*f41c9639SHawking Zhang #define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L 318*f41c9639SHawking Zhang //XPB_CLG_CFG6 319*f41c9639SHawking Zhang #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 320*f41c9639SHawking Zhang #define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 321*f41c9639SHawking Zhang #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 322*f41c9639SHawking Zhang #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 323*f41c9639SHawking Zhang #define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe 324*f41c9639SHawking Zhang #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 325*f41c9639SHawking Zhang #define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L 326*f41c9639SHawking Zhang #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 327*f41c9639SHawking Zhang #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 328*f41c9639SHawking Zhang #define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L 329*f41c9639SHawking Zhang //XPB_CLG_CFG7 330*f41c9639SHawking Zhang #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 331*f41c9639SHawking Zhang #define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 332*f41c9639SHawking Zhang #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 333*f41c9639SHawking Zhang #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 334*f41c9639SHawking Zhang #define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe 335*f41c9639SHawking Zhang #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 336*f41c9639SHawking Zhang #define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L 337*f41c9639SHawking Zhang #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 338*f41c9639SHawking Zhang #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 339*f41c9639SHawking Zhang #define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L 340*f41c9639SHawking Zhang //XPB_CLG_EXTRA 341*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 342*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 343*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__VLD0__SHIFT 0xb 344*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc 345*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf 346*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 347*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a 348*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b 349*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL 350*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L 351*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L 352*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L 353*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L 354*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L 355*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L 356*f41c9639SHawking Zhang #define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L 357*f41c9639SHawking Zhang //XPB_CLG_EXTRA_MSK 358*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 359*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 360*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb 361*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 362*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL 363*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L 364*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L 365*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L 366*f41c9639SHawking Zhang //XPB_LB_ADDR 367*f41c9639SHawking Zhang #define XPB_LB_ADDR__CMP0__SHIFT 0x0 368*f41c9639SHawking Zhang #define XPB_LB_ADDR__MASK0__SHIFT 0xa 369*f41c9639SHawking Zhang #define XPB_LB_ADDR__CMP1__SHIFT 0x14 370*f41c9639SHawking Zhang #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 371*f41c9639SHawking Zhang #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 372*f41c9639SHawking Zhang #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 373*f41c9639SHawking Zhang #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 374*f41c9639SHawking Zhang #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 375*f41c9639SHawking Zhang //XPB_WCB_STS 376*f41c9639SHawking Zhang #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 377*f41c9639SHawking Zhang #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 378*f41c9639SHawking Zhang #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 379*f41c9639SHawking Zhang #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 380*f41c9639SHawking Zhang #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 381*f41c9639SHawking Zhang #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 382*f41c9639SHawking Zhang //XPB_HST_CFG 383*f41c9639SHawking Zhang #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 384*f41c9639SHawking Zhang #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 385*f41c9639SHawking Zhang //XPB_P2P_BAR_CFG 386*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 387*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 388*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 389*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 390*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 391*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 392*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 393*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 394*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 395*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 396*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 397*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 398*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 399*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 400*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 401*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 402*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 403*f41c9639SHawking Zhang #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 404*f41c9639SHawking Zhang //XPB_P2P_BAR0 405*f41c9639SHawking Zhang #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 406*f41c9639SHawking Zhang #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 407*f41c9639SHawking Zhang #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 408*f41c9639SHawking Zhang #define XPB_P2P_BAR0__VALID__SHIFT 0xc 409*f41c9639SHawking Zhang #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 410*f41c9639SHawking Zhang #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 411*f41c9639SHawking Zhang #define XPB_P2P_BAR0__RESERVE__SHIFT 0xf 412*f41c9639SHawking Zhang #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 413*f41c9639SHawking Zhang #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 414*f41c9639SHawking Zhang #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 415*f41c9639SHawking Zhang #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 416*f41c9639SHawking Zhang #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 417*f41c9639SHawking Zhang #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 418*f41c9639SHawking Zhang #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 419*f41c9639SHawking Zhang #define XPB_P2P_BAR0__RESERVE_MASK 0x00008000L 420*f41c9639SHawking Zhang #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 421*f41c9639SHawking Zhang //XPB_P2P_BAR1 422*f41c9639SHawking Zhang #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 423*f41c9639SHawking Zhang #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 424*f41c9639SHawking Zhang #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 425*f41c9639SHawking Zhang #define XPB_P2P_BAR1__VALID__SHIFT 0xc 426*f41c9639SHawking Zhang #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 427*f41c9639SHawking Zhang #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 428*f41c9639SHawking Zhang #define XPB_P2P_BAR1__RESERVE__SHIFT 0xf 429*f41c9639SHawking Zhang #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 430*f41c9639SHawking Zhang #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 431*f41c9639SHawking Zhang #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 432*f41c9639SHawking Zhang #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 433*f41c9639SHawking Zhang #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 434*f41c9639SHawking Zhang #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 435*f41c9639SHawking Zhang #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 436*f41c9639SHawking Zhang #define XPB_P2P_BAR1__RESERVE_MASK 0x00008000L 437*f41c9639SHawking Zhang #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 438*f41c9639SHawking Zhang //XPB_P2P_BAR2 439*f41c9639SHawking Zhang #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 440*f41c9639SHawking Zhang #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 441*f41c9639SHawking Zhang #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 442*f41c9639SHawking Zhang #define XPB_P2P_BAR2__VALID__SHIFT 0xc 443*f41c9639SHawking Zhang #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 444*f41c9639SHawking Zhang #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 445*f41c9639SHawking Zhang #define XPB_P2P_BAR2__RESERVE__SHIFT 0xf 446*f41c9639SHawking Zhang #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 447*f41c9639SHawking Zhang #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 448*f41c9639SHawking Zhang #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 449*f41c9639SHawking Zhang #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 450*f41c9639SHawking Zhang #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 451*f41c9639SHawking Zhang #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 452*f41c9639SHawking Zhang #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 453*f41c9639SHawking Zhang #define XPB_P2P_BAR2__RESERVE_MASK 0x00008000L 454*f41c9639SHawking Zhang #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 455*f41c9639SHawking Zhang //XPB_P2P_BAR3 456*f41c9639SHawking Zhang #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 457*f41c9639SHawking Zhang #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 458*f41c9639SHawking Zhang #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 459*f41c9639SHawking Zhang #define XPB_P2P_BAR3__VALID__SHIFT 0xc 460*f41c9639SHawking Zhang #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 461*f41c9639SHawking Zhang #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 462*f41c9639SHawking Zhang #define XPB_P2P_BAR3__RESERVE__SHIFT 0xf 463*f41c9639SHawking Zhang #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 464*f41c9639SHawking Zhang #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 465*f41c9639SHawking Zhang #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 466*f41c9639SHawking Zhang #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 467*f41c9639SHawking Zhang #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 468*f41c9639SHawking Zhang #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 469*f41c9639SHawking Zhang #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 470*f41c9639SHawking Zhang #define XPB_P2P_BAR3__RESERVE_MASK 0x00008000L 471*f41c9639SHawking Zhang #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 472*f41c9639SHawking Zhang //XPB_P2P_BAR4 473*f41c9639SHawking Zhang #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 474*f41c9639SHawking Zhang #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 475*f41c9639SHawking Zhang #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 476*f41c9639SHawking Zhang #define XPB_P2P_BAR4__VALID__SHIFT 0xc 477*f41c9639SHawking Zhang #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 478*f41c9639SHawking Zhang #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 479*f41c9639SHawking Zhang #define XPB_P2P_BAR4__RESERVE__SHIFT 0xf 480*f41c9639SHawking Zhang #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 481*f41c9639SHawking Zhang #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 482*f41c9639SHawking Zhang #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 483*f41c9639SHawking Zhang #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 484*f41c9639SHawking Zhang #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 485*f41c9639SHawking Zhang #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 486*f41c9639SHawking Zhang #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 487*f41c9639SHawking Zhang #define XPB_P2P_BAR4__RESERVE_MASK 0x00008000L 488*f41c9639SHawking Zhang #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 489*f41c9639SHawking Zhang //XPB_P2P_BAR5 490*f41c9639SHawking Zhang #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 491*f41c9639SHawking Zhang #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 492*f41c9639SHawking Zhang #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 493*f41c9639SHawking Zhang #define XPB_P2P_BAR5__VALID__SHIFT 0xc 494*f41c9639SHawking Zhang #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 495*f41c9639SHawking Zhang #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 496*f41c9639SHawking Zhang #define XPB_P2P_BAR5__RESERVE__SHIFT 0xf 497*f41c9639SHawking Zhang #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 498*f41c9639SHawking Zhang #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 499*f41c9639SHawking Zhang #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 500*f41c9639SHawking Zhang #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 501*f41c9639SHawking Zhang #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 502*f41c9639SHawking Zhang #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 503*f41c9639SHawking Zhang #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 504*f41c9639SHawking Zhang #define XPB_P2P_BAR5__RESERVE_MASK 0x00008000L 505*f41c9639SHawking Zhang #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 506*f41c9639SHawking Zhang //XPB_P2P_BAR6 507*f41c9639SHawking Zhang #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 508*f41c9639SHawking Zhang #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 509*f41c9639SHawking Zhang #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 510*f41c9639SHawking Zhang #define XPB_P2P_BAR6__VALID__SHIFT 0xc 511*f41c9639SHawking Zhang #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 512*f41c9639SHawking Zhang #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 513*f41c9639SHawking Zhang #define XPB_P2P_BAR6__RESERVE__SHIFT 0xf 514*f41c9639SHawking Zhang #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 515*f41c9639SHawking Zhang #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 516*f41c9639SHawking Zhang #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 517*f41c9639SHawking Zhang #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 518*f41c9639SHawking Zhang #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 519*f41c9639SHawking Zhang #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 520*f41c9639SHawking Zhang #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 521*f41c9639SHawking Zhang #define XPB_P2P_BAR6__RESERVE_MASK 0x00008000L 522*f41c9639SHawking Zhang #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 523*f41c9639SHawking Zhang //XPB_P2P_BAR7 524*f41c9639SHawking Zhang #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 525*f41c9639SHawking Zhang #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 526*f41c9639SHawking Zhang #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 527*f41c9639SHawking Zhang #define XPB_P2P_BAR7__VALID__SHIFT 0xc 528*f41c9639SHawking Zhang #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 529*f41c9639SHawking Zhang #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 530*f41c9639SHawking Zhang #define XPB_P2P_BAR7__RESERVE__SHIFT 0xf 531*f41c9639SHawking Zhang #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 532*f41c9639SHawking Zhang #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 533*f41c9639SHawking Zhang #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 534*f41c9639SHawking Zhang #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 535*f41c9639SHawking Zhang #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 536*f41c9639SHawking Zhang #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 537*f41c9639SHawking Zhang #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 538*f41c9639SHawking Zhang #define XPB_P2P_BAR7__RESERVE_MASK 0x00008000L 539*f41c9639SHawking Zhang #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 540*f41c9639SHawking Zhang //XPB_P2P_BAR_SETUP 541*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 542*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 543*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 544*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 545*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 546*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__RESERVE__SHIFT 0xf 547*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 548*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 549*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 550*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 551*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 552*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 553*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__RESERVE_MASK 0x00008000L 554*f41c9639SHawking Zhang #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 555*f41c9639SHawking Zhang //XPB_P2P_BAR_DELTA_ABOVE 556*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 557*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 558*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 559*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 560*f41c9639SHawking Zhang //XPB_P2P_BAR_DELTA_BELOW 561*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 562*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 563*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 564*f41c9639SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 565*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR0 566*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 567*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 568*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 569*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 570*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR1 571*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 572*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 573*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 574*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 575*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR2 576*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 577*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 578*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 579*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 580*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR3 581*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 582*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 583*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 584*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 585*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR4 586*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 587*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 588*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 589*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 590*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR5 591*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 592*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 593*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 594*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 595*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR6 596*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 597*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 598*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 599*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 600*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR7 601*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 602*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 603*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 604*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 605*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR8 606*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 607*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 608*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 609*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 610*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR9 611*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 612*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 613*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 614*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 615*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR10 616*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR10__VALID__SHIFT 0x0 617*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR10__ADDR__SHIFT 0x1 618*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR10__VALID_MASK 0x00000001L 619*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR10__ADDR_MASK 0xFFFFFFFEL 620*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR11 621*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR11__VALID__SHIFT 0x0 622*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR11__ADDR__SHIFT 0x1 623*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR11__VALID_MASK 0x00000001L 624*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR11__ADDR_MASK 0xFFFFFFFEL 625*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR12 626*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR12__VALID__SHIFT 0x0 627*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR12__ADDR__SHIFT 0x1 628*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR12__VALID_MASK 0x00000001L 629*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR12__ADDR_MASK 0xFFFFFFFEL 630*f41c9639SHawking Zhang //XPB_PEER_SYS_BAR13 631*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR13__VALID__SHIFT 0x0 632*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR13__ADDR__SHIFT 0x1 633*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR13__VALID_MASK 0x00000001L 634*f41c9639SHawking Zhang #define XPB_PEER_SYS_BAR13__ADDR_MASK 0xFFFFFFFEL 635*f41c9639SHawking Zhang //XPB_CLK_GAT 636*f41c9639SHawking Zhang #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 637*f41c9639SHawking Zhang #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 638*f41c9639SHawking Zhang #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 639*f41c9639SHawking Zhang #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 640*f41c9639SHawking Zhang #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 641*f41c9639SHawking Zhang #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 642*f41c9639SHawking Zhang #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 643*f41c9639SHawking Zhang #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 644*f41c9639SHawking Zhang #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 645*f41c9639SHawking Zhang #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 646*f41c9639SHawking Zhang //XPB_INTF_CFG 647*f41c9639SHawking Zhang #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 648*f41c9639SHawking Zhang #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 649*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 650*f41c9639SHawking Zhang #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK__SHIFT 0x17 651*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 652*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 653*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 654*f41c9639SHawking Zhang #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA__SHIFT 0x1f 655*f41c9639SHawking Zhang #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 656*f41c9639SHawking Zhang #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 657*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 658*f41c9639SHawking Zhang #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK_MASK 0x00800000L 659*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 660*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 661*f41c9639SHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 662*f41c9639SHawking Zhang #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA_MASK 0x80000000L 663*f41c9639SHawking Zhang //XPB_INTF_STS 664*f41c9639SHawking Zhang #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 665*f41c9639SHawking Zhang #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 666*f41c9639SHawking Zhang #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 667*f41c9639SHawking Zhang #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 668*f41c9639SHawking Zhang #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 669*f41c9639SHawking Zhang #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 670*f41c9639SHawking Zhang #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 671*f41c9639SHawking Zhang #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 672*f41c9639SHawking Zhang #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 673*f41c9639SHawking Zhang #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 674*f41c9639SHawking Zhang #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 675*f41c9639SHawking Zhang #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 676*f41c9639SHawking Zhang #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 677*f41c9639SHawking Zhang #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 678*f41c9639SHawking Zhang //XPB_PIPE_STS 679*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 680*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 681*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 682*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 683*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 684*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 685*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 686*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 687*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 688*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 689*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 690*f41c9639SHawking Zhang #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 691*f41c9639SHawking Zhang #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 692*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 693*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 694*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 695*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 696*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 697*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 698*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 699*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 700*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 701*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 702*f41c9639SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 703*f41c9639SHawking Zhang #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 704*f41c9639SHawking Zhang #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 705*f41c9639SHawking Zhang //XPB_SUB_CTRL 706*f41c9639SHawking Zhang #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 707*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 708*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 709*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 710*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 711*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 712*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 713*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 714*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 715*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 716*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 717*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 718*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 719*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 720*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 721*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 722*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 723*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 724*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 725*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 726*f41c9639SHawking Zhang #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 727*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 728*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 729*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 730*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 731*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 732*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 733*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 734*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 735*f41c9639SHawking Zhang #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 736*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 737*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 738*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 739*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 740*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 741*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 742*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 743*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 744*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 745*f41c9639SHawking Zhang #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 746*f41c9639SHawking Zhang //XPB_MAP_INVERT_FLUSH_NUM_LSB 747*f41c9639SHawking Zhang #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 748*f41c9639SHawking Zhang #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 749*f41c9639SHawking Zhang //XPB_PERF_KNOBS 750*f41c9639SHawking Zhang #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 751*f41c9639SHawking Zhang #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 752*f41c9639SHawking Zhang #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 753*f41c9639SHawking Zhang #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 754*f41c9639SHawking Zhang #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 755*f41c9639SHawking Zhang #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 756*f41c9639SHawking Zhang //XPB_STICKY 757*f41c9639SHawking Zhang #define XPB_STICKY__BITS__SHIFT 0x0 758*f41c9639SHawking Zhang #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 759*f41c9639SHawking Zhang //XPB_STICKY_W1C 760*f41c9639SHawking Zhang #define XPB_STICKY_W1C__BITS__SHIFT 0x0 761*f41c9639SHawking Zhang #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 762*f41c9639SHawking Zhang //XPB_MISC_CFG 763*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 764*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 765*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 766*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 767*f41c9639SHawking Zhang #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 768*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 769*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 770*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 771*f41c9639SHawking Zhang #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 772*f41c9639SHawking Zhang #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 773*f41c9639SHawking Zhang //XPB_INTF_CFG2 774*f41c9639SHawking Zhang #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 775*f41c9639SHawking Zhang #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 776*f41c9639SHawking Zhang //XPB_CLG_EXTRA_RD 777*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 778*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 779*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 780*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 781*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 782*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 783*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 784*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 785*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 786*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 787*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 788*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 789*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 790*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 791*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 792*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 793*f41c9639SHawking Zhang //XPB_CLG_EXTRA_MSK_RD 794*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 795*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 796*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 797*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 798*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 799*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 800*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 801*f41c9639SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 802*f41c9639SHawking Zhang //XPB_CLG_GFX_MATCH 803*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 804*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 805*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc 806*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 807*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 808*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 809*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a 810*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b 811*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL 812*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 813*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L 814*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 815*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L 816*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L 817*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L 818*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L 819*f41c9639SHawking Zhang //XPB_CLG_GFX_MATCH_MSK 820*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 821*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 822*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 823*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 824*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 825*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 826*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 827*f41c9639SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 828*f41c9639SHawking Zhang //XPB_CLG_MM_MATCH 829*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 830*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 831*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0xc 832*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0xd 833*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL 834*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 835*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x00001000L 836*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x00002000L 837*f41c9639SHawking Zhang //XPB_CLG_MM_MATCH_MSK 838*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 839*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 840*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 841*f41c9639SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 842*f41c9639SHawking Zhang //XPB_CLG_GUS_MATCH 843*f41c9639SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_ID__SHIFT 0x0 844*f41c9639SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD__SHIFT 0x6 845*f41c9639SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_ID_MASK 0x0000003FL 846*f41c9639SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD_MASK 0x00000040L 847*f41c9639SHawking Zhang //XPB_CLG_GUS_MATCH_MSK 848*f41c9639SHawking Zhang #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 849*f41c9639SHawking Zhang #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 850*f41c9639SHawking Zhang 851*f41c9639SHawking Zhang 852*f41c9639SHawking Zhang // addressBlock: athub_rpbdec 853*f41c9639SHawking Zhang //RPB_PASSPW_CONF 854*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 855*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 856*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE__SHIFT 0x2 857*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_EN__SHIFT 0x3 858*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE__SHIFT 0x4 859*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_EN__SHIFT 0x5 860*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE__SHIFT 0x6 861*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_EN__SHIFT 0x7 862*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE__SHIFT 0x8 863*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_EN__SHIFT 0x9 864*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0xa 865*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xb 866*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE__SHIFT 0xc 867*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 868*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0xe 869*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0xf 870*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x10 871*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x11 872*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x12 873*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0x13 874*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0x14 875*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0x15 876*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x16 877*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x17 878*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 879*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 880*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_MASK 0x00000004L 881*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_EN_MASK 0x00000008L 882*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_MASK 0x00000010L 883*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_EN_MASK 0x00000020L 884*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_MASK 0x00000040L 885*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_EN_MASK 0x00000080L 886*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_MASK 0x00000100L 887*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_EN_MASK 0x00000200L 888*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000400L 889*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00000800L 890*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_MASK 0x00001000L 891*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 892*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00004000L 893*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00008000L 894*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00010000L 895*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00020000L 896*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00040000L 897*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00080000L 898*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00100000L 899*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00200000L 900*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00400000L 901*f41c9639SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00800000L 902*f41c9639SHawking Zhang //RPB_BLOCKLEVEL_CONF 903*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 904*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x2 905*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL__SHIFT 0x3 906*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL__SHIFT 0x5 907*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x7 908*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x9 909*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0xb 910*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xd 911*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xe 912*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 913*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0x11 914*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x13 915*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 916*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00000004L 917*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL_MASK 0x00000018L 918*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL_MASK 0x00000060L 919*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000180L 920*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x00000600L 921*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00001800L 922*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00002000L 923*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x0000C000L 924*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 925*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00060000L 926*f41c9639SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00080000L 927*f41c9639SHawking Zhang //RPB_TAG_CONF 928*f41c9639SHawking Zhang #define RPB_TAG_CONF__RPB_IO_RD__SHIFT 0x0 929*f41c9639SHawking Zhang #define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0xa 930*f41c9639SHawking Zhang #define RPB_TAG_CONF__RPB_IO_RD_MASK 0x000003FFL 931*f41c9639SHawking Zhang #define RPB_TAG_CONF__RPB_IO_WR_MASK 0x000FFC00L 932*f41c9639SHawking Zhang //RPB_ARB_CNTL 933*f41c9639SHawking Zhang #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 934*f41c9639SHawking Zhang #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 935*f41c9639SHawking Zhang #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 936*f41c9639SHawking Zhang #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 937*f41c9639SHawking Zhang #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 938*f41c9639SHawking Zhang #define RPB_ARB_CNTL__RPB_VC0_CRD__SHIFT 0x1a 939*f41c9639SHawking Zhang #define RPB_ARB_CNTL__DISABLE_FED__SHIFT 0x1f 940*f41c9639SHawking Zhang #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 941*f41c9639SHawking Zhang #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 942*f41c9639SHawking Zhang #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 943*f41c9639SHawking Zhang #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 944*f41c9639SHawking Zhang #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 945*f41c9639SHawking Zhang #define RPB_ARB_CNTL__RPB_VC0_CRD_MASK 0x7C000000L 946*f41c9639SHawking Zhang #define RPB_ARB_CNTL__DISABLE_FED_MASK 0x80000000L 947*f41c9639SHawking Zhang //RPB_ARB_CNTL2 948*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 949*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 950*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 951*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__RPB_VC1_CRD__SHIFT 0x18 952*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 953*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 954*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 955*f41c9639SHawking Zhang #define RPB_ARB_CNTL2__RPB_VC1_CRD_MASK 0x1F000000L 956*f41c9639SHawking Zhang //RPB_BIF_CNTL 957*f41c9639SHawking Zhang #define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 958*f41c9639SHawking Zhang #define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 959*f41c9639SHawking Zhang #define RPB_BIF_CNTL__VC2_SWITCH_NUM__SHIFT 0x10 960*f41c9639SHawking Zhang #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN__SHIFT 0x18 961*f41c9639SHawking Zhang #define RPB_BIF_CNTL__TR_QOS_VC__SHIFT 0x19 962*f41c9639SHawking Zhang #define RPB_BIF_CNTL__FATAL_ERROR_ENABLE__SHIFT 0x1c 963*f41c9639SHawking Zhang #define RPB_BIF_CNTL__RESERVE__SHIFT 0x1d 964*f41c9639SHawking Zhang #define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 965*f41c9639SHawking Zhang #define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 966*f41c9639SHawking Zhang #define RPB_BIF_CNTL__VC2_SWITCH_NUM_MASK 0x00FF0000L 967*f41c9639SHawking Zhang #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN_MASK 0x01000000L 968*f41c9639SHawking Zhang #define RPB_BIF_CNTL__TR_QOS_VC_MASK 0x0E000000L 969*f41c9639SHawking Zhang #define RPB_BIF_CNTL__FATAL_ERROR_ENABLE_MASK 0x10000000L 970*f41c9639SHawking Zhang #define RPB_BIF_CNTL__RESERVE_MASK 0xE0000000L 971*f41c9639SHawking Zhang //RPB_BIF_CNTL2 972*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__ARB_MODE__SHIFT 0x0 973*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__DRAIN_VC_NUM__SHIFT 0x1 974*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__SWITCH_ENABLE__SHIFT 0x3 975*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__SWITCH_THRESHOLD__SHIFT 0x4 976*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__PAGE_PRI_EN__SHIFT 0xc 977*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__VC5_TR_PRI_EN__SHIFT 0xd 978*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__VC0_TR_PRI_EN__SHIFT 0xe 979*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE__SHIFT 0xf 980*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__PARITY_CHECK_EN__SHIFT 0x10 981*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN__SHIFT 0x11 982*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__RESERVE__SHIFT 0x19 983*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__ARB_MODE_MASK 0x00000001L 984*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__DRAIN_VC_NUM_MASK 0x00000006L 985*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__SWITCH_ENABLE_MASK 0x00000008L 986*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__SWITCH_THRESHOLD_MASK 0x00000FF0L 987*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__PAGE_PRI_EN_MASK 0x00001000L 988*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__VC5_TR_PRI_EN_MASK 0x00002000L 989*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__VC0_TR_PRI_EN_MASK 0x00004000L 990*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE_MASK 0x00008000L 991*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__PARITY_CHECK_EN_MASK 0x00010000L 992*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN_MASK 0x00020000L 993*f41c9639SHawking Zhang #define RPB_BIF_CNTL2__RESERVE_MASK 0xFE000000L 994*f41c9639SHawking Zhang //ATHUB_MISC_CNTL 995*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x0 996*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x6 997*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x7 998*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x8 999*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x9 1000*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__ALWAYS_BUSY__SHIFT 0xf 1001*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x10 1002*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x11 1003*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__RPB_BUSY__SHIFT 0x12 1004*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__XPB_BUSY__SHIFT 0x13 1005*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__ATS_BUSY__SHIFT 0x14 1006*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__SDPNCS_BUSY__SHIFT 0x15 1007*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__DFPORT_BUSY__SHIFT 0x16 1008*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__SWITCH_CNTL__SHIFT 0x17 1009*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__LS_DELAY_ENABLE__SHIFT 0x18 1010*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__LS_DELAY_TIME__SHIFT 0x19 1011*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__RESETB_PG_CLK_GATING_ENABLE__SHIFT 0x1e 1012*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__RM_VALID_ENABLE__SHIFT 0x1f 1013*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x0000003FL 1014*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00000040L 1015*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00000080L 1016*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00000100L 1017*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x00007E00L 1018*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__ALWAYS_BUSY_MASK 0x00008000L 1019*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x00010000L 1020*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x00020000L 1021*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__RPB_BUSY_MASK 0x00040000L 1022*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__XPB_BUSY_MASK 0x00080000L 1023*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__ATS_BUSY_MASK 0x00100000L 1024*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__SDPNCS_BUSY_MASK 0x00200000L 1025*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__DFPORT_BUSY_MASK 0x00400000L 1026*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__SWITCH_CNTL_MASK 0x00800000L 1027*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__LS_DELAY_ENABLE_MASK 0x01000000L 1028*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__LS_DELAY_TIME_MASK 0x3E000000L 1029*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__RESETB_PG_CLK_GATING_ENABLE_MASK 0x40000000L 1030*f41c9639SHawking Zhang #define ATHUB_MISC_CNTL__RM_VALID_ENABLE_MASK 0x80000000L 1031*f41c9639SHawking Zhang //ATHUB_MEM_POWER_LS 1032*f41c9639SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 1033*f41c9639SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 1034*f41c9639SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 1035*f41c9639SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x0007FFC0L 1036*f41c9639SHawking Zhang //RPB_SDPPORT_CNTL 1037*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 1038*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 1039*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 1040*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 1041*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 1042*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 1043*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__RESERVE1__SHIFT 0xa 1044*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 1045*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 1046*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 1047*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 1048*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 1049*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 1050*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__CG_BUSY_PORT__SHIFT 0x1c 1051*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__RESERVE__SHIFT 0x1d 1052*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 1053*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 1054*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 1055*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 1056*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 1057*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 1058*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__RESERVE1_MASK 0x003FFC00L 1059*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 1060*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 1061*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 1062*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 1063*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 1064*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 1065*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__CG_BUSY_PORT_MASK 0x10000000L 1066*f41c9639SHawking Zhang #define RPB_SDPPORT_CNTL__RESERVE_MASK 0xE0000000L 1067*f41c9639SHawking Zhang //RPB_NBIF_SDPPORT_CNTL 1068*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD__SHIFT 0x0 1069*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD__SHIFT 0x8 1070*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD__SHIFT 0x10 1071*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD__SHIFT 0x18 1072*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD_MASK 0x000000FFL 1073*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD_MASK 0x0000FF00L 1074*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD_MASK 0x00FF0000L 1075*f41c9639SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD_MASK 0xFF000000L 1076*f41c9639SHawking Zhang //RPB_DEINTRLV_COMBINE_CNTL 1077*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 1078*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 1079*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 1080*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD__SHIFT 0x6 1081*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN__SHIFT 0xe 1082*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__RESERVE__SHIFT 0xf 1083*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 1084*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 1085*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 1086*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD_MASK 0x00003FC0L 1087*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN_MASK 0x00004000L 1088*f41c9639SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__RESERVE_MASK 0xFFFF8000L 1089*f41c9639SHawking Zhang //RPB_VC_SWITCH_RDWR 1090*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 1091*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 1092*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 1093*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12 1094*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__CENTER_MARGIN__SHIFT 0x1a 1095*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 1096*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 1097*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 1098*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L 1099*f41c9639SHawking Zhang #define RPB_VC_SWITCH_RDWR__CENTER_MARGIN_MASK 0xFC000000L 1100*f41c9639SHawking Zhang //RPB_PERF_COUNTER_CNTL 1101*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1102*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 1103*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 1104*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 1105*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 1106*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 1107*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe 1108*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 1109*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 1110*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 1111*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L 1112*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L 1113*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L 1114*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L 1115*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L 1116*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L 1117*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L 1118*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L 1119*f41c9639SHawking Zhang //RPB_PERF_COUNTER_STATUS 1120*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 1121*f41c9639SHawking Zhang #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xFFFFFFFFL 1122*f41c9639SHawking Zhang //RPB_PERFCOUNTER_LO 1123*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1124*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1125*f41c9639SHawking Zhang //RPB_PERFCOUNTER_HI 1126*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1127*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1128*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1129*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1130*f41c9639SHawking Zhang //RPB_PERFCOUNTER0_CFG 1131*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1132*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1133*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1134*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1135*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1136*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1137*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1138*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1139*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1140*f41c9639SHawking Zhang #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1141*f41c9639SHawking Zhang //RPB_PERFCOUNTER1_CFG 1142*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1143*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1144*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1145*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1146*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1147*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1148*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1149*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1150*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1151*f41c9639SHawking Zhang #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1152*f41c9639SHawking Zhang //RPB_PERFCOUNTER2_CFG 1153*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1154*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1155*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1156*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1157*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1158*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1159*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1160*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1161*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1162*f41c9639SHawking Zhang #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1163*f41c9639SHawking Zhang //RPB_PERFCOUNTER3_CFG 1164*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 1165*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 1166*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 1167*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 1168*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 1169*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 1170*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 1171*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 1172*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 1173*f41c9639SHawking Zhang #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 1174*f41c9639SHawking Zhang //RPB_PERFCOUNTER_RSLT_CNTL 1175*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1176*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1177*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1178*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1179*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1180*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1181*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1182*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1183*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1184*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1185*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1186*f41c9639SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1187*f41c9639SHawking Zhang //RPB_ATS_CNTL3 1188*f41c9639SHawking Zhang #define RPB_ATS_CNTL3__RPB_ATS_VC5_TR__SHIFT 0x0 1189*f41c9639SHawking Zhang #define RPB_ATS_CNTL3__RPB_ATS_VC0_TR__SHIFT 0x9 1190*f41c9639SHawking Zhang #define RPB_ATS_CNTL3__RPB_ATS_PR__SHIFT 0x12 1191*f41c9639SHawking Zhang #define RPB_ATS_CNTL3__RPB_ATS_VC5_TR_MASK 0x000001FFL 1192*f41c9639SHawking Zhang #define RPB_ATS_CNTL3__RPB_ATS_VC0_TR_MASK 0x0003FE00L 1193*f41c9639SHawking Zhang #define RPB_ATS_CNTL3__RPB_ATS_PR_MASK 0x07FC0000L 1194*f41c9639SHawking Zhang //RPB_DF_SDPPORT_CNTL 1195*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD__SHIFT 0x0 1196*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD__SHIFT 0x6 1197*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0xc 1198*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE__SHIFT 0x10 1199*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_INSERT_PARITY_ERR__SHIFT 0x11 1200*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_BUSY_INCLUDE_CONN__SHIFT 0x12 1201*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_ORIG_ACK_TIMER__SHIFT 0x13 1202*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__RESERVE__SHIFT 0x1b 1203*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD_MASK 0x0000003FL 1204*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD_MASK 0x00000FC0L 1205*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0x0000F000L 1206*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE_MASK 0x00010000L 1207*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_INSERT_PARITY_ERR_MASK 0x00020000L 1208*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_BUSY_INCLUDE_CONN_MASK 0x00040000L 1209*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_ORIG_ACK_TIMER_MASK 0x07F80000L 1210*f41c9639SHawking Zhang #define RPB_DF_SDPPORT_CNTL__RESERVE_MASK 0xF8000000L 1211*f41c9639SHawking Zhang //RPB_ATS_CNTL 1212*f41c9639SHawking Zhang #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 1213*f41c9639SHawking Zhang #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 1214*f41c9639SHawking Zhang #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 1215*f41c9639SHawking Zhang #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 1216*f41c9639SHawking Zhang #define RPB_ATS_CNTL__ATCTR_VC0_SWITCH_NUM__SHIFT 0xf 1217*f41c9639SHawking Zhang #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 1218*f41c9639SHawking Zhang #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 1219*f41c9639SHawking Zhang #define RPB_ATS_CNTL__MM_TRANS_VC5_ENABLE__SHIFT 0x19 1220*f41c9639SHawking Zhang #define RPB_ATS_CNTL__GC_TRANS_VC5_ENABLE__SHIFT 0x1a 1221*f41c9639SHawking Zhang #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 1222*f41c9639SHawking Zhang #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 1223*f41c9639SHawking Zhang #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 1224*f41c9639SHawking Zhang #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 1225*f41c9639SHawking Zhang #define RPB_ATS_CNTL__ATCTR_VC0_SWITCH_NUM_MASK 0x00078000L 1226*f41c9639SHawking Zhang #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 1227*f41c9639SHawking Zhang #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 1228*f41c9639SHawking Zhang #define RPB_ATS_CNTL__MM_TRANS_VC5_ENABLE_MASK 0x02000000L 1229*f41c9639SHawking Zhang #define RPB_ATS_CNTL__GC_TRANS_VC5_ENABLE_MASK 0x04000000L 1230*f41c9639SHawking Zhang //RPB_ATS_CNTL2 1231*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_CMD__SHIFT 0x0 1232*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x6 1233*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0xc 1234*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0x12 1235*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0x15 1236*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x18 1237*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__RPB_VC5_CRD__SHIFT 0x1a 1238*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_CMD_MASK 0x0000003FL 1239*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x00000FC0L 1240*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x0003F000L 1241*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x001C0000L 1242*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00E00000L 1243*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x03000000L 1244*f41c9639SHawking Zhang #define RPB_ATS_CNTL2__RPB_VC5_CRD_MASK 0x7C000000L 1245*f41c9639SHawking Zhang 1246*f41c9639SHawking Zhang #endif 1247