1*1b0f0f7bSHawking Zhang /* 2*1b0f0f7bSHawking Zhang * Copyright 2022 Advanced Micro Devices, Inc. 3*1b0f0f7bSHawking Zhang * 4*1b0f0f7bSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*1b0f0f7bSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*1b0f0f7bSHawking Zhang * to deal in the Software without restriction, including without limitation 7*1b0f0f7bSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*1b0f0f7bSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*1b0f0f7bSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*1b0f0f7bSHawking Zhang * 11*1b0f0f7bSHawking Zhang * The above copyright notice and this permission notice shall be included in 12*1b0f0f7bSHawking Zhang * all copies or substantial portions of the Software. 13*1b0f0f7bSHawking Zhang * 14*1b0f0f7bSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*1b0f0f7bSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*1b0f0f7bSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*1b0f0f7bSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*1b0f0f7bSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*1b0f0f7bSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*1b0f0f7bSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*1b0f0f7bSHawking Zhang * 22*1b0f0f7bSHawking Zhang */ 23*1b0f0f7bSHawking Zhang #ifndef _athub_1_8_0_SH_MASK_HEADER 24*1b0f0f7bSHawking Zhang #define _athub_1_8_0_SH_MASK_HEADER 25*1b0f0f7bSHawking Zhang 26*1b0f0f7bSHawking Zhang 27*1b0f0f7bSHawking Zhang // addressBlock: aid_athub_atsdec 28*1b0f0f7bSHawking Zhang //ATC_ATS_CNTL 29*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 30*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 31*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 32*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 33*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10 34*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 35*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 36*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 37*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 38*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L 39*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000F0000L 40*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L 41*1b0f0f7bSHawking Zhang //ATC_ATS_CNTL2 42*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC5TR__SHIFT 0x0 43*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC0TR__SHIFT 0x8 44*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV__SHIFT 0x10 45*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__TRANSLATION_STALL__SHIFT 0x18 46*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__GC_TRANS_VC5_ENABLE__SHIFT 0x19 47*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__MM_TRANS_VC5_ENABLE__SHIFT 0x1a 48*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__RESERVED__SHIFT 0x1b 49*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC5TR_MASK 0x000000FFL 50*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC0TR_MASK 0x0000FF00L 51*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV_MASK 0x00FF0000L 52*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__TRANSLATION_STALL_MASK 0x01000000L 53*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__GC_TRANS_VC5_ENABLE_MASK 0x02000000L 54*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__MM_TRANS_VC5_ENABLE_MASK 0x04000000L 55*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL2__RESERVED_MASK 0xF8000000L 56*1b0f0f7bSHawking Zhang //ATC_ATS_CNTL3 57*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL3__RESERVED__SHIFT 0x0 58*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL3__RESERVED_MASK 0xFFFFFFFFL 59*1b0f0f7bSHawking Zhang //ATC_ATS_CNTL4 60*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL4__RESERVED__SHIFT 0x0 61*1b0f0f7bSHawking Zhang #define ATC_ATS_CNTL4__RESERVED_MASK 0xFFFFFFFFL 62*1b0f0f7bSHawking Zhang //ATC_ATS_MISC_CNTL 63*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_HOST__SHIFT 0x10 64*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_GUEST__SHIFT 0x11 65*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__DEBUG_COLLISION__SHIFT 0x12 66*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__EFFECTIVE_TRANS_WORK_QUEUE__SHIFT 0x13 67*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__TRANS_RESP_NULL_PASID_SEL__SHIFT 0x1d 68*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__RESERVED__SHIFT 0x1e 69*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_HOST_MASK 0x00010000L 70*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_GUEST_MASK 0x00020000L 71*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__DEBUG_COLLISION_MASK 0x00040000L 72*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__EFFECTIVE_TRANS_WORK_QUEUE_MASK 0x1FF80000L 73*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__TRANS_RESP_NULL_PASID_SEL_MASK 0x20000000L 74*1b0f0f7bSHawking Zhang #define ATC_ATS_MISC_CNTL__RESERVED_MASK 0xC0000000L 75*1b0f0f7bSHawking Zhang //ATC_ATS_STATUS 76*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__BUSY__SHIFT 0x0 77*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 78*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 79*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__FED_IND__SHIFT 0x3 80*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__BUSY_MASK 0x00000001L 81*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L 82*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L 83*1b0f0f7bSHawking Zhang #define ATC_ATS_STATUS__FED_IND_MASK 0x00000008L 84*1b0f0f7bSHawking Zhang //ATC_PERFCOUNTER0_CFG 85*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 86*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 87*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 88*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 89*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 90*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 91*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 92*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 93*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 94*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 95*1b0f0f7bSHawking Zhang //ATC_PERFCOUNTER1_CFG 96*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 97*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 98*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 99*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 100*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 101*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 102*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 103*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 104*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 105*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 106*1b0f0f7bSHawking Zhang //ATC_PERFCOUNTER2_CFG 107*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 108*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 109*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 110*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 111*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 112*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 113*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 114*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 115*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 116*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 117*1b0f0f7bSHawking Zhang //ATC_PERFCOUNTER3_CFG 118*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 119*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 120*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 121*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 122*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 123*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 124*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 125*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 126*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 127*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 128*1b0f0f7bSHawking Zhang //ATC_PERFCOUNTER_RSLT_CNTL 129*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 130*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 131*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 132*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 133*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 134*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 135*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 136*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 137*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 138*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 139*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 140*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 141*1b0f0f7bSHawking Zhang //ATC_PERFCOUNTER_LO 142*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 143*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 144*1b0f0f7bSHawking Zhang //ATC_PERFCOUNTER_HI 145*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 146*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 147*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 148*1b0f0f7bSHawking Zhang #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 149*1b0f0f7bSHawking Zhang //ATC_ATS_FAULT_CNTL 150*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 151*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 152*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 153*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL 154*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L 155*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L 156*1b0f0f7bSHawking Zhang //ATC_ATS_FAULT_STATUS_INFO 157*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 158*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__VMID_ALL__SHIFT 0x9 159*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 160*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf 161*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 162*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 163*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 164*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 165*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 166*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PHYSICAL_ADDR_HIGH__SHIFT 0x1c 167*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL 168*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__VMID_ALL_MASK 0x00000200L 169*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L 170*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L 171*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L 172*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L 173*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L 174*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L 175*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L 176*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PHYSICAL_ADDR_HIGH_MASK 0xF0000000L 177*1b0f0f7bSHawking Zhang //ATC_ATS_FAULT_STATUS_INFO2 178*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 179*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 180*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__L2NUM__SHIFT 0x9 181*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX1__SHIFT 0xd 182*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX2__SHIFT 0x13 183*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX3__SHIFT 0x19 184*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L 185*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL 186*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__L2NUM_MASK 0x00001E00L 187*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX1_MASK 0x0007E000L 188*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX2_MASK 0x01F80000L 189*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX3_MASK 0x7E000000L 190*1b0f0f7bSHawking Zhang //ATC_ATS_FAULT_STATUS_INFO3 191*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX4__SHIFT 0x0 192*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX5__SHIFT 0x6 193*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX6__SHIFT 0xc 194*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX7__SHIFT 0x12 195*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_MM0__SHIFT 0x18 196*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX4_MASK 0x0000003FL 197*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX5_MASK 0x00000FC0L 198*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX6_MASK 0x0003F000L 199*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX7_MASK 0x00FC0000L 200*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_MM0_MASK 0x3F000000L 201*1b0f0f7bSHawking Zhang //ATC_ATS_FAULT_STATUS_INFO4 202*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM1__SHIFT 0x0 203*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM2__SHIFT 0x6 204*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM3__SHIFT 0xc 205*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM1_MASK 0x0000003FL 206*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM2_MASK 0x00000FC0L 207*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM3_MASK 0x0003F000L 208*1b0f0f7bSHawking Zhang //ATC_ATS_FAULT_STATUS_ADDR 209*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 210*1b0f0f7bSHawking Zhang #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL 211*1b0f0f7bSHawking Zhang //ATC_ATS_DEFAULT_PAGE_LOW 212*1b0f0f7bSHawking Zhang #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 213*1b0f0f7bSHawking Zhang #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL 214*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL 215*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 216*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 217*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 218*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 219*1b0f0f7bSHawking Zhang //ATHUB_PCIE_PASID_CNTL 220*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 221*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 222*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 223*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L 224*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L 225*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L 226*1b0f0f7bSHawking Zhang //ATHUB_PCIE_PAGE_REQ_CNTL 227*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 228*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 229*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L 230*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L 231*1b0f0f7bSHawking Zhang //ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 232*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 233*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL 234*1b0f0f7bSHawking Zhang //ATHUB_COMMAND 235*1b0f0f7bSHawking Zhang #define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 236*1b0f0f7bSHawking Zhang #define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L 237*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_0 238*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 239*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 240*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_1 241*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 242*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 243*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_2 244*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 245*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 246*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_3 247*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 248*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 249*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_4 250*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 251*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 252*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_5 253*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 254*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 255*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_6 256*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 257*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 258*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_7 259*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 260*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 261*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_8 262*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 263*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 264*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_9 265*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 266*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 267*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_10 268*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 269*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 270*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_11 271*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 272*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 273*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_12 274*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 275*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 276*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_13 277*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 278*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 279*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_14 280*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 281*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 282*1b0f0f7bSHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_15 283*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 284*1b0f0f7bSHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 285*1b0f0f7bSHawking Zhang //ATHUB_SHARED_VIRT_RESET_REQ 286*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 287*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 288*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 289*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 290*1b0f0f7bSHawking Zhang //ATHUB_SHARED_ACTIVE_FCN_ID 291*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 292*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 293*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 294*1b0f0f7bSHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 295*1b0f0f7bSHawking Zhang //ATC_ATS_SDPPORT_CNTL 296*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 297*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 298*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 299*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_REISSUE_CREDIT__SHIFT 0x7 300*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_ENABLE_DISRUPT_FULLDIS__SHIFT 0x8 301*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x9 302*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0xa 303*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0xb 304*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xf 305*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_RDY_MODE__SHIFT 0x10 306*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_REISSUE_CREDIT__SHIFT 0x11 307*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_ENABLE_DISRUPT_FULLDIS__SHIFT 0x12 308*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_INVALREQ_RDRSPSTATUS_CNTL__SHIFT 0x13 309*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x16 310*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 311*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 312*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 313*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 314*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 315*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x1c 316*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x1d 317*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x1e 318*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x1f 319*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L 320*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L 321*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L 322*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_REISSUE_CREDIT_MASK 0x00000080L 323*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_ENABLE_DISRUPT_FULLDIS_MASK 0x00000100L 324*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000200L 325*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000400L 326*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00007800L 327*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00008000L 328*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_RDY_MODE_MASK 0x00010000L 329*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_REISSUE_CREDIT_MASK 0x00020000L 330*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_ENABLE_DISRUPT_FULLDIS_MASK 0x00040000L 331*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_INVALREQ_RDRSPSTATUS_CNTL_MASK 0x00380000L 332*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 333*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 334*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 335*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 336*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 337*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 338*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x10000000L 339*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x20000000L 340*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x40000000L 341*1b0f0f7bSHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x80000000L 342*1b0f0f7bSHawking Zhang //ATC_VMID_PASID_MAPPING_UPDATE_STATUS 343*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 344*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 345*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 346*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 347*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 348*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 349*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 350*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 351*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 352*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 353*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 354*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb 355*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc 356*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd 357*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe 358*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf 359*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L 360*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L 361*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L 362*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L 363*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L 364*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L 365*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L 366*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L 367*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L 368*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L 369*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L 370*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L 371*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L 372*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L 373*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L 374*1b0f0f7bSHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L 375*1b0f0f7bSHawking Zhang //ATC_VMID0_PASID_MAPPING 376*1b0f0f7bSHawking Zhang #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 377*1b0f0f7bSHawking Zhang #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 378*1b0f0f7bSHawking Zhang #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f 379*1b0f0f7bSHawking Zhang #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL 380*1b0f0f7bSHawking Zhang #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 381*1b0f0f7bSHawking Zhang #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L 382*1b0f0f7bSHawking Zhang //ATC_VMID1_PASID_MAPPING 383*1b0f0f7bSHawking Zhang #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 384*1b0f0f7bSHawking Zhang #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 385*1b0f0f7bSHawking Zhang #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f 386*1b0f0f7bSHawking Zhang #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL 387*1b0f0f7bSHawking Zhang #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 388*1b0f0f7bSHawking Zhang #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L 389*1b0f0f7bSHawking Zhang //ATC_VMID2_PASID_MAPPING 390*1b0f0f7bSHawking Zhang #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 391*1b0f0f7bSHawking Zhang #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 392*1b0f0f7bSHawking Zhang #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f 393*1b0f0f7bSHawking Zhang #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL 394*1b0f0f7bSHawking Zhang #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 395*1b0f0f7bSHawking Zhang #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L 396*1b0f0f7bSHawking Zhang //ATC_VMID3_PASID_MAPPING 397*1b0f0f7bSHawking Zhang #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 398*1b0f0f7bSHawking Zhang #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 399*1b0f0f7bSHawking Zhang #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f 400*1b0f0f7bSHawking Zhang #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL 401*1b0f0f7bSHawking Zhang #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 402*1b0f0f7bSHawking Zhang #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L 403*1b0f0f7bSHawking Zhang //ATC_VMID4_PASID_MAPPING 404*1b0f0f7bSHawking Zhang #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 405*1b0f0f7bSHawking Zhang #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 406*1b0f0f7bSHawking Zhang #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f 407*1b0f0f7bSHawking Zhang #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL 408*1b0f0f7bSHawking Zhang #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 409*1b0f0f7bSHawking Zhang #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L 410*1b0f0f7bSHawking Zhang //ATC_VMID5_PASID_MAPPING 411*1b0f0f7bSHawking Zhang #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 412*1b0f0f7bSHawking Zhang #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 413*1b0f0f7bSHawking Zhang #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f 414*1b0f0f7bSHawking Zhang #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL 415*1b0f0f7bSHawking Zhang #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 416*1b0f0f7bSHawking Zhang #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L 417*1b0f0f7bSHawking Zhang //ATC_VMID6_PASID_MAPPING 418*1b0f0f7bSHawking Zhang #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 419*1b0f0f7bSHawking Zhang #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 420*1b0f0f7bSHawking Zhang #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f 421*1b0f0f7bSHawking Zhang #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL 422*1b0f0f7bSHawking Zhang #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 423*1b0f0f7bSHawking Zhang #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L 424*1b0f0f7bSHawking Zhang //ATC_VMID7_PASID_MAPPING 425*1b0f0f7bSHawking Zhang #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 426*1b0f0f7bSHawking Zhang #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 427*1b0f0f7bSHawking Zhang #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f 428*1b0f0f7bSHawking Zhang #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL 429*1b0f0f7bSHawking Zhang #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 430*1b0f0f7bSHawking Zhang #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L 431*1b0f0f7bSHawking Zhang //ATC_VMID8_PASID_MAPPING 432*1b0f0f7bSHawking Zhang #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 433*1b0f0f7bSHawking Zhang #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 434*1b0f0f7bSHawking Zhang #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f 435*1b0f0f7bSHawking Zhang #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL 436*1b0f0f7bSHawking Zhang #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 437*1b0f0f7bSHawking Zhang #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L 438*1b0f0f7bSHawking Zhang //ATC_VMID9_PASID_MAPPING 439*1b0f0f7bSHawking Zhang #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 440*1b0f0f7bSHawking Zhang #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 441*1b0f0f7bSHawking Zhang #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f 442*1b0f0f7bSHawking Zhang #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL 443*1b0f0f7bSHawking Zhang #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 444*1b0f0f7bSHawking Zhang #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L 445*1b0f0f7bSHawking Zhang //ATC_VMID10_PASID_MAPPING 446*1b0f0f7bSHawking Zhang #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 447*1b0f0f7bSHawking Zhang #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 448*1b0f0f7bSHawking Zhang #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f 449*1b0f0f7bSHawking Zhang #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL 450*1b0f0f7bSHawking Zhang #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 451*1b0f0f7bSHawking Zhang #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L 452*1b0f0f7bSHawking Zhang //ATC_VMID11_PASID_MAPPING 453*1b0f0f7bSHawking Zhang #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 454*1b0f0f7bSHawking Zhang #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 455*1b0f0f7bSHawking Zhang #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f 456*1b0f0f7bSHawking Zhang #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL 457*1b0f0f7bSHawking Zhang #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 458*1b0f0f7bSHawking Zhang #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L 459*1b0f0f7bSHawking Zhang //ATC_VMID12_PASID_MAPPING 460*1b0f0f7bSHawking Zhang #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 461*1b0f0f7bSHawking Zhang #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 462*1b0f0f7bSHawking Zhang #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f 463*1b0f0f7bSHawking Zhang #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL 464*1b0f0f7bSHawking Zhang #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 465*1b0f0f7bSHawking Zhang #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L 466*1b0f0f7bSHawking Zhang //ATC_VMID13_PASID_MAPPING 467*1b0f0f7bSHawking Zhang #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 468*1b0f0f7bSHawking Zhang #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 469*1b0f0f7bSHawking Zhang #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f 470*1b0f0f7bSHawking Zhang #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL 471*1b0f0f7bSHawking Zhang #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 472*1b0f0f7bSHawking Zhang #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L 473*1b0f0f7bSHawking Zhang //ATC_VMID14_PASID_MAPPING 474*1b0f0f7bSHawking Zhang #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 475*1b0f0f7bSHawking Zhang #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 476*1b0f0f7bSHawking Zhang #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f 477*1b0f0f7bSHawking Zhang #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL 478*1b0f0f7bSHawking Zhang #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 479*1b0f0f7bSHawking Zhang #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L 480*1b0f0f7bSHawking Zhang //ATC_VMID15_PASID_MAPPING 481*1b0f0f7bSHawking Zhang #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 482*1b0f0f7bSHawking Zhang #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 483*1b0f0f7bSHawking Zhang #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f 484*1b0f0f7bSHawking Zhang #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL 485*1b0f0f7bSHawking Zhang #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 486*1b0f0f7bSHawking Zhang #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L 487*1b0f0f7bSHawking Zhang //ATC_TRANS_FAULT_RSPCNTRL 488*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 489*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 490*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 491*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 492*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 493*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 494*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 495*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 496*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 497*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 498*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 499*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb 500*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc 501*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd 502*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe 503*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf 504*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L 505*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L 506*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L 507*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L 508*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L 509*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L 510*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L 511*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L 512*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L 513*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L 514*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L 515*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L 516*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L 517*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L 518*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L 519*1b0f0f7bSHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L 520*1b0f0f7bSHawking Zhang //ATC_ATS_VMID_STATUS 521*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 522*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 523*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 524*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 525*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 526*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 527*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 528*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 529*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 530*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 531*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 532*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb 533*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc 534*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd 535*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe 536*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf 537*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L 538*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L 539*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L 540*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L 541*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L 542*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L 543*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L 544*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L 545*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L 546*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L 547*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L 548*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L 549*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L 550*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L 551*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L 552*1b0f0f7bSHawking Zhang #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L 553*1b0f0f7bSHawking Zhang //ATHUB_MISC_CNTL 554*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 555*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 556*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 557*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 558*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 559*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b 560*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c 561*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__SRAM_FGCG_ENABLE__SHIFT 0x1d 562*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L 563*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L 564*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L 565*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L 566*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L 567*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L 568*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L 569*1b0f0f7bSHawking Zhang #define ATHUB_MISC_CNTL__SRAM_FGCG_ENABLE_MASK 0x20000000L 570*1b0f0f7bSHawking Zhang //ATHUB_MEM_POWER_LS 571*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 572*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 573*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_DELAY_ENABLE__SHIFT 0x13 574*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_DELAY_TIME__SHIFT 0x14 575*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 576*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x0007FFC0L 577*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_DELAY_ENABLE_MASK 0x00080000L 578*1b0f0f7bSHawking Zhang #define ATHUB_MEM_POWER_LS__LS_DELAY_TIME_MASK 0x03F00000L 579*1b0f0f7bSHawking Zhang //ATHUB_IH_CREDIT 580*1b0f0f7bSHawking Zhang #define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 581*1b0f0f7bSHawking Zhang #define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 582*1b0f0f7bSHawking Zhang #define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 583*1b0f0f7bSHawking Zhang #define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 584*1b0f0f7bSHawking Zhang 585*1b0f0f7bSHawking Zhang 586*1b0f0f7bSHawking Zhang // addressBlock: aid_athub_xpbdec 587*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR0 588*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 589*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 590*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR1 591*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 592*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 593*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR2 594*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 595*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 596*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR3 597*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 598*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 599*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR4 600*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 601*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 602*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR5 603*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 604*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 605*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR6 606*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 607*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 608*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR7 609*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 610*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 611*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR8 612*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 613*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 614*1b0f0f7bSHawking Zhang //XPB_RTR_SRC_APRTR9 615*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 616*1b0f0f7bSHawking Zhang #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 617*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_SRC_APRTR0 618*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 619*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 620*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_SRC_APRTR1 621*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 622*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 623*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_SRC_APRTR2 624*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 625*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 626*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_SRC_APRTR3 627*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 628*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 629*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP0 630*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 631*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 632*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 633*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 634*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 635*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 636*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 637*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 638*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 639*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 640*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 641*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 642*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP1 643*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 644*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 645*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 646*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 647*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 648*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 649*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 650*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 651*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 652*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 653*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 654*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 655*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP2 656*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 657*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 658*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 659*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 660*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 661*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 662*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 663*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 664*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 665*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 666*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 667*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 668*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP3 669*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 670*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 671*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 672*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 673*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 674*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 675*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 676*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 677*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 678*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 679*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 680*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 681*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP4 682*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 683*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 684*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 685*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 686*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 687*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 688*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 689*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 690*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 691*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 692*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L 693*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 694*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP5 695*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 696*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 697*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 698*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 699*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 700*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 701*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 702*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 703*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 704*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 705*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L 706*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 707*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP6 708*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 709*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 710*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 711*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 712*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 713*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 714*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 715*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 716*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 717*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 718*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L 719*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 720*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP7 721*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 722*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 723*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 724*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 725*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 726*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 727*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 728*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 729*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 730*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 731*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L 732*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 733*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP8 734*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 735*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 736*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 737*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 738*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 739*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 740*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 741*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 742*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 743*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 744*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L 745*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 746*1b0f0f7bSHawking Zhang //XPB_RTR_DEST_MAP9 747*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 748*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 749*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 750*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 751*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 752*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 753*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 754*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 755*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 756*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 757*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L 758*1b0f0f7bSHawking Zhang #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 759*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_DEST_MAP0 760*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 761*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 762*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 763*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 764*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 765*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 766*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L 767*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 768*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 769*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 770*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 771*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 772*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_DEST_MAP1 773*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 774*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 775*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 776*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 777*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 778*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 779*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L 780*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 781*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 782*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 783*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 784*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 785*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_DEST_MAP2 786*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 787*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 788*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 789*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 790*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 791*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 792*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L 793*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 794*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 795*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 796*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 797*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 798*1b0f0f7bSHawking Zhang //XPB_XDMA_RTR_DEST_MAP3 799*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 800*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 801*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 802*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 803*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 804*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 805*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L 806*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 807*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 808*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 809*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 810*1b0f0f7bSHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 811*1b0f0f7bSHawking Zhang //XPB_CLG_CFG0 812*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 813*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 814*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 815*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 816*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe 817*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 818*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L 819*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 820*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 821*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L 822*1b0f0f7bSHawking Zhang //XPB_CLG_CFG1 823*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 824*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 825*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 826*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 827*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe 828*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 829*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L 830*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 831*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 832*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L 833*1b0f0f7bSHawking Zhang //XPB_CLG_CFG2 834*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 835*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 836*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 837*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 838*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe 839*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 840*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L 841*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 842*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 843*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L 844*1b0f0f7bSHawking Zhang //XPB_CLG_CFG3 845*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 846*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 847*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 848*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 849*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe 850*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 851*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L 852*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 853*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 854*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L 855*1b0f0f7bSHawking Zhang //XPB_CLG_CFG4 856*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 857*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 858*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 859*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 860*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe 861*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 862*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L 863*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 864*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 865*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L 866*1b0f0f7bSHawking Zhang //XPB_CLG_CFG5 867*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 868*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 869*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 870*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 871*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe 872*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 873*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L 874*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 875*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 876*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L 877*1b0f0f7bSHawking Zhang //XPB_CLG_CFG6 878*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 879*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 880*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 881*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 882*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe 883*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 884*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L 885*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 886*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 887*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L 888*1b0f0f7bSHawking Zhang //XPB_CLG_CFG7 889*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 890*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 891*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 892*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 893*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe 894*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 895*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L 896*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 897*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 898*1b0f0f7bSHawking Zhang #define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L 899*1b0f0f7bSHawking Zhang //XPB_CLG_EXTRA0 900*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__CMP0_HIGH__SHIFT 0x0 901*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__CMP0_LOW__SHIFT 0x8 902*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__VLD0__SHIFT 0xd 903*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__CLG0_NUM__SHIFT 0xe 904*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__CMP0_HIGH_MASK 0x000000FFL 905*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__CMP0_LOW_MASK 0x00001F00L 906*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__VLD0_MASK 0x00002000L 907*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA0__CLG0_NUM_MASK 0x0001C000L 908*1b0f0f7bSHawking Zhang //XPB_CLG_EXTRA1 909*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__CMP1_HIGH__SHIFT 0x0 910*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__CMP1_LOW__SHIFT 0x8 911*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__VLD1__SHIFT 0xd 912*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__CLG1_NUM__SHIFT 0xe 913*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__CMP1_HIGH_MASK 0x000000FFL 914*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__CMP1_LOW_MASK 0x00001F00L 915*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__VLD1_MASK 0x00002000L 916*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA1__CLG1_NUM_MASK 0x0001C000L 917*1b0f0f7bSHawking Zhang //XPB_CLG_EXTRA_MSK 918*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 919*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x8 920*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xd 921*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x15 922*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x000000FFL 923*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x00001F00L 924*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x001FE000L 925*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x03E00000L 926*1b0f0f7bSHawking Zhang //XPB_LB_ADDR 927*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__CMP0__SHIFT 0x0 928*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__MASK0__SHIFT 0xa 929*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__CMP1__SHIFT 0x14 930*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 931*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 932*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 933*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 934*1b0f0f7bSHawking Zhang #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 935*1b0f0f7bSHawking Zhang //XPB_WCB_STS 936*1b0f0f7bSHawking Zhang #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 937*1b0f0f7bSHawking Zhang #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 938*1b0f0f7bSHawking Zhang #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 939*1b0f0f7bSHawking Zhang #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 940*1b0f0f7bSHawking Zhang #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 941*1b0f0f7bSHawking Zhang #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 942*1b0f0f7bSHawking Zhang //XPB_HST_CFG 943*1b0f0f7bSHawking Zhang #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 944*1b0f0f7bSHawking Zhang #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 945*1b0f0f7bSHawking Zhang //XPB_P2P_BAR_CFG 946*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 947*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 948*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 949*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 950*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 951*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 952*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 953*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 954*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 955*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 956*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 957*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 958*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 959*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 960*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 961*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 962*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 963*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 964*1b0f0f7bSHawking Zhang //XPB_P2P_BAR0 965*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 966*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 967*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 968*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__VALID__SHIFT 0xc 969*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 970*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 971*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__RESERVED__SHIFT 0xf 972*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 973*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 974*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 975*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 976*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 977*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 978*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 979*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L 980*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 981*1b0f0f7bSHawking Zhang //XPB_P2P_BAR1 982*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 983*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 984*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 985*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__VALID__SHIFT 0xc 986*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 987*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 988*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__RESERVED__SHIFT 0xf 989*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 990*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 991*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 992*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 993*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 994*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 995*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 996*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L 997*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 998*1b0f0f7bSHawking Zhang //XPB_P2P_BAR2 999*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 1000*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 1001*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 1002*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__VALID__SHIFT 0xc 1003*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 1004*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 1005*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__RESERVED__SHIFT 0xf 1006*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 1007*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 1008*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 1009*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 1010*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 1011*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 1012*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 1013*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L 1014*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 1015*1b0f0f7bSHawking Zhang //XPB_P2P_BAR3 1016*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 1017*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 1018*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 1019*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__VALID__SHIFT 0xc 1020*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 1021*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 1022*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__RESERVED__SHIFT 0xf 1023*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 1024*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 1025*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 1026*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 1027*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 1028*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 1029*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 1030*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L 1031*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 1032*1b0f0f7bSHawking Zhang //XPB_P2P_BAR4 1033*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 1034*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 1035*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 1036*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__VALID__SHIFT 0xc 1037*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 1038*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 1039*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__RESERVED__SHIFT 0xf 1040*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 1041*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 1042*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 1043*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 1044*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 1045*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 1046*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 1047*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L 1048*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 1049*1b0f0f7bSHawking Zhang //XPB_P2P_BAR5 1050*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 1051*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 1052*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 1053*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__VALID__SHIFT 0xc 1054*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 1055*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 1056*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__RESERVED__SHIFT 0xf 1057*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 1058*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 1059*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 1060*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 1061*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 1062*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 1063*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 1064*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L 1065*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 1066*1b0f0f7bSHawking Zhang //XPB_P2P_BAR6 1067*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 1068*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 1069*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 1070*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__VALID__SHIFT 0xc 1071*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 1072*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 1073*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__RESERVED__SHIFT 0xf 1074*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 1075*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 1076*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 1077*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 1078*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 1079*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 1080*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 1081*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L 1082*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 1083*1b0f0f7bSHawking Zhang //XPB_P2P_BAR7 1084*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 1085*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 1086*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 1087*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__VALID__SHIFT 0xc 1088*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 1089*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 1090*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__RESERVED__SHIFT 0xf 1091*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 1092*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 1093*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 1094*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 1095*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 1096*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 1097*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 1098*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L 1099*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 1100*1b0f0f7bSHawking Zhang //XPB_P2P_BAR_SETUP 1101*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 1102*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 1103*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 1104*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 1105*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 1106*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf 1107*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 1108*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 1109*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 1110*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 1111*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 1112*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 1113*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L 1114*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 1115*1b0f0f7bSHawking Zhang //XPB_P2P_BAR_DELTA_ABOVE 1116*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 1117*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 1118*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 1119*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 1120*1b0f0f7bSHawking Zhang //XPB_P2P_BAR_DELTA_BELOW 1121*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 1122*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 1123*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 1124*1b0f0f7bSHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 1125*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR0 1126*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 1127*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1128*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1129*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1130*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR1 1131*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 1132*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1133*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1134*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1135*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR2 1136*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 1137*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1138*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1139*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1140*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR3 1141*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 1142*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1143*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1144*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1145*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR4 1146*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 1147*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 1148*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 1149*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 1150*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR5 1151*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 1152*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 1153*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 1154*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 1155*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR6 1156*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 1157*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 1158*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 1159*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 1160*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR7 1161*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 1162*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 1163*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 1164*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 1165*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR8 1166*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 1167*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 1168*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 1169*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 1170*1b0f0f7bSHawking Zhang //XPB_PEER_SYS_BAR9 1171*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 1172*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 1173*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 1174*1b0f0f7bSHawking Zhang #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 1175*1b0f0f7bSHawking Zhang //XPB_XDMA_PEER_SYS_BAR0 1176*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 1177*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1178*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1179*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1180*1b0f0f7bSHawking Zhang //XPB_XDMA_PEER_SYS_BAR1 1181*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 1182*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1183*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1184*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1185*1b0f0f7bSHawking Zhang //XPB_XDMA_PEER_SYS_BAR2 1186*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 1187*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1188*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1189*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1190*1b0f0f7bSHawking Zhang //XPB_XDMA_PEER_SYS_BAR3 1191*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 1192*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1193*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1194*1b0f0f7bSHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1195*1b0f0f7bSHawking Zhang //XPB_CLK_GAT 1196*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 1197*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 1198*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 1199*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 1200*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 1201*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 1202*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 1203*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 1204*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 1205*1b0f0f7bSHawking Zhang #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 1206*1b0f0f7bSHawking Zhang //XPB_INTF_CFG 1207*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 1208*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 1209*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 1210*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 1211*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 1212*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 1213*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a 1214*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 1215*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 1216*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 1217*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA__SHIFT 0x1f 1218*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 1219*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 1220*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 1221*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L 1222*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L 1223*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L 1224*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L 1225*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 1226*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 1227*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 1228*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA_MASK 0x80000000L 1229*1b0f0f7bSHawking Zhang //XPB_INTF_STS 1230*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 1231*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 1232*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 1233*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 1234*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 1235*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 1236*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 1237*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 1238*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 1239*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 1240*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 1241*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 1242*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 1243*1b0f0f7bSHawking Zhang #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 1244*1b0f0f7bSHawking Zhang //XPB_PIPE_STS 1245*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 1246*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 1247*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 1248*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 1249*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 1250*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 1251*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 1252*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 1253*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 1254*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 1255*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 1256*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 1257*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 1258*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 1259*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 1260*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 1261*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 1262*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 1263*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 1264*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 1265*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 1266*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 1267*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 1268*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 1269*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 1270*1b0f0f7bSHawking Zhang #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 1271*1b0f0f7bSHawking Zhang //XPB_SUB_CTRL 1272*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 1273*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 1274*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 1275*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 1276*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 1277*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 1278*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 1279*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 1280*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 1281*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 1282*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 1283*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 1284*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 1285*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 1286*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 1287*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 1288*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 1289*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 1290*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 1291*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 1292*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 1293*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 1294*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 1295*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 1296*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 1297*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 1298*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 1299*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 1300*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 1301*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 1302*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 1303*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 1304*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 1305*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 1306*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 1307*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 1308*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 1309*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 1310*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 1311*1b0f0f7bSHawking Zhang #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 1312*1b0f0f7bSHawking Zhang //XPB_MAP_INVERT_FLUSH_NUM_LSB 1313*1b0f0f7bSHawking Zhang #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 1314*1b0f0f7bSHawking Zhang #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 1315*1b0f0f7bSHawking Zhang //XPB_PERF_KNOBS 1316*1b0f0f7bSHawking Zhang #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 1317*1b0f0f7bSHawking Zhang #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 1318*1b0f0f7bSHawking Zhang #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 1319*1b0f0f7bSHawking Zhang #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 1320*1b0f0f7bSHawking Zhang #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 1321*1b0f0f7bSHawking Zhang #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 1322*1b0f0f7bSHawking Zhang //XPB_STICKY 1323*1b0f0f7bSHawking Zhang #define XPB_STICKY__BITS__SHIFT 0x0 1324*1b0f0f7bSHawking Zhang #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 1325*1b0f0f7bSHawking Zhang //XPB_STICKY_W1C 1326*1b0f0f7bSHawking Zhang #define XPB_STICKY_W1C__BITS__SHIFT 0x0 1327*1b0f0f7bSHawking Zhang #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 1328*1b0f0f7bSHawking Zhang //XPB_MISC_CFG 1329*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 1330*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 1331*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 1332*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 1333*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 1334*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 1335*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 1336*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 1337*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 1338*1b0f0f7bSHawking Zhang #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 1339*1b0f0f7bSHawking Zhang //XPB_INTF_CFG2 1340*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 1341*1b0f0f7bSHawking Zhang #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 1342*1b0f0f7bSHawking Zhang //XPB_CLG_EXTRA_RD 1343*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 1344*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 1345*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 1346*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 1347*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 1348*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 1349*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 1350*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 1351*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 1352*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 1353*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 1354*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 1355*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 1356*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 1357*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 1358*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 1359*1b0f0f7bSHawking Zhang //XPB_CLG_EXTRA_MSK_RD 1360*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 1361*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 1362*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 1363*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 1364*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 1365*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 1366*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 1367*1b0f0f7bSHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 1368*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_MATCH 1369*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 1370*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x8 1371*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0x10 1372*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x18 1373*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x000000FFL 1374*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x0000FF00L 1375*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x00FF0000L 1376*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0xFF000000L 1377*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_MATCH_VLD 1378*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC0_VLD__SHIFT 0x0 1379*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC1_VLD__SHIFT 0x1 1380*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC2_VLD__SHIFT 0x2 1381*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC3_VLD__SHIFT 0x3 1382*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC0_VLD_MASK 0x00000001L 1383*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC1_VLD_MASK 0x00000002L 1384*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC2_VLD_MASK 0x00000004L 1385*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_VLD__FARBIRC3_VLD_MASK 0x00000008L 1386*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_MATCH_MSK 1387*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1388*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x8 1389*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x10 1390*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x18 1391*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x000000FFL 1392*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x0000FF00L 1393*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x00FF0000L 1394*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0xFF000000L 1395*1b0f0f7bSHawking Zhang //XPB_CLG_MM_MATCH 1396*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 1397*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x8 1398*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0x10 1399*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x18 1400*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x000000FFL 1401*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x0000FF00L 1402*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x00FF0000L 1403*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0xFF000000L 1404*1b0f0f7bSHawking Zhang //XPB_CLG_MM_MATCH_VLD 1405*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC0_VLD__SHIFT 0x0 1406*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC1_VLD__SHIFT 0x1 1407*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC2_VLD__SHIFT 0x2 1408*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC3_VLD__SHIFT 0x3 1409*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC0_VLD_MASK 0x00000001L 1410*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC1_VLD_MASK 0x00000002L 1411*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC2_VLD_MASK 0x00000004L 1412*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_VLD__FARBIRC3_VLD_MASK 0x00000008L 1413*1b0f0f7bSHawking Zhang //XPB_CLG_MM_MATCH_MSK 1414*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1415*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x8 1416*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x10 1417*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x18 1418*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x000000FFL 1419*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x0000FF00L 1420*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x00FF0000L 1421*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0xFF000000L 1422*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING0 1423*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1424*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1425*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1426*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1427*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1428*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1429*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING1 1430*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1431*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1432*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1433*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1434*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1435*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1436*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING2 1437*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1438*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1439*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1440*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1441*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1442*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1443*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING3 1444*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1445*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1446*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1447*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1448*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1449*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1450*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING4 1451*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 1452*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 1453*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 1454*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 1455*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 1456*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 1457*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING5 1458*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 1459*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 1460*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 1461*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 1462*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 1463*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 1464*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING6 1465*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 1466*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 1467*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 1468*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 1469*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 1470*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 1471*1b0f0f7bSHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING7 1472*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 1473*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 1474*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 1475*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 1476*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 1477*1b0f0f7bSHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 1478*1b0f0f7bSHawking Zhang //XPB_CLG_MM_UNITID_MAPPING0 1479*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1480*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1481*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1482*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1483*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1484*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1485*1b0f0f7bSHawking Zhang //XPB_CLG_MM_UNITID_MAPPING1 1486*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1487*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1488*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1489*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1490*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1491*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1492*1b0f0f7bSHawking Zhang //XPB_CLG_MM_UNITID_MAPPING2 1493*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1494*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1495*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1496*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1497*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1498*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1499*1b0f0f7bSHawking Zhang //XPB_CLG_MM_UNITID_MAPPING3 1500*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1501*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1502*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1503*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1504*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1505*1b0f0f7bSHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1506*1b0f0f7bSHawking Zhang 1507*1b0f0f7bSHawking Zhang 1508*1b0f0f7bSHawking Zhang // addressBlock: aid_athub_rpbdec 1509*1b0f0f7bSHawking Zhang //RPB_PASSPW_CONF 1510*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 1511*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 1512*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 1513*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 1514*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 1515*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 1516*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 1517*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 1518*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 1519*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 1520*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa 1521*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb 1522*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc 1523*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 1524*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe 1525*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf 1526*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 1527*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 1528*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 1529*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 1530*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L 1531*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L 1532*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L 1533*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L 1534*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L 1535*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L 1536*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L 1537*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L 1538*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L 1539*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L 1540*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L 1541*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 1542*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L 1543*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L 1544*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L 1545*1b0f0f7bSHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L 1546*1b0f0f7bSHawking Zhang //RPB_BLOCKLEVEL_CONF 1547*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 1548*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL__SHIFT 0x2 1549*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL__SHIFT 0x4 1550*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x6 1551*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x8 1552*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0xa 1553*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xc 1554*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xe 1555*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 1556*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 1557*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x12 1558*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x13 1559*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 1560*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL_MASK 0x0000000CL 1561*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL_MASK 0x00000030L 1562*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x000000C0L 1563*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x00000300L 1564*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L 1565*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L 1566*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x0000C000L 1567*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 1568*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L 1569*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00040000L 1570*1b0f0f7bSHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00080000L 1571*1b0f0f7bSHawking Zhang //RPB_TAG_CONF 1572*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF__RPB_ATS_VC0_TR__SHIFT 0x0 1573*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF__RPB_ATS_VC5_TR__SHIFT 0xa 1574*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x14 1575*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF__RPB_ATS_VC0_TR_MASK 0x000003FFL 1576*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF__RPB_ATS_VC5_TR_MASK 0x000FFC00L 1577*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x3FF00000L 1578*1b0f0f7bSHawking Zhang //RPB_TAG_CONF2 1579*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF2__RPB_IO_WR__SHIFT 0x0 1580*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF2__RPB_IO_MAX_LIMIT__SHIFT 0xa 1581*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF2__RPB_IO_RD_MARGIN__SHIFT 0x15 1582*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF2__RPB_IO_WR_MASK 0x000003FFL 1583*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF2__RPB_IO_MAX_LIMIT_MASK 0x001FFC00L 1584*1b0f0f7bSHawking Zhang #define RPB_TAG_CONF2__RPB_IO_RD_MARGIN_MASK 0xFFE00000L 1585*1b0f0f7bSHawking Zhang //RPB_ARB_CNTL 1586*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 1587*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 1588*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 1589*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 1590*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 1591*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 1592*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 1593*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 1594*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 1595*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 1596*1b0f0f7bSHawking Zhang //RPB_ARB_CNTL2 1597*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 1598*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 1599*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 1600*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 1601*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 1602*1b0f0f7bSHawking Zhang #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 1603*1b0f0f7bSHawking Zhang //RPB_BIF_CNTL 1604*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x0 1605*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x1 1606*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x3 1607*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x4 1608*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0xc 1609*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__VC0TR_PRI_EN__SHIFT 0xd 1610*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__VC5TR_PRI_EN__SHIFT 0xe 1611*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0xf 1612*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__ARB_MODE_MASK 0x00000001L 1613*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00000006L 1614*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00000008L 1615*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x00000FF0L 1616*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x00001000L 1617*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__VC0TR_PRI_EN_MASK 0x00002000L 1618*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__VC5TR_PRI_EN_MASK 0x00004000L 1619*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x00008000L 1620*1b0f0f7bSHawking Zhang //RPB_BIF_CNTL2 1621*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL2__VC0_SWITCH_NUM__SHIFT 0x0 1622*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL2__VC1_SWITCH_NUM__SHIFT 0x8 1623*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL2__VC5_SWITCH_NUM__SHIFT 0x10 1624*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL2__VC0_SWITCH_NUM_MASK 0x000000FFL 1625*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL2__VC1_SWITCH_NUM_MASK 0x0000FF00L 1626*1b0f0f7bSHawking Zhang #define RPB_BIF_CNTL2__VC5_SWITCH_NUM_MASK 0x00FF0000L 1627*1b0f0f7bSHawking Zhang //RPB_PERF_COUNTER_CNTL 1628*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1629*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 1630*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 1631*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 1632*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 1633*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 1634*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe 1635*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 1636*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 1637*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 1638*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L 1639*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L 1640*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L 1641*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L 1642*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L 1643*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L 1644*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L 1645*1b0f0f7bSHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L 1646*1b0f0f7bSHawking Zhang //RPB_DEINTRLV_COMBINE_CNTL 1647*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 1648*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 1649*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 1650*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN__SHIFT 0x6 1651*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 1652*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 1653*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 1654*1b0f0f7bSHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN_MASK 0x00000040L 1655*1b0f0f7bSHawking Zhang //RPB_VC_SWITCH_RDWR 1656*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 1657*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 1658*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 1659*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12 1660*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 1661*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 1662*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 1663*1b0f0f7bSHawking Zhang #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L 1664*1b0f0f7bSHawking Zhang //RPB_PERFCOUNTER_LO 1665*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1666*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1667*1b0f0f7bSHawking Zhang //RPB_PERFCOUNTER_HI 1668*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1669*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1670*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1671*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1672*1b0f0f7bSHawking Zhang //RPB_PERFCOUNTER0_CFG 1673*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1674*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1675*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1676*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1677*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1678*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1679*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1680*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1681*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1682*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1683*1b0f0f7bSHawking Zhang //RPB_PERFCOUNTER1_CFG 1684*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1685*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1686*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1687*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1688*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1689*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1690*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1691*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1692*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1693*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1694*1b0f0f7bSHawking Zhang //RPB_PERFCOUNTER2_CFG 1695*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1696*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1697*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1698*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1699*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1700*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1701*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1702*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1703*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1704*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1705*1b0f0f7bSHawking Zhang //RPB_PERFCOUNTER3_CFG 1706*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 1707*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 1708*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 1709*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 1710*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 1711*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 1712*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 1713*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 1714*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 1715*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 1716*1b0f0f7bSHawking Zhang //RPB_PERFCOUNTER_RSLT_CNTL 1717*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1718*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1719*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1720*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1721*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1722*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1723*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1724*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1725*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1726*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1727*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1728*1b0f0f7bSHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1729*1b0f0f7bSHawking Zhang //RPB_ATS_CNTL 1730*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 1731*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 1732*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 1733*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 1734*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf 1735*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 1736*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 1737*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 1738*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 1739*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 1740*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 1741*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 1742*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L 1743*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 1744*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 1745*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L 1746*1b0f0f7bSHawking Zhang //RPB_ATS_CNTL2 1747*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 1748*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 1749*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc 1750*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf 1751*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 1752*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__MM_TRANS_VC5_ENABLE__SHIFT 0x14 1753*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__GC_TRANS_VC5_ENABLE__SHIFT 0x15 1754*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__RPB_VC5_CRD__SHIFT 0x16 1755*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL 1756*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L 1757*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L 1758*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L 1759*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L 1760*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__MM_TRANS_VC5_ENABLE_MASK 0x00100000L 1761*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__GC_TRANS_VC5_ENABLE_MASK 0x00200000L 1762*1b0f0f7bSHawking Zhang #define RPB_ATS_CNTL2__RPB_VC5_CRD_MASK 0x07C00000L 1763*1b0f0f7bSHawking Zhang //RPB_SDPPORT_CNTL 1764*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 1765*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 1766*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 1767*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 1768*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 1769*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 1770*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa 1771*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb 1772*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd 1773*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe 1774*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf 1775*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 1776*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 1777*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 1778*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 1779*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 1780*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 1781*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 1782*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 1783*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 1784*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0x1c 1785*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 1786*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 1787*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 1788*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 1789*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 1790*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 1791*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L 1792*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L 1793*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L 1794*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L 1795*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L 1796*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L 1797*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L 1798*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L 1799*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 1800*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 1801*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 1802*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 1803*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 1804*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 1805*1b0f0f7bSHawking Zhang #define RPB_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0xF0000000L 1806*1b0f0f7bSHawking Zhang 1807*1b0f0f7bSHawking Zhang #endif 1808