16ce68225SFeifei Xu /* 26ce68225SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 36ce68225SFeifei Xu * 46ce68225SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 56ce68225SFeifei Xu * copy of this software and associated documentation files (the "Software"), 66ce68225SFeifei Xu * to deal in the Software without restriction, including without limitation 76ce68225SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 86ce68225SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 96ce68225SFeifei Xu * Software is furnished to do so, subject to the following conditions: 106ce68225SFeifei Xu * 116ce68225SFeifei Xu * The above copyright notice and this permission notice shall be included 126ce68225SFeifei Xu * in all copies or substantial portions of the Software. 136ce68225SFeifei Xu * 146ce68225SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 156ce68225SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 166ce68225SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 176ce68225SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 186ce68225SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 196ce68225SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 206ce68225SFeifei Xu */ 216ce68225SFeifei Xu #ifndef _athub_1_0_SH_MASK_HEADER 226ce68225SFeifei Xu #define _athub_1_0_SH_MASK_HEADER 236ce68225SFeifei Xu 246ce68225SFeifei Xu 256ce68225SFeifei Xu // addressBlock: athub_atsdec 266ce68225SFeifei Xu //ATC_ATS_CNTL 276ce68225SFeifei Xu #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 286ce68225SFeifei Xu #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 296ce68225SFeifei Xu #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 306ce68225SFeifei Xu #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 316ce68225SFeifei Xu #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 326ce68225SFeifei Xu #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 336ce68225SFeifei Xu #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 346ce68225SFeifei Xu #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 356ce68225SFeifei Xu #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 366ce68225SFeifei Xu #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 376ce68225SFeifei Xu #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L 386ce68225SFeifei Xu #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L 396ce68225SFeifei Xu #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L 406ce68225SFeifei Xu #define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L 416ce68225SFeifei Xu //ATC_ATS_STATUS 426ce68225SFeifei Xu #define ATC_ATS_STATUS__BUSY__SHIFT 0x0 436ce68225SFeifei Xu #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 446ce68225SFeifei Xu #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 456ce68225SFeifei Xu #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 466ce68225SFeifei Xu #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 476ce68225SFeifei Xu #define ATC_ATS_STATUS__BUSY_MASK 0x00000001L 486ce68225SFeifei Xu #define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L 496ce68225SFeifei Xu #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L 506ce68225SFeifei Xu #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L 516ce68225SFeifei Xu #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L 526ce68225SFeifei Xu //ATC_ATS_FAULT_CNTL 536ce68225SFeifei Xu #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 546ce68225SFeifei Xu #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 556ce68225SFeifei Xu #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 566ce68225SFeifei Xu #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL 576ce68225SFeifei Xu #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L 586ce68225SFeifei Xu #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L 596ce68225SFeifei Xu //ATC_ATS_FAULT_STATUS_INFO 606ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 616ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 626ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf 636ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 646ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 656ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 666ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 676ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 686ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL 696ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L 706ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L 716ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L 726ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L 736ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L 746ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L 756ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L 766ce68225SFeifei Xu //ATC_ATS_FAULT_STATUS_ADDR 776ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 786ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL 796ce68225SFeifei Xu //ATC_ATS_DEFAULT_PAGE_LOW 806ce68225SFeifei Xu #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 816ce68225SFeifei Xu #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL 826ce68225SFeifei Xu //ATC_TRANS_FAULT_RSPCNTRL 836ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 846ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 856ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 866ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 876ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 886ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 896ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 906ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 916ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 926ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 936ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 946ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb 956ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc 966ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd 976ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe 986ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf 996ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 1006ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 1016ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 1026ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 1036ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 1046ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 1056ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 1066ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 1076ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 1086ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 1096ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a 1106ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b 1116ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c 1126ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d 1136ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e 1146ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f 1156ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L 1166ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L 1176ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L 1186ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L 1196ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L 1206ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L 1216ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L 1226ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L 1236ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L 1246ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L 1256ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L 1266ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L 1276ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L 1286ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L 1296ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L 1306ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L 1316ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L 1326ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L 1336ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L 1346ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L 1356ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L 1366ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L 1376ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L 1386ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L 1396ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L 1406ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L 1416ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L 1426ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L 1436ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L 1446ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L 1456ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L 1466ce68225SFeifei Xu #define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L 1476ce68225SFeifei Xu //ATC_ATS_FAULT_STATUS_INFO2 1486ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 1496ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 1506ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 1516ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L 1526ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL 1536ce68225SFeifei Xu #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L 1546ce68225SFeifei Xu //ATHUB_MISC_CNTL 1556ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 1566ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 1576ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 1586ce68225SFeifei Xu #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 1596ce68225SFeifei Xu #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 1606ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b 1616ce68225SFeifei Xu #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c 1626ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L 1636ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L 1646ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L 1656ce68225SFeifei Xu #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L 1666ce68225SFeifei Xu #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L 1676ce68225SFeifei Xu #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L 1686ce68225SFeifei Xu #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L 1696ce68225SFeifei Xu //ATC_VMID_PASID_MAPPING_UPDATE_STATUS 1706ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 1716ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 1726ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 1736ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 1746ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 1756ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 1766ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 1776ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 1786ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 1796ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 1806ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 1816ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb 1826ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc 1836ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd 1846ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe 1856ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf 1866ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 1876ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 1886ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 1896ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 1906ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 1916ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 1926ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 1936ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 1946ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 1956ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 1966ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a 1976ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b 1986ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c 1996ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d 2006ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e 2016ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f 2026ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L 2036ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L 2046ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L 2056ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L 2066ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L 2076ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L 2086ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L 2096ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L 2106ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L 2116ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L 2126ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L 2136ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L 2146ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L 2156ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L 2166ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L 2176ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L 2186ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L 2196ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L 2206ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L 2216ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L 2226ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L 2236ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L 2246ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L 2256ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L 2266ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L 2276ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L 2286ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L 2296ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L 2306ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L 2316ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L 2326ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L 2336ce68225SFeifei Xu #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L 2346ce68225SFeifei Xu //ATC_VMID0_PASID_MAPPING 2356ce68225SFeifei Xu #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 2366ce68225SFeifei Xu #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2376ce68225SFeifei Xu #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f 2386ce68225SFeifei Xu #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2396ce68225SFeifei Xu #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2406ce68225SFeifei Xu #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L 2416ce68225SFeifei Xu //ATC_VMID1_PASID_MAPPING 2426ce68225SFeifei Xu #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 2436ce68225SFeifei Xu #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2446ce68225SFeifei Xu #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f 2456ce68225SFeifei Xu #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2466ce68225SFeifei Xu #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2476ce68225SFeifei Xu #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L 2486ce68225SFeifei Xu //ATC_VMID2_PASID_MAPPING 2496ce68225SFeifei Xu #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 2506ce68225SFeifei Xu #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2516ce68225SFeifei Xu #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f 2526ce68225SFeifei Xu #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2536ce68225SFeifei Xu #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2546ce68225SFeifei Xu #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L 2556ce68225SFeifei Xu //ATC_VMID3_PASID_MAPPING 2566ce68225SFeifei Xu #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 2576ce68225SFeifei Xu #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2586ce68225SFeifei Xu #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f 2596ce68225SFeifei Xu #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2606ce68225SFeifei Xu #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2616ce68225SFeifei Xu #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L 2626ce68225SFeifei Xu //ATC_VMID4_PASID_MAPPING 2636ce68225SFeifei Xu #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 2646ce68225SFeifei Xu #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2656ce68225SFeifei Xu #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f 2666ce68225SFeifei Xu #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2676ce68225SFeifei Xu #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2686ce68225SFeifei Xu #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L 2696ce68225SFeifei Xu //ATC_VMID5_PASID_MAPPING 2706ce68225SFeifei Xu #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 2716ce68225SFeifei Xu #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2726ce68225SFeifei Xu #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f 2736ce68225SFeifei Xu #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2746ce68225SFeifei Xu #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2756ce68225SFeifei Xu #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L 2766ce68225SFeifei Xu //ATC_VMID6_PASID_MAPPING 2776ce68225SFeifei Xu #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 2786ce68225SFeifei Xu #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2796ce68225SFeifei Xu #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f 2806ce68225SFeifei Xu #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2816ce68225SFeifei Xu #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2826ce68225SFeifei Xu #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L 2836ce68225SFeifei Xu //ATC_VMID7_PASID_MAPPING 2846ce68225SFeifei Xu #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 2856ce68225SFeifei Xu #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2866ce68225SFeifei Xu #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f 2876ce68225SFeifei Xu #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2886ce68225SFeifei Xu #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2896ce68225SFeifei Xu #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L 2906ce68225SFeifei Xu //ATC_VMID8_PASID_MAPPING 2916ce68225SFeifei Xu #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 2926ce68225SFeifei Xu #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 2936ce68225SFeifei Xu #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f 2946ce68225SFeifei Xu #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL 2956ce68225SFeifei Xu #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 2966ce68225SFeifei Xu #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L 2976ce68225SFeifei Xu //ATC_VMID9_PASID_MAPPING 2986ce68225SFeifei Xu #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 2996ce68225SFeifei Xu #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 3006ce68225SFeifei Xu #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f 3016ce68225SFeifei Xu #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL 3026ce68225SFeifei Xu #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 3036ce68225SFeifei Xu #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L 3046ce68225SFeifei Xu //ATC_VMID10_PASID_MAPPING 3056ce68225SFeifei Xu #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 3066ce68225SFeifei Xu #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 3076ce68225SFeifei Xu #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f 3086ce68225SFeifei Xu #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL 3096ce68225SFeifei Xu #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 3106ce68225SFeifei Xu #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L 3116ce68225SFeifei Xu //ATC_VMID11_PASID_MAPPING 3126ce68225SFeifei Xu #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 3136ce68225SFeifei Xu #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 3146ce68225SFeifei Xu #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f 3156ce68225SFeifei Xu #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL 3166ce68225SFeifei Xu #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 3176ce68225SFeifei Xu #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L 3186ce68225SFeifei Xu //ATC_VMID12_PASID_MAPPING 3196ce68225SFeifei Xu #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 3206ce68225SFeifei Xu #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 3216ce68225SFeifei Xu #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f 3226ce68225SFeifei Xu #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL 3236ce68225SFeifei Xu #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 3246ce68225SFeifei Xu #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L 3256ce68225SFeifei Xu //ATC_VMID13_PASID_MAPPING 3266ce68225SFeifei Xu #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 3276ce68225SFeifei Xu #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 3286ce68225SFeifei Xu #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f 3296ce68225SFeifei Xu #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL 3306ce68225SFeifei Xu #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 3316ce68225SFeifei Xu #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L 3326ce68225SFeifei Xu //ATC_VMID14_PASID_MAPPING 3336ce68225SFeifei Xu #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 3346ce68225SFeifei Xu #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 3356ce68225SFeifei Xu #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f 3366ce68225SFeifei Xu #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL 3376ce68225SFeifei Xu #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 3386ce68225SFeifei Xu #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L 3396ce68225SFeifei Xu //ATC_VMID15_PASID_MAPPING 3406ce68225SFeifei Xu #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 3416ce68225SFeifei Xu #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 3426ce68225SFeifei Xu #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f 3436ce68225SFeifei Xu #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL 3446ce68225SFeifei Xu #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 3456ce68225SFeifei Xu #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L 3466ce68225SFeifei Xu //ATC_ATS_VMID_STATUS 3476ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 3486ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 3496ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 3506ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 3516ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 3526ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 3536ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 3546ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 3556ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 3566ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 3576ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 3586ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb 3596ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc 3606ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd 3616ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe 3626ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf 3636ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 3646ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 3656ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 3666ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 3676ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 3686ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 3696ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 3706ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 3716ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 3726ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 3736ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a 3746ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b 3756ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c 3766ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d 3776ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e 3786ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f 3796ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L 3806ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L 3816ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L 3826ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L 3836ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L 3846ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L 3856ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L 3866ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L 3876ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L 3886ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L 3896ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L 3906ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L 3916ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L 3926ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L 3936ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L 3946ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L 3956ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L 3966ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L 3976ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L 3986ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L 3996ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L 4006ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L 4016ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L 4026ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L 4036ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L 4046ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L 4056ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L 4066ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L 4076ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L 4086ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L 4096ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L 4106ce68225SFeifei Xu #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L 4116ce68225SFeifei Xu //ATC_ATS_GFX_ATCL2_STATUS 4126ce68225SFeifei Xu #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 4136ce68225SFeifei Xu #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 4146ce68225SFeifei Xu //ATC_PERFCOUNTER0_CFG 4156ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4166ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4176ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4186ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4196ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4206ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4216ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4226ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4236ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4246ce68225SFeifei Xu #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4256ce68225SFeifei Xu //ATC_PERFCOUNTER1_CFG 4266ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4276ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4286ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4296ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4306ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4316ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4326ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4336ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4346ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4356ce68225SFeifei Xu #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4366ce68225SFeifei Xu //ATC_PERFCOUNTER2_CFG 4376ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 4386ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 4396ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 4406ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 4416ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4426ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 4436ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 4446ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 4456ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 4466ce68225SFeifei Xu #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 4476ce68225SFeifei Xu //ATC_PERFCOUNTER3_CFG 4486ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 4496ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 4506ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 4516ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 4526ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4536ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 4546ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 4556ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 4566ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 4576ce68225SFeifei Xu #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 4586ce68225SFeifei Xu //ATC_PERFCOUNTER_RSLT_CNTL 4596ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4606ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4616ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4626ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4636ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4646ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4656ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4666ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4676ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4686ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4696ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4706ce68225SFeifei Xu #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4716ce68225SFeifei Xu //ATC_PERFCOUNTER_LO 4726ce68225SFeifei Xu #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4736ce68225SFeifei Xu #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4746ce68225SFeifei Xu //ATC_PERFCOUNTER_HI 4756ce68225SFeifei Xu #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4766ce68225SFeifei Xu #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4776ce68225SFeifei Xu #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4786ce68225SFeifei Xu #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4796ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL 4806ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 4816ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 4826ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 4836ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 4846ce68225SFeifei Xu //ATHUB_PCIE_PASID_CNTL 4856ce68225SFeifei Xu #define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 4866ce68225SFeifei Xu #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 4876ce68225SFeifei Xu #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 4886ce68225SFeifei Xu #define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L 4896ce68225SFeifei Xu #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L 4906ce68225SFeifei Xu #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L 4916ce68225SFeifei Xu //ATHUB_PCIE_PAGE_REQ_CNTL 4926ce68225SFeifei Xu #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 4936ce68225SFeifei Xu #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 4946ce68225SFeifei Xu #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L 4956ce68225SFeifei Xu #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L 4966ce68225SFeifei Xu //ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 4976ce68225SFeifei Xu #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 4986ce68225SFeifei Xu #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL 4996ce68225SFeifei Xu //ATHUB_COMMAND 5006ce68225SFeifei Xu #define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 5016ce68225SFeifei Xu #define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L 5026ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_0 5036ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 5046ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 5056ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_1 5066ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 5076ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 5086ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_2 5096ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 5106ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 5116ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_3 5126ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 5136ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 5146ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_4 5156ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 5166ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 5176ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_5 5186ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 5196ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 5206ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_6 5216ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 5226ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 5236ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_7 5246ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 5256ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 5266ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_8 5276ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 5286ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 5296ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_9 5306ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 5316ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 5326ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_10 5336ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 5346ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 5356ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_11 5366ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 5376ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 5386ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_12 5396ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 5406ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 5416ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_13 5426ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 5436ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 5446ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_14 5456ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 5466ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 5476ce68225SFeifei Xu //ATHUB_PCIE_ATS_CNTL_VF_15 5486ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 5496ce68225SFeifei Xu #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 5506ce68225SFeifei Xu //ATHUB_MEM_POWER_LS 5516ce68225SFeifei Xu #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 5526ce68225SFeifei Xu #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 5536ce68225SFeifei Xu #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 5546ce68225SFeifei Xu #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 5556ce68225SFeifei Xu //ATS_IH_CREDIT 5566ce68225SFeifei Xu #define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 5576ce68225SFeifei Xu #define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 5586ce68225SFeifei Xu #define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 5596ce68225SFeifei Xu #define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 5606ce68225SFeifei Xu //ATHUB_IH_CREDIT 5616ce68225SFeifei Xu #define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 5626ce68225SFeifei Xu #define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 5636ce68225SFeifei Xu #define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 5646ce68225SFeifei Xu #define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 5656ce68225SFeifei Xu //ATC_VMID16_PASID_MAPPING 5666ce68225SFeifei Xu #define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 5676ce68225SFeifei Xu #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 5686ce68225SFeifei Xu #define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f 5696ce68225SFeifei Xu #define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL 5706ce68225SFeifei Xu #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 5716ce68225SFeifei Xu #define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L 5726ce68225SFeifei Xu //ATC_VMID17_PASID_MAPPING 5736ce68225SFeifei Xu #define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 5746ce68225SFeifei Xu #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 5756ce68225SFeifei Xu #define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f 5766ce68225SFeifei Xu #define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL 5776ce68225SFeifei Xu #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 5786ce68225SFeifei Xu #define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L 5796ce68225SFeifei Xu //ATC_VMID18_PASID_MAPPING 5806ce68225SFeifei Xu #define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 5816ce68225SFeifei Xu #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 5826ce68225SFeifei Xu #define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f 5836ce68225SFeifei Xu #define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL 5846ce68225SFeifei Xu #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 5856ce68225SFeifei Xu #define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L 5866ce68225SFeifei Xu //ATC_VMID19_PASID_MAPPING 5876ce68225SFeifei Xu #define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 5886ce68225SFeifei Xu #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 5896ce68225SFeifei Xu #define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f 5906ce68225SFeifei Xu #define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL 5916ce68225SFeifei Xu #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 5926ce68225SFeifei Xu #define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L 5936ce68225SFeifei Xu //ATC_VMID20_PASID_MAPPING 5946ce68225SFeifei Xu #define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 5956ce68225SFeifei Xu #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 5966ce68225SFeifei Xu #define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f 5976ce68225SFeifei Xu #define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL 5986ce68225SFeifei Xu #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 5996ce68225SFeifei Xu #define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L 6006ce68225SFeifei Xu //ATC_VMID21_PASID_MAPPING 6016ce68225SFeifei Xu #define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 6026ce68225SFeifei Xu #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6036ce68225SFeifei Xu #define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f 6046ce68225SFeifei Xu #define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6056ce68225SFeifei Xu #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6066ce68225SFeifei Xu #define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L 6076ce68225SFeifei Xu //ATC_VMID22_PASID_MAPPING 6086ce68225SFeifei Xu #define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 6096ce68225SFeifei Xu #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6106ce68225SFeifei Xu #define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f 6116ce68225SFeifei Xu #define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6126ce68225SFeifei Xu #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6136ce68225SFeifei Xu #define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L 6146ce68225SFeifei Xu //ATC_VMID23_PASID_MAPPING 6156ce68225SFeifei Xu #define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 6166ce68225SFeifei Xu #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6176ce68225SFeifei Xu #define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f 6186ce68225SFeifei Xu #define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6196ce68225SFeifei Xu #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6206ce68225SFeifei Xu #define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L 6216ce68225SFeifei Xu //ATC_VMID24_PASID_MAPPING 6226ce68225SFeifei Xu #define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 6236ce68225SFeifei Xu #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6246ce68225SFeifei Xu #define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f 6256ce68225SFeifei Xu #define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6266ce68225SFeifei Xu #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6276ce68225SFeifei Xu #define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L 6286ce68225SFeifei Xu //ATC_VMID25_PASID_MAPPING 6296ce68225SFeifei Xu #define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 6306ce68225SFeifei Xu #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6316ce68225SFeifei Xu #define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f 6326ce68225SFeifei Xu #define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6336ce68225SFeifei Xu #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6346ce68225SFeifei Xu #define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L 6356ce68225SFeifei Xu //ATC_VMID26_PASID_MAPPING 6366ce68225SFeifei Xu #define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 6376ce68225SFeifei Xu #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6386ce68225SFeifei Xu #define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f 6396ce68225SFeifei Xu #define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6406ce68225SFeifei Xu #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6416ce68225SFeifei Xu #define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L 6426ce68225SFeifei Xu //ATC_VMID27_PASID_MAPPING 6436ce68225SFeifei Xu #define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 6446ce68225SFeifei Xu #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6456ce68225SFeifei Xu #define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f 6466ce68225SFeifei Xu #define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6476ce68225SFeifei Xu #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6486ce68225SFeifei Xu #define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L 6496ce68225SFeifei Xu //ATC_VMID28_PASID_MAPPING 6506ce68225SFeifei Xu #define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 6516ce68225SFeifei Xu #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6526ce68225SFeifei Xu #define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f 6536ce68225SFeifei Xu #define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6546ce68225SFeifei Xu #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6556ce68225SFeifei Xu #define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L 6566ce68225SFeifei Xu //ATC_VMID29_PASID_MAPPING 6576ce68225SFeifei Xu #define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 6586ce68225SFeifei Xu #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6596ce68225SFeifei Xu #define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f 6606ce68225SFeifei Xu #define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6616ce68225SFeifei Xu #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6626ce68225SFeifei Xu #define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L 6636ce68225SFeifei Xu //ATC_VMID30_PASID_MAPPING 6646ce68225SFeifei Xu #define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 6656ce68225SFeifei Xu #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6666ce68225SFeifei Xu #define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f 6676ce68225SFeifei Xu #define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6686ce68225SFeifei Xu #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6696ce68225SFeifei Xu #define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L 6706ce68225SFeifei Xu //ATC_VMID31_PASID_MAPPING 6716ce68225SFeifei Xu #define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 6726ce68225SFeifei Xu #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 6736ce68225SFeifei Xu #define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f 6746ce68225SFeifei Xu #define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL 6756ce68225SFeifei Xu #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 6766ce68225SFeifei Xu #define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L 6776ce68225SFeifei Xu //ATC_ATS_MMHUB_ATCL2_STATUS 6786ce68225SFeifei Xu #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 6796ce68225SFeifei Xu #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 6806ce68225SFeifei Xu //ATHUB_SHARED_VIRT_RESET_REQ 6816ce68225SFeifei Xu #define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 6826ce68225SFeifei Xu #define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 6836ce68225SFeifei Xu #define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 6846ce68225SFeifei Xu #define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 6856ce68225SFeifei Xu //ATHUB_SHARED_ACTIVE_FCN_ID 6866ce68225SFeifei Xu #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 6876ce68225SFeifei Xu #define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 6886ce68225SFeifei Xu #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 6896ce68225SFeifei Xu #define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 6906ce68225SFeifei Xu //ATC_ATS_SDPPORT_CNTL 6916ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 6926ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 6936ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 6946ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 6956ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 6966ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 6976ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd 6986ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe 6996ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf 7006ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 7016ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 7026ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 7036ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 7046ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 7056ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 7066ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 7076ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 7086ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 7096ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 7106ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L 7116ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L 7126ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L 7136ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L 7146ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L 7156ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L 7166ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L 7176ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L 7186ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L 7196ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L 7206ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L 7216ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L 7226ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L 7236ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L 7246ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L 7256ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L 7266ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L 7276ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L 7286ce68225SFeifei Xu #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L 7296ce68225SFeifei Xu //ATC_ATS_VMID_SNAPSHOT_GFX_STAT 7306ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 7316ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 7326ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 7336ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 7346ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 7356ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 7366ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 7376ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 7386ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 7396ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 7406ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa 7416ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb 7426ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc 7436ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd 7446ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe 7456ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf 7466ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L 7476ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L 7486ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L 7496ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L 7506ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L 7516ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L 7526ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L 7536ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L 7546ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L 7556ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L 7566ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L 7576ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L 7586ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L 7596ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L 7606ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L 7616ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L 7626ce68225SFeifei Xu //ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 7636ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 7646ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 7656ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 7666ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 7676ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 7686ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 7696ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 7706ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 7716ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 7726ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 7736ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa 7746ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb 7756ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc 7766ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd 7776ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe 7786ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf 7796ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L 7806ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L 7816ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L 7826ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L 7836ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L 7846ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L 7856ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L 7866ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L 7876ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L 7886ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L 7896ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L 7906ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L 7916ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L 7926ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L 7936ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L 7946ce68225SFeifei Xu #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L 7956ce68225SFeifei Xu 7966ce68225SFeifei Xu 7976ce68225SFeifei Xu // addressBlock: athub_xpbdec 7986ce68225SFeifei Xu //XPB_RTR_SRC_APRTR0 7996ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 8006ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 8016ce68225SFeifei Xu //XPB_RTR_SRC_APRTR1 8026ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 8036ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 8046ce68225SFeifei Xu //XPB_RTR_SRC_APRTR2 8056ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 8066ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 8076ce68225SFeifei Xu //XPB_RTR_SRC_APRTR3 8086ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 8096ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 8106ce68225SFeifei Xu //XPB_RTR_SRC_APRTR4 8116ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 8126ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 8136ce68225SFeifei Xu //XPB_RTR_SRC_APRTR5 8146ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 8156ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 8166ce68225SFeifei Xu //XPB_RTR_SRC_APRTR6 8176ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 8186ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 8196ce68225SFeifei Xu //XPB_RTR_SRC_APRTR7 8206ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 8216ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 8226ce68225SFeifei Xu //XPB_RTR_SRC_APRTR8 8236ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 8246ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 8256ce68225SFeifei Xu //XPB_RTR_SRC_APRTR9 8266ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 8276ce68225SFeifei Xu #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 8286ce68225SFeifei Xu //XPB_XDMA_RTR_SRC_APRTR0 8296ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 8306ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 8316ce68225SFeifei Xu //XPB_XDMA_RTR_SRC_APRTR1 8326ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 8336ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 8346ce68225SFeifei Xu //XPB_XDMA_RTR_SRC_APRTR2 8356ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 8366ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 8376ce68225SFeifei Xu //XPB_XDMA_RTR_SRC_APRTR3 8386ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 8396ce68225SFeifei Xu #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 8406ce68225SFeifei Xu //XPB_RTR_DEST_MAP0 8416ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 8426ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 8436ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 8446ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 8456ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 8466ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 8476ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 8486ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 8496ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 8506ce68225SFeifei Xu #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 8516ce68225SFeifei Xu //XPB_RTR_DEST_MAP1 8526ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 8536ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 8546ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 8556ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 8566ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 8576ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 8586ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 8596ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 8606ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 8616ce68225SFeifei Xu #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 8626ce68225SFeifei Xu //XPB_RTR_DEST_MAP2 8636ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 8646ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 8656ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 8666ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 8676ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 8686ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 8696ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 8706ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 8716ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 8726ce68225SFeifei Xu #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 8736ce68225SFeifei Xu //XPB_RTR_DEST_MAP3 8746ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 8756ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 8766ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 8776ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 8786ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 8796ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 8806ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 8816ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 8826ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 8836ce68225SFeifei Xu #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 8846ce68225SFeifei Xu //XPB_RTR_DEST_MAP4 8856ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 8866ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 8876ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 8886ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 8896ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 8906ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 8916ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 8926ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 8936ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 8946ce68225SFeifei Xu #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 8956ce68225SFeifei Xu //XPB_RTR_DEST_MAP5 8966ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 8976ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 8986ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 8996ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 9006ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 9016ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 9026ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 9036ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 9046ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 9056ce68225SFeifei Xu #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 9066ce68225SFeifei Xu //XPB_RTR_DEST_MAP6 9076ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 9086ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 9096ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 9106ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 9116ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 9126ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 9136ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 9146ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 9156ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 9166ce68225SFeifei Xu #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 9176ce68225SFeifei Xu //XPB_RTR_DEST_MAP7 9186ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 9196ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 9206ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 9216ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 9226ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 9236ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 9246ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 9256ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 9266ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 9276ce68225SFeifei Xu #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 9286ce68225SFeifei Xu //XPB_RTR_DEST_MAP8 9296ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 9306ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 9316ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 9326ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 9336ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 9346ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 9356ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 9366ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 9376ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 9386ce68225SFeifei Xu #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 9396ce68225SFeifei Xu //XPB_RTR_DEST_MAP9 9406ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 9416ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 9426ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 9436ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 9446ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 9456ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 9466ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 9476ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 9486ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 9496ce68225SFeifei Xu #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 9506ce68225SFeifei Xu //XPB_XDMA_RTR_DEST_MAP0 9516ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 9526ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 9536ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 9546ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 9556ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 9566ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L 9576ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 9586ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 9596ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 9606ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 9616ce68225SFeifei Xu //XPB_XDMA_RTR_DEST_MAP1 9626ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 9636ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 9646ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 9656ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 9666ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 9676ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L 9686ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 9696ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 9706ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 9716ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 9726ce68225SFeifei Xu //XPB_XDMA_RTR_DEST_MAP2 9736ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 9746ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 9756ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 9766ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 9776ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 9786ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L 9796ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 9806ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 9816ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 9826ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 9836ce68225SFeifei Xu //XPB_XDMA_RTR_DEST_MAP3 9846ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 9856ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 9866ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 9876ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 9886ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 9896ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L 9906ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 9916ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 9926ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 9936ce68225SFeifei Xu #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 9946ce68225SFeifei Xu //XPB_CLG_CFG0 9956ce68225SFeifei Xu #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 9966ce68225SFeifei Xu #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 9976ce68225SFeifei Xu #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 9986ce68225SFeifei Xu #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 9996ce68225SFeifei Xu #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 10006ce68225SFeifei Xu #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 10016ce68225SFeifei Xu //XPB_CLG_CFG1 10026ce68225SFeifei Xu #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 10036ce68225SFeifei Xu #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 10046ce68225SFeifei Xu #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 10056ce68225SFeifei Xu #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 10066ce68225SFeifei Xu #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 10076ce68225SFeifei Xu #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 10086ce68225SFeifei Xu //XPB_CLG_CFG2 10096ce68225SFeifei Xu #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 10106ce68225SFeifei Xu #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 10116ce68225SFeifei Xu #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 10126ce68225SFeifei Xu #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 10136ce68225SFeifei Xu #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 10146ce68225SFeifei Xu #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 10156ce68225SFeifei Xu //XPB_CLG_CFG3 10166ce68225SFeifei Xu #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 10176ce68225SFeifei Xu #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 10186ce68225SFeifei Xu #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 10196ce68225SFeifei Xu #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 10206ce68225SFeifei Xu #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 10216ce68225SFeifei Xu #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 10226ce68225SFeifei Xu //XPB_CLG_CFG4 10236ce68225SFeifei Xu #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 10246ce68225SFeifei Xu #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 10256ce68225SFeifei Xu #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 10266ce68225SFeifei Xu #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 10276ce68225SFeifei Xu #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 10286ce68225SFeifei Xu #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 10296ce68225SFeifei Xu //XPB_CLG_CFG5 10306ce68225SFeifei Xu #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 10316ce68225SFeifei Xu #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 10326ce68225SFeifei Xu #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 10336ce68225SFeifei Xu #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 10346ce68225SFeifei Xu #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 10356ce68225SFeifei Xu #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 10366ce68225SFeifei Xu //XPB_CLG_CFG6 10376ce68225SFeifei Xu #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 10386ce68225SFeifei Xu #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 10396ce68225SFeifei Xu #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 10406ce68225SFeifei Xu #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 10416ce68225SFeifei Xu #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 10426ce68225SFeifei Xu #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 10436ce68225SFeifei Xu //XPB_CLG_CFG7 10446ce68225SFeifei Xu #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 10456ce68225SFeifei Xu #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 10466ce68225SFeifei Xu #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 10476ce68225SFeifei Xu #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 10486ce68225SFeifei Xu #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 10496ce68225SFeifei Xu #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 10506ce68225SFeifei Xu //XPB_CLG_EXTRA 10516ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 10526ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 10536ce68225SFeifei Xu #define XPB_CLG_EXTRA__VLD0__SHIFT 0xb 10546ce68225SFeifei Xu #define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc 10556ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf 10566ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 10576ce68225SFeifei Xu #define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a 10586ce68225SFeifei Xu #define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b 10596ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL 10606ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L 10616ce68225SFeifei Xu #define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L 10626ce68225SFeifei Xu #define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L 10636ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L 10646ce68225SFeifei Xu #define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L 10656ce68225SFeifei Xu #define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L 10666ce68225SFeifei Xu #define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L 10676ce68225SFeifei Xu //XPB_CLG_EXTRA_MSK 10686ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 10696ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 10706ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb 10716ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 10726ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL 10736ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L 10746ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L 10756ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L 10766ce68225SFeifei Xu //XPB_LB_ADDR 10776ce68225SFeifei Xu #define XPB_LB_ADDR__CMP0__SHIFT 0x0 10786ce68225SFeifei Xu #define XPB_LB_ADDR__MASK0__SHIFT 0xa 10796ce68225SFeifei Xu #define XPB_LB_ADDR__CMP1__SHIFT 0x14 10806ce68225SFeifei Xu #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 10816ce68225SFeifei Xu #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 10826ce68225SFeifei Xu #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 10836ce68225SFeifei Xu #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 10846ce68225SFeifei Xu #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 10856ce68225SFeifei Xu //XPB_WCB_STS 10866ce68225SFeifei Xu #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 10876ce68225SFeifei Xu #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 10886ce68225SFeifei Xu #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 10896ce68225SFeifei Xu #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 10906ce68225SFeifei Xu #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 10916ce68225SFeifei Xu #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 10926ce68225SFeifei Xu //XPB_HST_CFG 10936ce68225SFeifei Xu #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 10946ce68225SFeifei Xu #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 10956ce68225SFeifei Xu //XPB_P2P_BAR_CFG 10966ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 10976ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 10986ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 10996ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 11006ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 11016ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 11026ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 11036ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 11046ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 11056ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 11066ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 11076ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 11086ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 11096ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 11106ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 11116ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 11126ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 11136ce68225SFeifei Xu #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 11146ce68225SFeifei Xu //XPB_P2P_BAR0 11156ce68225SFeifei Xu #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 11166ce68225SFeifei Xu #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 11176ce68225SFeifei Xu #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 11186ce68225SFeifei Xu #define XPB_P2P_BAR0__VALID__SHIFT 0xc 11196ce68225SFeifei Xu #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 11206ce68225SFeifei Xu #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 11216ce68225SFeifei Xu #define XPB_P2P_BAR0__RESERVED__SHIFT 0xf 11226ce68225SFeifei Xu #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 11236ce68225SFeifei Xu #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 11246ce68225SFeifei Xu #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 11256ce68225SFeifei Xu #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 11266ce68225SFeifei Xu #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 11276ce68225SFeifei Xu #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 11286ce68225SFeifei Xu #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 11296ce68225SFeifei Xu #define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L 11306ce68225SFeifei Xu #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 11316ce68225SFeifei Xu //XPB_P2P_BAR1 11326ce68225SFeifei Xu #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 11336ce68225SFeifei Xu #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 11346ce68225SFeifei Xu #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 11356ce68225SFeifei Xu #define XPB_P2P_BAR1__VALID__SHIFT 0xc 11366ce68225SFeifei Xu #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 11376ce68225SFeifei Xu #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 11386ce68225SFeifei Xu #define XPB_P2P_BAR1__RESERVED__SHIFT 0xf 11396ce68225SFeifei Xu #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 11406ce68225SFeifei Xu #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 11416ce68225SFeifei Xu #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 11426ce68225SFeifei Xu #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 11436ce68225SFeifei Xu #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 11446ce68225SFeifei Xu #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 11456ce68225SFeifei Xu #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 11466ce68225SFeifei Xu #define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L 11476ce68225SFeifei Xu #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 11486ce68225SFeifei Xu //XPB_P2P_BAR2 11496ce68225SFeifei Xu #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 11506ce68225SFeifei Xu #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 11516ce68225SFeifei Xu #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 11526ce68225SFeifei Xu #define XPB_P2P_BAR2__VALID__SHIFT 0xc 11536ce68225SFeifei Xu #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 11546ce68225SFeifei Xu #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 11556ce68225SFeifei Xu #define XPB_P2P_BAR2__RESERVED__SHIFT 0xf 11566ce68225SFeifei Xu #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 11576ce68225SFeifei Xu #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 11586ce68225SFeifei Xu #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 11596ce68225SFeifei Xu #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 11606ce68225SFeifei Xu #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 11616ce68225SFeifei Xu #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 11626ce68225SFeifei Xu #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 11636ce68225SFeifei Xu #define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L 11646ce68225SFeifei Xu #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 11656ce68225SFeifei Xu //XPB_P2P_BAR3 11666ce68225SFeifei Xu #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 11676ce68225SFeifei Xu #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 11686ce68225SFeifei Xu #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 11696ce68225SFeifei Xu #define XPB_P2P_BAR3__VALID__SHIFT 0xc 11706ce68225SFeifei Xu #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 11716ce68225SFeifei Xu #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 11726ce68225SFeifei Xu #define XPB_P2P_BAR3__RESERVED__SHIFT 0xf 11736ce68225SFeifei Xu #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 11746ce68225SFeifei Xu #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 11756ce68225SFeifei Xu #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 11766ce68225SFeifei Xu #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 11776ce68225SFeifei Xu #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 11786ce68225SFeifei Xu #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 11796ce68225SFeifei Xu #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 11806ce68225SFeifei Xu #define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L 11816ce68225SFeifei Xu #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 11826ce68225SFeifei Xu //XPB_P2P_BAR4 11836ce68225SFeifei Xu #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 11846ce68225SFeifei Xu #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 11856ce68225SFeifei Xu #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 11866ce68225SFeifei Xu #define XPB_P2P_BAR4__VALID__SHIFT 0xc 11876ce68225SFeifei Xu #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 11886ce68225SFeifei Xu #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 11896ce68225SFeifei Xu #define XPB_P2P_BAR4__RESERVED__SHIFT 0xf 11906ce68225SFeifei Xu #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 11916ce68225SFeifei Xu #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 11926ce68225SFeifei Xu #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 11936ce68225SFeifei Xu #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 11946ce68225SFeifei Xu #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 11956ce68225SFeifei Xu #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 11966ce68225SFeifei Xu #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 11976ce68225SFeifei Xu #define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L 11986ce68225SFeifei Xu #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 11996ce68225SFeifei Xu //XPB_P2P_BAR5 12006ce68225SFeifei Xu #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 12016ce68225SFeifei Xu #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 12026ce68225SFeifei Xu #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 12036ce68225SFeifei Xu #define XPB_P2P_BAR5__VALID__SHIFT 0xc 12046ce68225SFeifei Xu #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 12056ce68225SFeifei Xu #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 12066ce68225SFeifei Xu #define XPB_P2P_BAR5__RESERVED__SHIFT 0xf 12076ce68225SFeifei Xu #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 12086ce68225SFeifei Xu #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 12096ce68225SFeifei Xu #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 12106ce68225SFeifei Xu #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 12116ce68225SFeifei Xu #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 12126ce68225SFeifei Xu #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 12136ce68225SFeifei Xu #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 12146ce68225SFeifei Xu #define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L 12156ce68225SFeifei Xu #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 12166ce68225SFeifei Xu //XPB_P2P_BAR6 12176ce68225SFeifei Xu #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 12186ce68225SFeifei Xu #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 12196ce68225SFeifei Xu #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 12206ce68225SFeifei Xu #define XPB_P2P_BAR6__VALID__SHIFT 0xc 12216ce68225SFeifei Xu #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 12226ce68225SFeifei Xu #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 12236ce68225SFeifei Xu #define XPB_P2P_BAR6__RESERVED__SHIFT 0xf 12246ce68225SFeifei Xu #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 12256ce68225SFeifei Xu #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 12266ce68225SFeifei Xu #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 12276ce68225SFeifei Xu #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 12286ce68225SFeifei Xu #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 12296ce68225SFeifei Xu #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 12306ce68225SFeifei Xu #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 12316ce68225SFeifei Xu #define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L 12326ce68225SFeifei Xu #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 12336ce68225SFeifei Xu //XPB_P2P_BAR7 12346ce68225SFeifei Xu #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 12356ce68225SFeifei Xu #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 12366ce68225SFeifei Xu #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 12376ce68225SFeifei Xu #define XPB_P2P_BAR7__VALID__SHIFT 0xc 12386ce68225SFeifei Xu #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 12396ce68225SFeifei Xu #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 12406ce68225SFeifei Xu #define XPB_P2P_BAR7__RESERVED__SHIFT 0xf 12416ce68225SFeifei Xu #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 12426ce68225SFeifei Xu #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 12436ce68225SFeifei Xu #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 12446ce68225SFeifei Xu #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 12456ce68225SFeifei Xu #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 12466ce68225SFeifei Xu #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 12476ce68225SFeifei Xu #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 12486ce68225SFeifei Xu #define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L 12496ce68225SFeifei Xu #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 12506ce68225SFeifei Xu //XPB_P2P_BAR_SETUP 12516ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 12526ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 12536ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 12546ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 12556ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 12566ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf 12576ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 12586ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 12596ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 12606ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 12616ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 12626ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 12636ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L 12646ce68225SFeifei Xu #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 12656ce68225SFeifei Xu //XPB_P2P_BAR_DELTA_ABOVE 12666ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 12676ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 12686ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 12696ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 12706ce68225SFeifei Xu //XPB_P2P_BAR_DELTA_BELOW 12716ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 12726ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 12736ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 12746ce68225SFeifei Xu #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 12756ce68225SFeifei Xu //XPB_PEER_SYS_BAR0 12766ce68225SFeifei Xu #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 12776ce68225SFeifei Xu #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 12786ce68225SFeifei Xu #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 12796ce68225SFeifei Xu #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 12806ce68225SFeifei Xu //XPB_PEER_SYS_BAR1 12816ce68225SFeifei Xu #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 12826ce68225SFeifei Xu #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 12836ce68225SFeifei Xu #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 12846ce68225SFeifei Xu #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 12856ce68225SFeifei Xu //XPB_PEER_SYS_BAR2 12866ce68225SFeifei Xu #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 12876ce68225SFeifei Xu #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 12886ce68225SFeifei Xu #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 12896ce68225SFeifei Xu #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 12906ce68225SFeifei Xu //XPB_PEER_SYS_BAR3 12916ce68225SFeifei Xu #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 12926ce68225SFeifei Xu #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 12936ce68225SFeifei Xu #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 12946ce68225SFeifei Xu #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 12956ce68225SFeifei Xu //XPB_PEER_SYS_BAR4 12966ce68225SFeifei Xu #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 12976ce68225SFeifei Xu #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 12986ce68225SFeifei Xu #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 12996ce68225SFeifei Xu #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 13006ce68225SFeifei Xu //XPB_PEER_SYS_BAR5 13016ce68225SFeifei Xu #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 13026ce68225SFeifei Xu #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 13036ce68225SFeifei Xu #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 13046ce68225SFeifei Xu #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 13056ce68225SFeifei Xu //XPB_PEER_SYS_BAR6 13066ce68225SFeifei Xu #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 13076ce68225SFeifei Xu #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 13086ce68225SFeifei Xu #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 13096ce68225SFeifei Xu #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 13106ce68225SFeifei Xu //XPB_PEER_SYS_BAR7 13116ce68225SFeifei Xu #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 13126ce68225SFeifei Xu #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 13136ce68225SFeifei Xu #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 13146ce68225SFeifei Xu #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 13156ce68225SFeifei Xu //XPB_PEER_SYS_BAR8 13166ce68225SFeifei Xu #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 13176ce68225SFeifei Xu #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 13186ce68225SFeifei Xu #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 13196ce68225SFeifei Xu #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 13206ce68225SFeifei Xu //XPB_PEER_SYS_BAR9 13216ce68225SFeifei Xu #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 13226ce68225SFeifei Xu #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 13236ce68225SFeifei Xu #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 13246ce68225SFeifei Xu #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 13256ce68225SFeifei Xu //XPB_XDMA_PEER_SYS_BAR0 13266ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 13276ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 13286ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L 13296ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 13306ce68225SFeifei Xu //XPB_XDMA_PEER_SYS_BAR1 13316ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 13326ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 13336ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L 13346ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 13356ce68225SFeifei Xu //XPB_XDMA_PEER_SYS_BAR2 13366ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 13376ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 13386ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L 13396ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 13406ce68225SFeifei Xu //XPB_XDMA_PEER_SYS_BAR3 13416ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 13426ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 13436ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L 13446ce68225SFeifei Xu #define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 13456ce68225SFeifei Xu //XPB_CLK_GAT 13466ce68225SFeifei Xu #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 13476ce68225SFeifei Xu #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 13486ce68225SFeifei Xu #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 13496ce68225SFeifei Xu #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 13506ce68225SFeifei Xu #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 13516ce68225SFeifei Xu #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 13526ce68225SFeifei Xu #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 13536ce68225SFeifei Xu #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 13546ce68225SFeifei Xu #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 13556ce68225SFeifei Xu #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 13566ce68225SFeifei Xu //XPB_INTF_CFG 13576ce68225SFeifei Xu #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 13586ce68225SFeifei Xu #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 13596ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 13606ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 13616ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 13626ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 13636ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a 13646ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 13656ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 13666ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 13676ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f 13686ce68225SFeifei Xu #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 13696ce68225SFeifei Xu #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 13706ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 13716ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L 13726ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L 13736ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L 13746ce68225SFeifei Xu #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L 13756ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 13766ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 13776ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 13786ce68225SFeifei Xu #define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L 13796ce68225SFeifei Xu //XPB_INTF_STS 13806ce68225SFeifei Xu #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 13816ce68225SFeifei Xu #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 13826ce68225SFeifei Xu #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 13836ce68225SFeifei Xu #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 13846ce68225SFeifei Xu #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 13856ce68225SFeifei Xu #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 13866ce68225SFeifei Xu #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 13876ce68225SFeifei Xu #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 13886ce68225SFeifei Xu #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 13896ce68225SFeifei Xu #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 13906ce68225SFeifei Xu #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 13916ce68225SFeifei Xu #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 13926ce68225SFeifei Xu #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 13936ce68225SFeifei Xu #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 13946ce68225SFeifei Xu //XPB_PIPE_STS 13956ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 13966ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 13976ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 13986ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 13996ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 14006ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 14016ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 14026ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 14036ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 14046ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 14056ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 14066ce68225SFeifei Xu #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 14076ce68225SFeifei Xu #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 14086ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 14096ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 14106ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 14116ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 14126ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 14136ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 14146ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 14156ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 14166ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 14176ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 14186ce68225SFeifei Xu #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 14196ce68225SFeifei Xu #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 14206ce68225SFeifei Xu #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 14216ce68225SFeifei Xu //XPB_SUB_CTRL 14226ce68225SFeifei Xu #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 14236ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 14246ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 14256ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 14266ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 14276ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 14286ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 14296ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 14306ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 14316ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 14326ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 14336ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 14346ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 14356ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 14366ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 14376ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 14386ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 14396ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 14406ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 14416ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 14426ce68225SFeifei Xu #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 14436ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 14446ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 14456ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 14466ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 14476ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 14486ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 14496ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 14506ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 14516ce68225SFeifei Xu #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 14526ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 14536ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 14546ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 14556ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 14566ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 14576ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 14586ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 14596ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 14606ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 14616ce68225SFeifei Xu #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 14626ce68225SFeifei Xu //XPB_MAP_INVERT_FLUSH_NUM_LSB 14636ce68225SFeifei Xu #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 14646ce68225SFeifei Xu #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 14656ce68225SFeifei Xu //XPB_PERF_KNOBS 14666ce68225SFeifei Xu #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 14676ce68225SFeifei Xu #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 14686ce68225SFeifei Xu #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 14696ce68225SFeifei Xu #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 14706ce68225SFeifei Xu #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 14716ce68225SFeifei Xu #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 14726ce68225SFeifei Xu //XPB_STICKY 14736ce68225SFeifei Xu #define XPB_STICKY__BITS__SHIFT 0x0 14746ce68225SFeifei Xu #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 14756ce68225SFeifei Xu //XPB_STICKY_W1C 14766ce68225SFeifei Xu #define XPB_STICKY_W1C__BITS__SHIFT 0x0 14776ce68225SFeifei Xu #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 14786ce68225SFeifei Xu //XPB_MISC_CFG 14796ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 14806ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 14816ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 14826ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 14836ce68225SFeifei Xu #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 14846ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 14856ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 14866ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 14876ce68225SFeifei Xu #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 14886ce68225SFeifei Xu #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 14896ce68225SFeifei Xu //XPB_INTF_CFG2 14906ce68225SFeifei Xu #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 14916ce68225SFeifei Xu #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 14926ce68225SFeifei Xu //XPB_CLG_EXTRA_RD 14936ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 14946ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 14956ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 14966ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 14976ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 14986ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 14996ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 15006ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 15016ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 15026ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 15036ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 15046ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 15056ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 15066ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 15076ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 15086ce68225SFeifei Xu #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 15096ce68225SFeifei Xu //XPB_CLG_EXTRA_MSK_RD 15106ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 15116ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 15126ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 15136ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 15146ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 15156ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 15166ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 15176ce68225SFeifei Xu #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 15186ce68225SFeifei Xu //XPB_CLG_GFX_MATCH 15196ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 15206ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 15216ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc 15226ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 15236ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 15246ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 15256ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a 15266ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b 15276ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL 15286ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 15296ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L 15306ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 15316ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L 15326ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L 15336ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L 15346ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L 15356ce68225SFeifei Xu //XPB_CLG_GFX_MATCH_MSK 15366ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 15376ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 15386ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 15396ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 15406ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 15416ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 15426ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 15436ce68225SFeifei Xu #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 15446ce68225SFeifei Xu //XPB_CLG_MM_MATCH 15456ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 15466ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 15476ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc 15486ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 15496ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 15506ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 15516ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a 15526ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b 15536ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL 15546ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 15556ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L 15566ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 15576ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L 15586ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L 15596ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L 15606ce68225SFeifei Xu #define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L 15616ce68225SFeifei Xu //XPB_CLG_MM_MATCH_MSK 15626ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 15636ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 15646ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 15656ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 15666ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 15676ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 15686ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 15696ce68225SFeifei Xu #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 15706ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING0 15716ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 15726ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 15736ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 15746ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 15756ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 15766ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 15776ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING1 15786ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 15796ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 15806ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 15816ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 15826ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 15836ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 15846ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING2 15856ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 15866ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 15876ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 15886ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 15896ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 15906ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 15916ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING3 15926ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 15936ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 15946ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 15956ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 15966ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 15976ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 15986ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING4 15996ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 16006ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 16016ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 16026ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 16036ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 16046ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 16056ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING5 16066ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 16076ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 16086ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 16096ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 16106ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 16116ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 16126ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING6 16136ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 16146ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 16156ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 16166ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 16176ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 16186ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 16196ce68225SFeifei Xu //XPB_CLG_GFX_UNITID_MAPPING7 16206ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 16216ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 16226ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 16236ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 16246ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 16256ce68225SFeifei Xu #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 16266ce68225SFeifei Xu //XPB_CLG_MM_UNITID_MAPPING0 16276ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 16286ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 16296ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 16306ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 16316ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 16326ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 16336ce68225SFeifei Xu //XPB_CLG_MM_UNITID_MAPPING1 16346ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 16356ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 16366ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 16376ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 16386ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 16396ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 16406ce68225SFeifei Xu //XPB_CLG_MM_UNITID_MAPPING2 16416ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 16426ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 16436ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 16446ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 16456ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 16466ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 16476ce68225SFeifei Xu //XPB_CLG_MM_UNITID_MAPPING3 16486ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 16496ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 16506ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 16516ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 16526ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 16536ce68225SFeifei Xu #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 16546ce68225SFeifei Xu 16556ce68225SFeifei Xu 16566ce68225SFeifei Xu // addressBlock: athub_rpbdec 16576ce68225SFeifei Xu //RPB_PASSPW_CONF 16586ce68225SFeifei Xu #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 16596ce68225SFeifei Xu #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 16606ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 16616ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 16626ce68225SFeifei Xu #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 16636ce68225SFeifei Xu #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 16646ce68225SFeifei Xu #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 16656ce68225SFeifei Xu #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 16666ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 16676ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 16686ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa 16696ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb 16706ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc 16716ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 16726ce68225SFeifei Xu #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe 16736ce68225SFeifei Xu #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf 16746ce68225SFeifei Xu #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 16756ce68225SFeifei Xu #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 16766ce68225SFeifei Xu #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 16776ce68225SFeifei Xu #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 16786ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L 16796ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L 16806ce68225SFeifei Xu #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L 16816ce68225SFeifei Xu #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L 16826ce68225SFeifei Xu #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L 16836ce68225SFeifei Xu #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L 16846ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L 16856ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L 16866ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L 16876ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L 16886ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L 16896ce68225SFeifei Xu #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 16906ce68225SFeifei Xu #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L 16916ce68225SFeifei Xu #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L 16926ce68225SFeifei Xu #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L 16936ce68225SFeifei Xu #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L 16946ce68225SFeifei Xu //RPB_BLOCKLEVEL_CONF 16956ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 16966ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 16976ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 16986ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 16996ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 17006ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa 17016ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc 17026ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe 17036ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf 17046ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 17056ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 17066ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 17076ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL 17086ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L 17096ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L 17106ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L 17116ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L 17126ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L 17136ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L 17146ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L 17156ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 17166ce68225SFeifei Xu #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L 17176ce68225SFeifei Xu //RPB_TAG_CONF 17186ce68225SFeifei Xu #define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 17196ce68225SFeifei Xu #define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 17206ce68225SFeifei Xu #define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 17216ce68225SFeifei Xu #define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL 17226ce68225SFeifei Xu #define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L 17236ce68225SFeifei Xu #define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L 17246ce68225SFeifei Xu //RPB_EFF_CNTL 17256ce68225SFeifei Xu #define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 17266ce68225SFeifei Xu #define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 17276ce68225SFeifei Xu #define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL 17286ce68225SFeifei Xu #define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L 17296ce68225SFeifei Xu //RPB_ARB_CNTL 17306ce68225SFeifei Xu #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 17316ce68225SFeifei Xu #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 17326ce68225SFeifei Xu #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 17336ce68225SFeifei Xu #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 17346ce68225SFeifei Xu #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 17356ce68225SFeifei Xu #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 17366ce68225SFeifei Xu #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 17376ce68225SFeifei Xu #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 17386ce68225SFeifei Xu #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 17396ce68225SFeifei Xu #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 17406ce68225SFeifei Xu //RPB_ARB_CNTL2 17416ce68225SFeifei Xu #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 17426ce68225SFeifei Xu #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 17436ce68225SFeifei Xu #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 17446ce68225SFeifei Xu #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 17456ce68225SFeifei Xu #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 17466ce68225SFeifei Xu #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 17476ce68225SFeifei Xu //RPB_BIF_CNTL 17486ce68225SFeifei Xu #define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 17496ce68225SFeifei Xu #define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 17506ce68225SFeifei Xu #define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 17516ce68225SFeifei Xu #define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 17526ce68225SFeifei Xu #define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 17536ce68225SFeifei Xu #define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 17546ce68225SFeifei Xu #define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b 17556ce68225SFeifei Xu #define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c 17566ce68225SFeifei Xu #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d 17576ce68225SFeifei Xu #define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e 17586ce68225SFeifei Xu #define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 17596ce68225SFeifei Xu #define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 17606ce68225SFeifei Xu #define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L 17616ce68225SFeifei Xu #define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L 17626ce68225SFeifei Xu #define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L 17636ce68225SFeifei Xu #define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L 17646ce68225SFeifei Xu #define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L 17656ce68225SFeifei Xu #define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L 17666ce68225SFeifei Xu #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L 17676ce68225SFeifei Xu #define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L 17686ce68225SFeifei Xu //RPB_WR_SWITCH_CNTL 17696ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 17706ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 17716ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 17726ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 17736ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 17746ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 17756ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 17766ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 17776ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 17786ce68225SFeifei Xu #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 17796ce68225SFeifei Xu //RPB_RD_SWITCH_CNTL 17806ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 17816ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 17826ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 17836ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 17846ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 17856ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 17866ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 17876ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 17886ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 17896ce68225SFeifei Xu #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 17906ce68225SFeifei Xu //RPB_CID_QUEUE_WR 17916ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 17926ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 17936ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb 17946ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc 17956ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf 17966ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 17976ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL 17986ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L 17996ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L 18006ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L 18016ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L 18026ce68225SFeifei Xu #define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L 18036ce68225SFeifei Xu //RPB_CID_QUEUE_RD 18046ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 18056ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 18066ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb 18076ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe 18086ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL 18096ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L 18106ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L 18116ce68225SFeifei Xu #define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L 18126ce68225SFeifei Xu //RPB_CID_QUEUE_EX 18136ce68225SFeifei Xu #define RPB_CID_QUEUE_EX__START__SHIFT 0x0 18146ce68225SFeifei Xu #define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 18156ce68225SFeifei Xu #define RPB_CID_QUEUE_EX__START_MASK 0x00000001L 18166ce68225SFeifei Xu #define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL 18176ce68225SFeifei Xu //RPB_CID_QUEUE_EX_DATA 18186ce68225SFeifei Xu #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 18196ce68225SFeifei Xu #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 18206ce68225SFeifei Xu #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL 18216ce68225SFeifei Xu #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L 18226ce68225SFeifei Xu //RPB_SWITCH_CNTL2 18236ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 18246ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 18256ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe 18266ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 18276ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL 18286ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L 18296ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L 18306ce68225SFeifei Xu #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L 18316ce68225SFeifei Xu //RPB_DEINTRLV_COMBINE_CNTL 18326ce68225SFeifei Xu #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 18336ce68225SFeifei Xu #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 18346ce68225SFeifei Xu #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 18356ce68225SFeifei Xu #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 18366ce68225SFeifei Xu #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 18376ce68225SFeifei Xu #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 18386ce68225SFeifei Xu //RPB_VC_SWITCH_RDWR 18396ce68225SFeifei Xu #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 18406ce68225SFeifei Xu #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 18416ce68225SFeifei Xu #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 18426ce68225SFeifei Xu #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 18436ce68225SFeifei Xu #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 18446ce68225SFeifei Xu #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 18456ce68225SFeifei Xu //RPB_PERFCOUNTER_LO 18466ce68225SFeifei Xu #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 18476ce68225SFeifei Xu #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 18486ce68225SFeifei Xu //RPB_PERFCOUNTER_HI 18496ce68225SFeifei Xu #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 18506ce68225SFeifei Xu #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 18516ce68225SFeifei Xu #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 18526ce68225SFeifei Xu #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 18536ce68225SFeifei Xu //RPB_PERFCOUNTER0_CFG 18546ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 18556ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 18566ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 18576ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 18586ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 18596ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 18606ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 18616ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 18626ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 18636ce68225SFeifei Xu #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 18646ce68225SFeifei Xu //RPB_PERFCOUNTER1_CFG 18656ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 18666ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 18676ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 18686ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 18696ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 18706ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 18716ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 18726ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 18736ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 18746ce68225SFeifei Xu #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 18756ce68225SFeifei Xu //RPB_PERFCOUNTER2_CFG 18766ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 18776ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 18786ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 18796ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 18806ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 18816ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 18826ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 18836ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 18846ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 18856ce68225SFeifei Xu #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 18866ce68225SFeifei Xu //RPB_PERFCOUNTER3_CFG 18876ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 18886ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 18896ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 18906ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 18916ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 18926ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 18936ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 18946ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 18956ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 18966ce68225SFeifei Xu #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 18976ce68225SFeifei Xu //RPB_PERFCOUNTER_RSLT_CNTL 18986ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 18996ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 19006ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 19016ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 19026ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 19036ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 19046ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 19056ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 19066ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 19076ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 19086ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 19096ce68225SFeifei Xu #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 19106ce68225SFeifei Xu //RPB_RD_QUEUE_CNTL 19116ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 19126ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 19136ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 19146ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 19156ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 19166ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 19176ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 19186ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 19196ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 19206ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 19216ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 19226ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 19236ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 19246ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 19256ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 19266ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 19276ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 19286ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 19296ce68225SFeifei Xu //RPB_RD_QUEUE_CNTL2 19306ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 19316ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 19326ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 19336ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 19346ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 19356ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 19366ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 19376ce68225SFeifei Xu #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 19386ce68225SFeifei Xu //RPB_WR_QUEUE_CNTL 19396ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 19406ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 19416ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 19426ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 19436ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 19446ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 19456ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 19466ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 19476ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 19486ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 19496ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 19506ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 19516ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 19526ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 19536ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 19546ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 19556ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 19566ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 19576ce68225SFeifei Xu //RPB_WR_QUEUE_CNTL2 19586ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 19596ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 19606ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 19616ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 19626ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 19636ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 19646ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 19656ce68225SFeifei Xu #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 19666ce68225SFeifei Xu //RPB_EA_QUEUE_WR 19676ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 19686ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 19696ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 19706ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb 19716ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL 19726ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L 19736ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L 19746ce68225SFeifei Xu #define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L 19756ce68225SFeifei Xu //RPB_ATS_CNTL 19766ce68225SFeifei Xu #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 19776ce68225SFeifei Xu #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 19786ce68225SFeifei Xu #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 19796ce68225SFeifei Xu #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 19806ce68225SFeifei Xu #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf 19816ce68225SFeifei Xu #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 19826ce68225SFeifei Xu #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 19836ce68225SFeifei Xu #define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 19846ce68225SFeifei Xu #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 19856ce68225SFeifei Xu #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 19866ce68225SFeifei Xu #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 19876ce68225SFeifei Xu #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 19886ce68225SFeifei Xu #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L 19896ce68225SFeifei Xu #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 19906ce68225SFeifei Xu #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 19916ce68225SFeifei Xu #define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L 19926ce68225SFeifei Xu //RPB_ATS_CNTL2 19936ce68225SFeifei Xu #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 19946ce68225SFeifei Xu #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 19956ce68225SFeifei Xu #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc 19966ce68225SFeifei Xu #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf 19976ce68225SFeifei Xu #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 19986ce68225SFeifei Xu #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL 19996ce68225SFeifei Xu #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L 20006ce68225SFeifei Xu #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L 20016ce68225SFeifei Xu #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L 20026ce68225SFeifei Xu #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L 20036ce68225SFeifei Xu //RPB_SDPPORT_CNTL 20046ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 20056ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 20066ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 20076ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 20086ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 20096ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 20106ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa 20116ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb 20126ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd 20136ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe 20146ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf 20156ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 20166ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 20176ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 20186ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 20196ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 20206ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 20216ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 20226ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 20236ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 20246ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 20256ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 20266ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 20276ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 20286ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 20296ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 20306ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L 20316ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L 20326ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L 20336ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L 20346ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L 20356ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L 20366ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L 20376ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L 20386ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 20396ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 20406ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 20416ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 20426ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 20436ce68225SFeifei Xu #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 20446ce68225SFeifei Xu 20456ce68225SFeifei Xu #endif 2046