1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 27 28 /* 29 * Supported ASIC types 30 */ 31 enum amd_asic_type { 32 CHIP_TAHITI = 0, 33 CHIP_PITCAIRN, 34 CHIP_VERDE, 35 CHIP_OLAND, 36 CHIP_HAINAN, 37 CHIP_BONAIRE, 38 CHIP_KAVERI, 39 CHIP_KABINI, 40 CHIP_HAWAII, 41 CHIP_MULLINS, 42 CHIP_TOPAZ, 43 CHIP_TONGA, 44 CHIP_FIJI, 45 CHIP_CARRIZO, 46 CHIP_STONEY, 47 CHIP_POLARIS10, 48 CHIP_POLARIS11, 49 CHIP_LAST, 50 }; 51 52 /* 53 * Chip flags 54 */ 55 enum amd_chip_flags { 56 AMD_ASIC_MASK = 0x0000ffffUL, 57 AMD_FLAGS_MASK = 0xffff0000UL, 58 AMD_IS_MOBILITY = 0x00010000UL, 59 AMD_IS_APU = 0x00020000UL, 60 AMD_IS_PX = 0x00040000UL, 61 AMD_EXP_HW_SUPPORT = 0x00080000UL, 62 }; 63 64 enum amd_ip_block_type { 65 AMD_IP_BLOCK_TYPE_COMMON, 66 AMD_IP_BLOCK_TYPE_GMC, 67 AMD_IP_BLOCK_TYPE_IH, 68 AMD_IP_BLOCK_TYPE_SMC, 69 AMD_IP_BLOCK_TYPE_DCE, 70 AMD_IP_BLOCK_TYPE_GFX, 71 AMD_IP_BLOCK_TYPE_SDMA, 72 AMD_IP_BLOCK_TYPE_UVD, 73 AMD_IP_BLOCK_TYPE_VCE, 74 AMD_IP_BLOCK_TYPE_ACP, 75 }; 76 77 enum amd_clockgating_state { 78 AMD_CG_STATE_GATE = 0, 79 AMD_CG_STATE_UNGATE, 80 }; 81 82 enum amd_powergating_state { 83 AMD_PG_STATE_GATE = 0, 84 AMD_PG_STATE_UNGATE, 85 }; 86 87 struct amd_vce_state { 88 /* vce clocks */ 89 u32 evclk; 90 u32 ecclk; 91 /* gpu clocks */ 92 u32 sclk; 93 u32 mclk; 94 u8 clk_idx; 95 u8 pstate; 96 }; 97 98 99 #define AMD_MAX_VCE_LEVELS 6 100 101 enum amd_vce_level { 102 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 103 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 104 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 105 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 106 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 107 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 108 }; 109 110 /* CG flags */ 111 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 112 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 113 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 114 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 115 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 116 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 117 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 118 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 119 #define AMD_CG_SUPPORT_MC_LS (1 << 8) 120 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 121 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 122 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 123 #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 124 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 125 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 126 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 127 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 128 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 129 130 /* PG flags */ 131 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 132 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 133 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 134 #define AMD_PG_SUPPORT_UVD (1 << 3) 135 #define AMD_PG_SUPPORT_VCE (1 << 4) 136 #define AMD_PG_SUPPORT_CP (1 << 5) 137 #define AMD_PG_SUPPORT_GDS (1 << 6) 138 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 139 #define AMD_PG_SUPPORT_SDMA (1 << 8) 140 #define AMD_PG_SUPPORT_ACP (1 << 9) 141 #define AMD_PG_SUPPORT_SAMU (1 << 10) 142 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 143 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 144 145 enum amd_pm_state_type { 146 /* not used for dpm */ 147 POWER_STATE_TYPE_DEFAULT, 148 POWER_STATE_TYPE_POWERSAVE, 149 /* user selectable states */ 150 POWER_STATE_TYPE_BATTERY, 151 POWER_STATE_TYPE_BALANCED, 152 POWER_STATE_TYPE_PERFORMANCE, 153 /* internal states */ 154 POWER_STATE_TYPE_INTERNAL_UVD, 155 POWER_STATE_TYPE_INTERNAL_UVD_SD, 156 POWER_STATE_TYPE_INTERNAL_UVD_HD, 157 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 158 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 159 POWER_STATE_TYPE_INTERNAL_BOOT, 160 POWER_STATE_TYPE_INTERNAL_THERMAL, 161 POWER_STATE_TYPE_INTERNAL_ACPI, 162 POWER_STATE_TYPE_INTERNAL_ULV, 163 POWER_STATE_TYPE_INTERNAL_3DPERF, 164 }; 165 166 struct amd_ip_funcs { 167 /* Name of IP block */ 168 char *name; 169 /* sets up early driver state (pre sw_init), does not configure hw - Optional */ 170 int (*early_init)(void *handle); 171 /* sets up late driver/hw state (post hw_init) - Optional */ 172 int (*late_init)(void *handle); 173 /* sets up driver state, does not configure hw */ 174 int (*sw_init)(void *handle); 175 /* tears down driver state, does not configure hw */ 176 int (*sw_fini)(void *handle); 177 /* sets up the hw state */ 178 int (*hw_init)(void *handle); 179 /* tears down the hw state */ 180 int (*hw_fini)(void *handle); 181 void (*late_fini)(void *handle); 182 /* handles IP specific hw/sw changes for suspend */ 183 int (*suspend)(void *handle); 184 /* handles IP specific hw/sw changes for resume */ 185 int (*resume)(void *handle); 186 /* returns current IP block idle status */ 187 bool (*is_idle)(void *handle); 188 /* poll for idle */ 189 int (*wait_for_idle)(void *handle); 190 /* check soft reset the IP block */ 191 bool (*check_soft_reset)(void *handle); 192 /* pre soft reset the IP block */ 193 int (*pre_soft_reset)(void *handle); 194 /* soft reset the IP block */ 195 int (*soft_reset)(void *handle); 196 /* post soft reset the IP block */ 197 int (*post_soft_reset)(void *handle); 198 /* enable/disable cg for the IP block */ 199 int (*set_clockgating_state)(void *handle, 200 enum amd_clockgating_state state); 201 /* enable/disable pg for the IP block */ 202 int (*set_powergating_state)(void *handle, 203 enum amd_powergating_state state); 204 }; 205 206 #endif /* __AMD_SHARED_H__ */ 207