1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #include <drm/amd_asic_type.h> 27 28 29 #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */ 30 31 /* 32 * Chip flags 33 */ 34 enum amd_chip_flags { 35 AMD_ASIC_MASK = 0x0000ffffUL, 36 AMD_FLAGS_MASK = 0xffff0000UL, 37 AMD_IS_MOBILITY = 0x00010000UL, 38 AMD_IS_APU = 0x00020000UL, 39 AMD_IS_PX = 0x00040000UL, 40 AMD_EXP_HW_SUPPORT = 0x00080000UL, 41 }; 42 43 enum amd_apu_flags { 44 AMD_APU_IS_RAVEN = 0x00000001UL, 45 AMD_APU_IS_RAVEN2 = 0x00000002UL, 46 AMD_APU_IS_PICASSO = 0x00000004UL, 47 AMD_APU_IS_RENOIR = 0x00000008UL, 48 }; 49 50 enum amd_ip_block_type { 51 AMD_IP_BLOCK_TYPE_COMMON, 52 AMD_IP_BLOCK_TYPE_GMC, 53 AMD_IP_BLOCK_TYPE_IH, 54 AMD_IP_BLOCK_TYPE_SMC, 55 AMD_IP_BLOCK_TYPE_PSP, 56 AMD_IP_BLOCK_TYPE_DCE, 57 AMD_IP_BLOCK_TYPE_GFX, 58 AMD_IP_BLOCK_TYPE_SDMA, 59 AMD_IP_BLOCK_TYPE_UVD, 60 AMD_IP_BLOCK_TYPE_VCE, 61 AMD_IP_BLOCK_TYPE_ACP, 62 AMD_IP_BLOCK_TYPE_VCN, 63 AMD_IP_BLOCK_TYPE_MES, 64 AMD_IP_BLOCK_TYPE_JPEG 65 }; 66 67 enum amd_clockgating_state { 68 AMD_CG_STATE_GATE = 0, 69 AMD_CG_STATE_UNGATE, 70 }; 71 72 73 enum amd_powergating_state { 74 AMD_PG_STATE_GATE = 0, 75 AMD_PG_STATE_UNGATE, 76 }; 77 78 79 /* CG flags */ 80 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 81 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 82 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 83 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 84 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 85 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 86 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 87 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 88 #define AMD_CG_SUPPORT_MC_LS (1 << 8) 89 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 90 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 91 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 92 #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 93 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 94 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 95 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 96 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 97 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 98 #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 99 #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 100 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 101 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 102 #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) 103 #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) 104 #define AMD_CG_SUPPORT_VCN_MGCG (1 << 24) 105 #define AMD_CG_SUPPORT_HDP_DS (1 << 25) 106 #define AMD_CG_SUPPORT_HDP_SD (1 << 26) 107 #define AMD_CG_SUPPORT_IH_CG (1 << 27) 108 #define AMD_CG_SUPPORT_ATHUB_LS (1 << 28) 109 #define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29) 110 #define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30) 111 /* PG flags */ 112 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 113 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 114 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 115 #define AMD_PG_SUPPORT_UVD (1 << 3) 116 #define AMD_PG_SUPPORT_VCE (1 << 4) 117 #define AMD_PG_SUPPORT_CP (1 << 5) 118 #define AMD_PG_SUPPORT_GDS (1 << 6) 119 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 120 #define AMD_PG_SUPPORT_SDMA (1 << 8) 121 #define AMD_PG_SUPPORT_ACP (1 << 9) 122 #define AMD_PG_SUPPORT_SAMU (1 << 10) 123 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 124 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 125 #define AMD_PG_SUPPORT_MMHUB (1 << 13) 126 #define AMD_PG_SUPPORT_VCN (1 << 14) 127 #define AMD_PG_SUPPORT_VCN_DPG (1 << 15) 128 #define AMD_PG_SUPPORT_ATHUB (1 << 16) 129 #define AMD_PG_SUPPORT_JPEG (1 << 17) 130 131 enum PP_FEATURE_MASK { 132 PP_SCLK_DPM_MASK = 0x1, 133 PP_MCLK_DPM_MASK = 0x2, 134 PP_PCIE_DPM_MASK = 0x4, 135 PP_SCLK_DEEP_SLEEP_MASK = 0x8, 136 PP_POWER_CONTAINMENT_MASK = 0x10, 137 PP_UVD_HANDSHAKE_MASK = 0x20, 138 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 139 PP_VBI_TIME_SUPPORT_MASK = 0x80, 140 PP_ULV_MASK = 0x100, 141 PP_ENABLE_GFX_CG_THRU_SMU = 0x200, 142 PP_CLOCK_STRETCH_MASK = 0x400, 143 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800, 144 PP_SOCCLK_DPM_MASK = 0x1000, 145 PP_DCEFCLK_DPM_MASK = 0x2000, 146 PP_OVERDRIVE_MASK = 0x4000, 147 PP_GFXOFF_MASK = 0x8000, 148 PP_ACG_MASK = 0x10000, 149 PP_STUTTER_MODE = 0x20000, 150 PP_AVFS_MASK = 0x40000, 151 }; 152 153 enum DC_FEATURE_MASK { 154 DC_FBC_MASK = 0x1, 155 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2, 156 DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4, 157 DC_PSR_MASK = 0x8, 158 }; 159 160 enum DC_DEBUG_MASK { 161 DC_DISABLE_PIPE_SPLIT = 0x1, 162 DC_DISABLE_STUTTER = 0x2, 163 DC_DISABLE_DSC = 0x4, 164 DC_DISABLE_CLOCK_GATING = 0x8 165 }; 166 167 enum amd_dpm_forced_level; 168 /** 169 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks 170 */ 171 struct amd_ip_funcs { 172 /** @name: Name of IP block */ 173 char *name; 174 /** 175 * @early_init: 176 * 177 * sets up early driver state (pre sw_init), 178 * does not configure hw - Optional 179 */ 180 int (*early_init)(void *handle); 181 /** @late_init: sets up late driver/hw state (post hw_init) - Optional */ 182 int (*late_init)(void *handle); 183 /** @sw_init: sets up driver state, does not configure hw */ 184 int (*sw_init)(void *handle); 185 /** @sw_fini: tears down driver state, does not configure hw */ 186 int (*sw_fini)(void *handle); 187 /** @hw_init: sets up the hw state */ 188 int (*hw_init)(void *handle); 189 /** @hw_fini: tears down the hw state */ 190 int (*hw_fini)(void *handle); 191 /** @late_fini: final cleanup */ 192 void (*late_fini)(void *handle); 193 /** @suspend: handles IP specific hw/sw changes for suspend */ 194 int (*suspend)(void *handle); 195 /** @resume: handles IP specific hw/sw changes for resume */ 196 int (*resume)(void *handle); 197 /** @is_idle: returns current IP block idle status */ 198 bool (*is_idle)(void *handle); 199 /** @wait_for_idle: poll for idle */ 200 int (*wait_for_idle)(void *handle); 201 /** @check_soft_reset: check soft reset the IP block */ 202 bool (*check_soft_reset)(void *handle); 203 /** @pre_soft_reset: pre soft reset the IP block */ 204 int (*pre_soft_reset)(void *handle); 205 /** @soft_reset: soft reset the IP block */ 206 int (*soft_reset)(void *handle); 207 /** @post_soft_reset: post soft reset the IP block */ 208 int (*post_soft_reset)(void *handle); 209 /** @set_clockgating_state: enable/disable cg for the IP block */ 210 int (*set_clockgating_state)(void *handle, 211 enum amd_clockgating_state state); 212 /** @set_powergating_state: enable/disable pg for the IP block */ 213 int (*set_powergating_state)(void *handle, 214 enum amd_powergating_state state); 215 /** @get_clockgating_state: get current clockgating status */ 216 void (*get_clockgating_state)(void *handle, u32 *flags); 217 /** @enable_umd_pstate: enable UMD powerstate */ 218 int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level); 219 }; 220 221 222 #endif /* __AMD_SHARED_H__ */ 223