1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ 27 28 struct seq_file; 29 30 /* 31 * Supported ASIC types 32 */ 33 enum amd_asic_type { 34 CHIP_TAHITI = 0, 35 CHIP_PITCAIRN, 36 CHIP_VERDE, 37 CHIP_OLAND, 38 CHIP_HAINAN, 39 CHIP_BONAIRE, 40 CHIP_KAVERI, 41 CHIP_KABINI, 42 CHIP_HAWAII, 43 CHIP_MULLINS, 44 CHIP_TOPAZ, 45 CHIP_TONGA, 46 CHIP_FIJI, 47 CHIP_CARRIZO, 48 CHIP_STONEY, 49 CHIP_POLARIS10, 50 CHIP_POLARIS11, 51 CHIP_POLARIS12, 52 CHIP_VEGA10, 53 CHIP_RAVEN, 54 CHIP_LAST, 55 }; 56 57 /* 58 * Chip flags 59 */ 60 enum amd_chip_flags { 61 AMD_ASIC_MASK = 0x0000ffffUL, 62 AMD_FLAGS_MASK = 0xffff0000UL, 63 AMD_IS_MOBILITY = 0x00010000UL, 64 AMD_IS_APU = 0x00020000UL, 65 AMD_IS_PX = 0x00040000UL, 66 AMD_EXP_HW_SUPPORT = 0x00080000UL, 67 }; 68 69 enum amd_ip_block_type { 70 AMD_IP_BLOCK_TYPE_COMMON, 71 AMD_IP_BLOCK_TYPE_GMC, 72 AMD_IP_BLOCK_TYPE_IH, 73 AMD_IP_BLOCK_TYPE_SMC, 74 AMD_IP_BLOCK_TYPE_PSP, 75 AMD_IP_BLOCK_TYPE_DCE, 76 AMD_IP_BLOCK_TYPE_GFX, 77 AMD_IP_BLOCK_TYPE_SDMA, 78 AMD_IP_BLOCK_TYPE_UVD, 79 AMD_IP_BLOCK_TYPE_VCE, 80 AMD_IP_BLOCK_TYPE_ACP, 81 AMD_IP_BLOCK_TYPE_VCN 82 }; 83 84 enum amd_clockgating_state { 85 AMD_CG_STATE_GATE = 0, 86 AMD_CG_STATE_UNGATE, 87 }; 88 89 enum amd_dpm_forced_level { 90 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 91 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 92 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 93 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 94 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 95 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 96 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 97 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 98 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 99 }; 100 101 enum amd_powergating_state { 102 AMD_PG_STATE_GATE = 0, 103 AMD_PG_STATE_UNGATE, 104 }; 105 106 struct amd_vce_state { 107 /* vce clocks */ 108 u32 evclk; 109 u32 ecclk; 110 /* gpu clocks */ 111 u32 sclk; 112 u32 mclk; 113 u8 clk_idx; 114 u8 pstate; 115 }; 116 117 118 #define AMD_MAX_VCE_LEVELS 6 119 120 enum amd_vce_level { 121 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 122 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 123 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 124 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 125 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 126 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 127 }; 128 129 enum amd_pp_profile_type { 130 AMD_PP_GFX_PROFILE, 131 AMD_PP_COMPUTE_PROFILE, 132 }; 133 134 struct amd_pp_profile { 135 enum amd_pp_profile_type type; 136 uint32_t min_sclk; 137 uint32_t min_mclk; 138 uint16_t activity_threshold; 139 uint8_t up_hyst; 140 uint8_t down_hyst; 141 }; 142 143 enum amd_fan_ctrl_mode { 144 AMD_FAN_CTRL_NONE = 0, 145 AMD_FAN_CTRL_MANUAL = 1, 146 AMD_FAN_CTRL_AUTO = 2, 147 }; 148 149 enum pp_clock_type { 150 PP_SCLK, 151 PP_MCLK, 152 PP_PCIE, 153 }; 154 155 /* CG flags */ 156 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 157 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 158 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 159 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 160 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 161 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 162 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 163 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 164 #define AMD_CG_SUPPORT_MC_LS (1 << 8) 165 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 166 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 167 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 168 #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 169 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 170 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 171 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 172 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 173 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 174 #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 175 #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 176 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 177 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 178 #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) 179 #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) 180 181 /* PG flags */ 182 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 183 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 184 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 185 #define AMD_PG_SUPPORT_UVD (1 << 3) 186 #define AMD_PG_SUPPORT_VCE (1 << 4) 187 #define AMD_PG_SUPPORT_CP (1 << 5) 188 #define AMD_PG_SUPPORT_GDS (1 << 6) 189 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 190 #define AMD_PG_SUPPORT_SDMA (1 << 8) 191 #define AMD_PG_SUPPORT_ACP (1 << 9) 192 #define AMD_PG_SUPPORT_SAMU (1 << 10) 193 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 194 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 195 #define AMD_PG_SUPPORT_MMHUB (1 << 13) 196 197 enum amd_pm_state_type { 198 /* not used for dpm */ 199 POWER_STATE_TYPE_DEFAULT, 200 POWER_STATE_TYPE_POWERSAVE, 201 /* user selectable states */ 202 POWER_STATE_TYPE_BATTERY, 203 POWER_STATE_TYPE_BALANCED, 204 POWER_STATE_TYPE_PERFORMANCE, 205 /* internal states */ 206 POWER_STATE_TYPE_INTERNAL_UVD, 207 POWER_STATE_TYPE_INTERNAL_UVD_SD, 208 POWER_STATE_TYPE_INTERNAL_UVD_HD, 209 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 210 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 211 POWER_STATE_TYPE_INTERNAL_BOOT, 212 POWER_STATE_TYPE_INTERNAL_THERMAL, 213 POWER_STATE_TYPE_INTERNAL_ACPI, 214 POWER_STATE_TYPE_INTERNAL_ULV, 215 POWER_STATE_TYPE_INTERNAL_3DPERF, 216 }; 217 218 struct amd_ip_funcs { 219 /* Name of IP block */ 220 char *name; 221 /* sets up early driver state (pre sw_init), does not configure hw - Optional */ 222 int (*early_init)(void *handle); 223 /* sets up late driver/hw state (post hw_init) - Optional */ 224 int (*late_init)(void *handle); 225 /* sets up driver state, does not configure hw */ 226 int (*sw_init)(void *handle); 227 /* tears down driver state, does not configure hw */ 228 int (*sw_fini)(void *handle); 229 /* sets up the hw state */ 230 int (*hw_init)(void *handle); 231 /* tears down the hw state */ 232 int (*hw_fini)(void *handle); 233 void (*late_fini)(void *handle); 234 /* handles IP specific hw/sw changes for suspend */ 235 int (*suspend)(void *handle); 236 /* handles IP specific hw/sw changes for resume */ 237 int (*resume)(void *handle); 238 /* returns current IP block idle status */ 239 bool (*is_idle)(void *handle); 240 /* poll for idle */ 241 int (*wait_for_idle)(void *handle); 242 /* check soft reset the IP block */ 243 bool (*check_soft_reset)(void *handle); 244 /* pre soft reset the IP block */ 245 int (*pre_soft_reset)(void *handle); 246 /* soft reset the IP block */ 247 int (*soft_reset)(void *handle); 248 /* post soft reset the IP block */ 249 int (*post_soft_reset)(void *handle); 250 /* enable/disable cg for the IP block */ 251 int (*set_clockgating_state)(void *handle, 252 enum amd_clockgating_state state); 253 /* enable/disable pg for the IP block */ 254 int (*set_powergating_state)(void *handle, 255 enum amd_powergating_state state); 256 /* get current clockgating status */ 257 void (*get_clockgating_state)(void *handle, u32 *flags); 258 }; 259 260 enum amd_pp_task; 261 262 struct pp_states_info; 263 264 struct amd_pm_funcs { 265 int (*get_temperature)(void *handle); 266 int (*pre_set_power_state)(void *handle); 267 int (*set_power_state)(void *handle); 268 void (*post_set_power_state)(void *handle); 269 void (*display_configuration_changed)(void *handle); 270 u32 (*get_sclk)(void *handle, bool low); 271 u32 (*get_mclk)(void *handle, bool low); 272 void (*print_power_state)(void *handle, void *ps); 273 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 274 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 275 bool (*vblank_too_short)(void *handle); 276 void (*powergate_uvd)(void *handle, bool gate); 277 void (*powergate_vce)(void *handle, bool gate); 278 void (*enable_bapm)(void *handle, bool enable); 279 void (*set_fan_control_mode)(void *handle, u32 mode); 280 u32 (*get_fan_control_mode)(void *handle); 281 int (*set_fan_speed_percent)(void *handle, u32 speed); 282 int (*get_fan_speed_percent)(void *handle, u32 *speed); 283 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 284 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 285 int (*get_sclk_od)(void *handle); 286 int (*set_sclk_od)(void *handle, uint32_t value); 287 int (*get_mclk_od)(void *handle); 288 int (*set_mclk_od)(void *handle, uint32_t value); 289 int (*check_state_equal)(void *handle, 290 void *cps, 291 void *rps, 292 bool *equal); 293 int (*read_sensor)(void *handle, int idx, void *value, 294 int *size); 295 296 struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx); 297 int (*reset_power_profile_state)(void *handle, 298 struct amd_pp_profile *request); 299 int (*get_power_profile_state)(void *handle, 300 struct amd_pp_profile *query); 301 int (*set_power_profile_state)(void *handle, 302 struct amd_pp_profile *request); 303 int (*switch_power_profile)(void *handle, 304 enum amd_pp_profile_type type); 305 int (*load_firmware)(void *handle); 306 int (*wait_for_fw_loading_complete)(void *handle); 307 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 308 enum amd_pm_state_type (*get_current_power_state)(void *handle); 309 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 310 void *input, void *output); 311 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 312 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 313 int (*get_pp_table)(void *handle, char **table); 314 int (*set_pp_table)(void *handle, const char *buf, size_t size); 315 }; 316 317 318 #endif /* __AMD_SHARED_H__ */ 319