1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 27 28 /* 29 * Supported GPU families (aligned with amdgpu_drm.h) 30 */ 31 #define AMD_FAMILY_UNKNOWN 0 32 #define AMD_FAMILY_CI 120 /* Bonaire, Hawaii */ 33 #define AMD_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 34 #define AMD_FAMILY_VI 130 /* Iceland, Tonga */ 35 #define AMD_FAMILY_CZ 135 /* Carrizo */ 36 37 /* 38 * Supported ASIC types 39 */ 40 enum amd_asic_type { 41 CHIP_BONAIRE = 0, 42 CHIP_KAVERI, 43 CHIP_KABINI, 44 CHIP_HAWAII, 45 CHIP_MULLINS, 46 CHIP_TOPAZ, 47 CHIP_TONGA, 48 CHIP_FIJI, 49 CHIP_CARRIZO, 50 CHIP_STONEY, 51 CHIP_LAST, 52 }; 53 54 /* 55 * Chip flags 56 */ 57 enum amd_chip_flags { 58 AMD_ASIC_MASK = 0x0000ffffUL, 59 AMD_FLAGS_MASK = 0xffff0000UL, 60 AMD_IS_MOBILITY = 0x00010000UL, 61 AMD_IS_APU = 0x00020000UL, 62 AMD_IS_PX = 0x00040000UL, 63 AMD_EXP_HW_SUPPORT = 0x00080000UL, 64 }; 65 66 enum amd_ip_block_type { 67 AMD_IP_BLOCK_TYPE_COMMON, 68 AMD_IP_BLOCK_TYPE_GMC, 69 AMD_IP_BLOCK_TYPE_IH, 70 AMD_IP_BLOCK_TYPE_SMC, 71 AMD_IP_BLOCK_TYPE_DCE, 72 AMD_IP_BLOCK_TYPE_GFX, 73 AMD_IP_BLOCK_TYPE_SDMA, 74 AMD_IP_BLOCK_TYPE_UVD, 75 AMD_IP_BLOCK_TYPE_VCE, 76 AMD_IP_BLOCK_TYPE_ACP, 77 }; 78 79 enum amd_clockgating_state { 80 AMD_CG_STATE_GATE = 0, 81 AMD_CG_STATE_UNGATE, 82 }; 83 84 enum amd_powergating_state { 85 AMD_PG_STATE_GATE = 0, 86 AMD_PG_STATE_UNGATE, 87 }; 88 89 enum amd_pm_state_type { 90 /* not used for dpm */ 91 POWER_STATE_TYPE_DEFAULT, 92 POWER_STATE_TYPE_POWERSAVE, 93 /* user selectable states */ 94 POWER_STATE_TYPE_BATTERY, 95 POWER_STATE_TYPE_BALANCED, 96 POWER_STATE_TYPE_PERFORMANCE, 97 /* internal states */ 98 POWER_STATE_TYPE_INTERNAL_UVD, 99 POWER_STATE_TYPE_INTERNAL_UVD_SD, 100 POWER_STATE_TYPE_INTERNAL_UVD_HD, 101 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 102 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 103 POWER_STATE_TYPE_INTERNAL_BOOT, 104 POWER_STATE_TYPE_INTERNAL_THERMAL, 105 POWER_STATE_TYPE_INTERNAL_ACPI, 106 POWER_STATE_TYPE_INTERNAL_ULV, 107 POWER_STATE_TYPE_INTERNAL_3DPERF, 108 }; 109 110 struct amd_ip_funcs { 111 /* sets up early driver state (pre sw_init), does not configure hw - Optional */ 112 int (*early_init)(void *handle); 113 /* sets up late driver/hw state (post hw_init) - Optional */ 114 int (*late_init)(void *handle); 115 /* sets up driver state, does not configure hw */ 116 int (*sw_init)(void *handle); 117 /* tears down driver state, does not configure hw */ 118 int (*sw_fini)(void *handle); 119 /* sets up the hw state */ 120 int (*hw_init)(void *handle); 121 /* tears down the hw state */ 122 int (*hw_fini)(void *handle); 123 /* handles IP specific hw/sw changes for suspend */ 124 int (*suspend)(void *handle); 125 /* handles IP specific hw/sw changes for resume */ 126 int (*resume)(void *handle); 127 /* returns current IP block idle status */ 128 bool (*is_idle)(void *handle); 129 /* poll for idle */ 130 int (*wait_for_idle)(void *handle); 131 /* soft reset the IP block */ 132 int (*soft_reset)(void *handle); 133 /* dump the IP block status registers */ 134 void (*print_status)(void *handle); 135 /* enable/disable cg for the IP block */ 136 int (*set_clockgating_state)(void *handle, 137 enum amd_clockgating_state state); 138 /* enable/disable pg for the IP block */ 139 int (*set_powergating_state)(void *handle, 140 enum amd_powergating_state state); 141 }; 142 143 #endif /* __AMD_SHARED_H__ */ 144