1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ 27 28 /* 29 * Supported ASIC types 30 */ 31 enum amd_asic_type { 32 CHIP_TAHITI = 0, 33 CHIP_PITCAIRN, 34 CHIP_VERDE, 35 CHIP_OLAND, 36 CHIP_HAINAN, 37 CHIP_BONAIRE, 38 CHIP_KAVERI, 39 CHIP_KABINI, 40 CHIP_HAWAII, 41 CHIP_MULLINS, 42 CHIP_TOPAZ, 43 CHIP_TONGA, 44 CHIP_FIJI, 45 CHIP_CARRIZO, 46 CHIP_STONEY, 47 CHIP_POLARIS10, 48 CHIP_POLARIS11, 49 CHIP_POLARIS12, 50 CHIP_LAST, 51 }; 52 53 /* 54 * Chip flags 55 */ 56 enum amd_chip_flags { 57 AMD_ASIC_MASK = 0x0000ffffUL, 58 AMD_FLAGS_MASK = 0xffff0000UL, 59 AMD_IS_MOBILITY = 0x00010000UL, 60 AMD_IS_APU = 0x00020000UL, 61 AMD_IS_PX = 0x00040000UL, 62 AMD_EXP_HW_SUPPORT = 0x00080000UL, 63 }; 64 65 enum amd_ip_block_type { 66 AMD_IP_BLOCK_TYPE_COMMON, 67 AMD_IP_BLOCK_TYPE_GMC, 68 AMD_IP_BLOCK_TYPE_IH, 69 AMD_IP_BLOCK_TYPE_SMC, 70 AMD_IP_BLOCK_TYPE_DCE, 71 AMD_IP_BLOCK_TYPE_GFX, 72 AMD_IP_BLOCK_TYPE_SDMA, 73 AMD_IP_BLOCK_TYPE_UVD, 74 AMD_IP_BLOCK_TYPE_VCE, 75 AMD_IP_BLOCK_TYPE_ACP, 76 }; 77 78 enum amd_clockgating_state { 79 AMD_CG_STATE_GATE = 0, 80 AMD_CG_STATE_UNGATE, 81 }; 82 83 enum amd_dpm_forced_level { 84 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 85 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 86 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 87 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 88 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 89 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 90 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 91 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 92 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 93 }; 94 95 enum amd_powergating_state { 96 AMD_PG_STATE_GATE = 0, 97 AMD_PG_STATE_UNGATE, 98 }; 99 100 struct amd_vce_state { 101 /* vce clocks */ 102 u32 evclk; 103 u32 ecclk; 104 /* gpu clocks */ 105 u32 sclk; 106 u32 mclk; 107 u8 clk_idx; 108 u8 pstate; 109 }; 110 111 112 #define AMD_MAX_VCE_LEVELS 6 113 114 enum amd_vce_level { 115 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 116 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 117 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 118 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 119 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 120 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 121 }; 122 123 /* CG flags */ 124 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 125 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 126 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 127 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 128 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 129 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 130 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 131 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 132 #define AMD_CG_SUPPORT_MC_LS (1 << 8) 133 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 134 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 135 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 136 #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 137 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 138 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 139 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 140 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 141 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 142 #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 143 #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 144 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 145 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 146 147 /* PG flags */ 148 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 149 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 150 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 151 #define AMD_PG_SUPPORT_UVD (1 << 3) 152 #define AMD_PG_SUPPORT_VCE (1 << 4) 153 #define AMD_PG_SUPPORT_CP (1 << 5) 154 #define AMD_PG_SUPPORT_GDS (1 << 6) 155 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 156 #define AMD_PG_SUPPORT_SDMA (1 << 8) 157 #define AMD_PG_SUPPORT_ACP (1 << 9) 158 #define AMD_PG_SUPPORT_SAMU (1 << 10) 159 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 160 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 161 162 enum amd_pm_state_type { 163 /* not used for dpm */ 164 POWER_STATE_TYPE_DEFAULT, 165 POWER_STATE_TYPE_POWERSAVE, 166 /* user selectable states */ 167 POWER_STATE_TYPE_BATTERY, 168 POWER_STATE_TYPE_BALANCED, 169 POWER_STATE_TYPE_PERFORMANCE, 170 /* internal states */ 171 POWER_STATE_TYPE_INTERNAL_UVD, 172 POWER_STATE_TYPE_INTERNAL_UVD_SD, 173 POWER_STATE_TYPE_INTERNAL_UVD_HD, 174 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 175 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 176 POWER_STATE_TYPE_INTERNAL_BOOT, 177 POWER_STATE_TYPE_INTERNAL_THERMAL, 178 POWER_STATE_TYPE_INTERNAL_ACPI, 179 POWER_STATE_TYPE_INTERNAL_ULV, 180 POWER_STATE_TYPE_INTERNAL_3DPERF, 181 }; 182 183 struct amd_ip_funcs { 184 /* Name of IP block */ 185 char *name; 186 /* sets up early driver state (pre sw_init), does not configure hw - Optional */ 187 int (*early_init)(void *handle); 188 /* sets up late driver/hw state (post hw_init) - Optional */ 189 int (*late_init)(void *handle); 190 /* sets up driver state, does not configure hw */ 191 int (*sw_init)(void *handle); 192 /* tears down driver state, does not configure hw */ 193 int (*sw_fini)(void *handle); 194 /* sets up the hw state */ 195 int (*hw_init)(void *handle); 196 /* tears down the hw state */ 197 int (*hw_fini)(void *handle); 198 void (*late_fini)(void *handle); 199 /* handles IP specific hw/sw changes for suspend */ 200 int (*suspend)(void *handle); 201 /* handles IP specific hw/sw changes for resume */ 202 int (*resume)(void *handle); 203 /* returns current IP block idle status */ 204 bool (*is_idle)(void *handle); 205 /* poll for idle */ 206 int (*wait_for_idle)(void *handle); 207 /* check soft reset the IP block */ 208 bool (*check_soft_reset)(void *handle); 209 /* pre soft reset the IP block */ 210 int (*pre_soft_reset)(void *handle); 211 /* soft reset the IP block */ 212 int (*soft_reset)(void *handle); 213 /* post soft reset the IP block */ 214 int (*post_soft_reset)(void *handle); 215 /* enable/disable cg for the IP block */ 216 int (*set_clockgating_state)(void *handle, 217 enum amd_clockgating_state state); 218 /* enable/disable pg for the IP block */ 219 int (*set_powergating_state)(void *handle, 220 enum amd_powergating_state state); 221 /* get current clockgating status */ 222 void (*get_clockgating_state)(void *handle, u32 *flags); 223 }; 224 225 #endif /* __AMD_SHARED_H__ */ 226