1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #include <drm/amd_asic_type.h> 27 28 struct seq_file; 29 30 #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ 31 32 /* 33 * Chip flags 34 */ 35 enum amd_chip_flags { 36 AMD_ASIC_MASK = 0x0000ffffUL, 37 AMD_FLAGS_MASK = 0xffff0000UL, 38 AMD_IS_MOBILITY = 0x00010000UL, 39 AMD_IS_APU = 0x00020000UL, 40 AMD_IS_PX = 0x00040000UL, 41 AMD_EXP_HW_SUPPORT = 0x00080000UL, 42 }; 43 44 enum amd_ip_block_type { 45 AMD_IP_BLOCK_TYPE_COMMON, 46 AMD_IP_BLOCK_TYPE_GMC, 47 AMD_IP_BLOCK_TYPE_IH, 48 AMD_IP_BLOCK_TYPE_SMC, 49 AMD_IP_BLOCK_TYPE_PSP, 50 AMD_IP_BLOCK_TYPE_DCE, 51 AMD_IP_BLOCK_TYPE_GFX, 52 AMD_IP_BLOCK_TYPE_SDMA, 53 AMD_IP_BLOCK_TYPE_UVD, 54 AMD_IP_BLOCK_TYPE_VCE, 55 AMD_IP_BLOCK_TYPE_ACP, 56 AMD_IP_BLOCK_TYPE_VCN 57 }; 58 59 enum amd_clockgating_state { 60 AMD_CG_STATE_GATE = 0, 61 AMD_CG_STATE_UNGATE, 62 }; 63 64 enum amd_dpm_forced_level { 65 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 66 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 67 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 68 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 69 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 70 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 71 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 72 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 73 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 74 }; 75 76 enum amd_powergating_state { 77 AMD_PG_STATE_GATE = 0, 78 AMD_PG_STATE_UNGATE, 79 }; 80 81 struct amd_vce_state { 82 /* vce clocks */ 83 u32 evclk; 84 u32 ecclk; 85 /* gpu clocks */ 86 u32 sclk; 87 u32 mclk; 88 u8 clk_idx; 89 u8 pstate; 90 }; 91 92 93 #define AMD_MAX_VCE_LEVELS 6 94 95 enum amd_vce_level { 96 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 97 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 98 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 99 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 100 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 101 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 102 }; 103 104 enum amd_pp_profile_type { 105 AMD_PP_GFX_PROFILE, 106 AMD_PP_COMPUTE_PROFILE, 107 }; 108 109 struct amd_pp_profile { 110 enum amd_pp_profile_type type; 111 uint32_t min_sclk; 112 uint32_t min_mclk; 113 uint16_t activity_threshold; 114 uint8_t up_hyst; 115 uint8_t down_hyst; 116 }; 117 118 enum amd_fan_ctrl_mode { 119 AMD_FAN_CTRL_NONE = 0, 120 AMD_FAN_CTRL_MANUAL = 1, 121 AMD_FAN_CTRL_AUTO = 2, 122 }; 123 124 enum pp_clock_type { 125 PP_SCLK, 126 PP_MCLK, 127 PP_PCIE, 128 }; 129 130 /* CG flags */ 131 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 132 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 133 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 134 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 135 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 136 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 137 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 138 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 139 #define AMD_CG_SUPPORT_MC_LS (1 << 8) 140 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 141 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 142 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 143 #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 144 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 145 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 146 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 147 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 148 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 149 #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 150 #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 151 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 152 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 153 #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) 154 #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) 155 156 /* PG flags */ 157 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 158 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 159 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 160 #define AMD_PG_SUPPORT_UVD (1 << 3) 161 #define AMD_PG_SUPPORT_VCE (1 << 4) 162 #define AMD_PG_SUPPORT_CP (1 << 5) 163 #define AMD_PG_SUPPORT_GDS (1 << 6) 164 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 165 #define AMD_PG_SUPPORT_SDMA (1 << 8) 166 #define AMD_PG_SUPPORT_ACP (1 << 9) 167 #define AMD_PG_SUPPORT_SAMU (1 << 10) 168 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 169 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 170 #define AMD_PG_SUPPORT_MMHUB (1 << 13) 171 172 enum amd_pm_state_type { 173 /* not used for dpm */ 174 POWER_STATE_TYPE_DEFAULT, 175 POWER_STATE_TYPE_POWERSAVE, 176 /* user selectable states */ 177 POWER_STATE_TYPE_BATTERY, 178 POWER_STATE_TYPE_BALANCED, 179 POWER_STATE_TYPE_PERFORMANCE, 180 /* internal states */ 181 POWER_STATE_TYPE_INTERNAL_UVD, 182 POWER_STATE_TYPE_INTERNAL_UVD_SD, 183 POWER_STATE_TYPE_INTERNAL_UVD_HD, 184 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 185 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 186 POWER_STATE_TYPE_INTERNAL_BOOT, 187 POWER_STATE_TYPE_INTERNAL_THERMAL, 188 POWER_STATE_TYPE_INTERNAL_ACPI, 189 POWER_STATE_TYPE_INTERNAL_ULV, 190 POWER_STATE_TYPE_INTERNAL_3DPERF, 191 }; 192 193 struct amd_ip_funcs { 194 /* Name of IP block */ 195 char *name; 196 /* sets up early driver state (pre sw_init), does not configure hw - Optional */ 197 int (*early_init)(void *handle); 198 /* sets up late driver/hw state (post hw_init) - Optional */ 199 int (*late_init)(void *handle); 200 /* sets up driver state, does not configure hw */ 201 int (*sw_init)(void *handle); 202 /* tears down driver state, does not configure hw */ 203 int (*sw_fini)(void *handle); 204 /* sets up the hw state */ 205 int (*hw_init)(void *handle); 206 /* tears down the hw state */ 207 int (*hw_fini)(void *handle); 208 void (*late_fini)(void *handle); 209 /* handles IP specific hw/sw changes for suspend */ 210 int (*suspend)(void *handle); 211 /* handles IP specific hw/sw changes for resume */ 212 int (*resume)(void *handle); 213 /* returns current IP block idle status */ 214 bool (*is_idle)(void *handle); 215 /* poll for idle */ 216 int (*wait_for_idle)(void *handle); 217 /* check soft reset the IP block */ 218 bool (*check_soft_reset)(void *handle); 219 /* pre soft reset the IP block */ 220 int (*pre_soft_reset)(void *handle); 221 /* soft reset the IP block */ 222 int (*soft_reset)(void *handle); 223 /* post soft reset the IP block */ 224 int (*post_soft_reset)(void *handle); 225 /* enable/disable cg for the IP block */ 226 int (*set_clockgating_state)(void *handle, 227 enum amd_clockgating_state state); 228 /* enable/disable pg for the IP block */ 229 int (*set_powergating_state)(void *handle, 230 enum amd_powergating_state state); 231 /* get current clockgating status */ 232 void (*get_clockgating_state)(void *handle, u32 *flags); 233 }; 234 235 236 enum amd_pp_task; 237 enum amd_pp_clock_type; 238 struct pp_states_info; 239 struct amd_pp_simple_clock_info; 240 struct amd_pp_display_configuration; 241 struct amd_pp_clock_info; 242 struct pp_display_clock_request; 243 struct pp_wm_sets_with_clock_ranges_soc15; 244 struct pp_clock_levels_with_voltage; 245 struct pp_clock_levels_with_latency; 246 struct amd_pp_clocks; 247 248 struct amd_pm_funcs { 249 /* export for dpm on ci and si */ 250 int (*pre_set_power_state)(void *handle); 251 int (*set_power_state)(void *handle); 252 void (*post_set_power_state)(void *handle); 253 void (*display_configuration_changed)(void *handle); 254 void (*print_power_state)(void *handle, void *ps); 255 bool (*vblank_too_short)(void *handle); 256 void (*enable_bapm)(void *handle, bool enable); 257 int (*check_state_equal)(void *handle, 258 void *cps, 259 void *rps, 260 bool *equal); 261 /* export for sysfs */ 262 int (*get_temperature)(void *handle); 263 void (*set_fan_control_mode)(void *handle, u32 mode); 264 u32 (*get_fan_control_mode)(void *handle); 265 int (*set_fan_speed_percent)(void *handle, u32 speed); 266 int (*get_fan_speed_percent)(void *handle, u32 *speed); 267 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 268 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 269 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 270 int (*get_sclk_od)(void *handle); 271 int (*set_sclk_od)(void *handle, uint32_t value); 272 int (*get_mclk_od)(void *handle); 273 int (*set_mclk_od)(void *handle, uint32_t value); 274 int (*read_sensor)(void *handle, int idx, void *value, int *size); 275 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 276 enum amd_pm_state_type (*get_current_power_state)(void *handle); 277 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 278 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 279 int (*get_pp_table)(void *handle, char **table); 280 int (*set_pp_table)(void *handle, const char *buf, size_t size); 281 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 282 283 int (*reset_power_profile_state)(void *handle, 284 struct amd_pp_profile *request); 285 int (*get_power_profile_state)(void *handle, 286 struct amd_pp_profile *query); 287 int (*set_power_profile_state)(void *handle, 288 struct amd_pp_profile *request); 289 int (*switch_power_profile)(void *handle, 290 enum amd_pp_profile_type type); 291 /* export to amdgpu */ 292 void (*powergate_uvd)(void *handle, bool gate); 293 void (*powergate_vce)(void *handle, bool gate); 294 struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx); 295 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 296 void *input, void *output); 297 int (*load_firmware)(void *handle); 298 int (*wait_for_fw_loading_complete)(void *handle); 299 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 300 /* export to DC */ 301 u32 (*get_sclk)(void *handle, bool low); 302 u32 (*get_mclk)(void *handle, bool low); 303 int (*display_configuration_change)(void *handle, 304 const struct amd_pp_display_configuration *input); 305 int (*get_display_power_level)(void *handle, 306 struct amd_pp_simple_clock_info *output); 307 int (*get_current_clocks)(void *handle, 308 struct amd_pp_clock_info *clocks); 309 int (*get_clock_by_type)(void *handle, 310 enum amd_pp_clock_type type, 311 struct amd_pp_clocks *clocks); 312 int (*get_clock_by_type_with_latency)(void *handle, 313 enum amd_pp_clock_type type, 314 struct pp_clock_levels_with_latency *clocks); 315 int (*get_clock_by_type_with_voltage)(void *handle, 316 enum amd_pp_clock_type type, 317 struct pp_clock_levels_with_voltage *clocks); 318 int (*set_watermarks_for_clocks_ranges)(void *handle, 319 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); 320 int (*display_clock_voltage_request)(void *handle, 321 struct pp_display_clock_request *clock); 322 int (*get_display_mode_validation_clocks)(void *handle, 323 struct amd_pp_simple_clock_info *clocks); 324 }; 325 326 327 #endif /* __AMD_SHARED_H__ */ 328