1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #ifndef __AMD_PCIE_H__
24 #define __AMD_PCIE_H__
25 
26 /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
27 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
28 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
29 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
30 #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
31 #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
32 
33 /* Following flags shows PCIe link speed supported by ASIC H/W.*/
34 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
35 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
36 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
37 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
38 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
39 
40 /* gen: chipset 1/2, asic 1/2/3 */
41 #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
42 				      | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
43 				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
44 				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
45 				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
46 
47 /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
48 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
49 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
50 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
51 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
52 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
53 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
54 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
55 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
56 
57 /* 1/2/4/8/16 lanes */
58 #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
59 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
60 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
61 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
62 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
63 
64 #endif
65