1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_LINK_SERVICE_TYPES_H__ 27 #define __DAL_LINK_SERVICE_TYPES_H__ 28 29 #include "grph_object_id.h" 30 #include "dal_types.h" 31 #include "irq_types.h" 32 33 /*struct mst_mgr_callback_object;*/ 34 struct ddc; 35 struct irq_manager; 36 37 enum { 38 MAX_CONTROLLER_NUM = 6 39 }; 40 41 enum dp_power_state { 42 DP_POWER_STATE_D0 = 1, 43 DP_POWER_STATE_D3 44 }; 45 46 enum edp_revision { 47 /* eDP version 1.1 or lower */ 48 EDP_REVISION_11 = 0x00, 49 /* eDP version 1.2 */ 50 EDP_REVISION_12 = 0x01, 51 /* eDP version 1.3 */ 52 EDP_REVISION_13 = 0x02 53 }; 54 55 enum { 56 LINK_RATE_REF_FREQ_IN_KHZ = 27000, /*27MHz*/ 57 BITS_PER_DP_BYTE = 10, 58 DATA_EFFICIENCY_8b_10b_x10000 = 8000, /* 80% data efficiency */ 59 DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100 = 97, /* 97% data efficiency when FEC is enabled */ 60 DATA_EFFICIENCY_128b_132b_x10000 = 9646, /* 96.71% data efficiency x 99.75% downspread factor */ 61 }; 62 63 enum link_training_result { 64 LINK_TRAINING_SUCCESS, 65 LINK_TRAINING_CR_FAIL_LANE0, 66 LINK_TRAINING_CR_FAIL_LANE1, 67 LINK_TRAINING_CR_FAIL_LANE23, 68 /* CR DONE bit is cleared during EQ step */ 69 LINK_TRAINING_EQ_FAIL_CR, 70 /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */ 71 LINK_TRAINING_EQ_FAIL_CR_PARTIAL, 72 /* other failure during EQ step */ 73 LINK_TRAINING_EQ_FAIL_EQ, 74 LINK_TRAINING_LQA_FAIL, 75 /* one of the CR,EQ or symbol lock is dropped */ 76 LINK_TRAINING_LINK_LOSS, 77 /* Abort link training (because sink unplugged) */ 78 LINK_TRAINING_ABORT, 79 DP_128b_132b_LT_FAILED, 80 DP_128b_132b_MAX_LOOP_COUNT_REACHED, 81 DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, 82 DP_128b_132b_CDS_DONE_TIMEOUT, 83 }; 84 85 enum lttpr_mode { 86 LTTPR_MODE_NON_LTTPR, 87 LTTPR_MODE_TRANSPARENT, 88 LTTPR_MODE_NON_TRANSPARENT, 89 }; 90 91 struct link_training_settings { 92 struct dc_link_settings link_settings; 93 94 /* TODO: turn lane settings below into mandatory fields 95 * as initial lane configuration 96 */ 97 enum dc_voltage_swing *voltage_swing; 98 enum dc_pre_emphasis *pre_emphasis; 99 enum dc_post_cursor2 *post_cursor2; 100 bool should_set_fec_ready; 101 /* TODO - factor lane_settings out because it changes during LT */ 102 union dc_dp_ffe_preset *ffe_preset; 103 104 uint16_t cr_pattern_time; 105 uint16_t eq_pattern_time; 106 uint16_t cds_pattern_time; 107 enum dc_dp_training_pattern pattern_for_cr; 108 enum dc_dp_training_pattern pattern_for_eq; 109 enum dc_dp_training_pattern pattern_for_cds; 110 111 uint32_t eq_wait_time_limit; 112 uint8_t eq_loop_count_limit; 113 uint32_t cds_wait_time_limit; 114 115 bool enhanced_framing; 116 enum lttpr_mode lttpr_mode; 117 118 /* disallow different lanes to have different lane settings */ 119 bool disallow_per_lane_settings; 120 /* dpcd lane settings will always use the same hw lane settings 121 * even if it doesn't match requested lane adjust */ 122 bool always_match_dpcd_with_hw_lane_settings; 123 124 /***************************************************************** 125 * training states - parameters that can change in link training 126 *****************************************************************/ 127 /* TODO: Move hw_lane_settings and dpcd_lane_settings 128 * along with lane adjust, lane align, offset and all 129 * other training states into a new structure called 130 * training states, so link_training_settings becomes 131 * a constant input pre-decided prior to link training. 132 * 133 * The goal is to strictly decouple link training settings 134 * decision making process from link training states to 135 * prevent it from messy code practice of changing training 136 * decision on the fly. 137 */ 138 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX]; 139 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]; 140 }; 141 142 /*TODO: Move this enum test harness*/ 143 /* Test patterns*/ 144 enum dp_test_pattern { 145 /* Input data is pass through Scrambler 146 * and 8b10b Encoder straight to output*/ 147 DP_TEST_PATTERN_VIDEO_MODE = 0, 148 149 /* phy test patterns*/ 150 DP_TEST_PATTERN_PHY_PATTERN_BEGIN, 151 DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN, 152 DP_TEST_PATTERN_SYMBOL_ERROR, 153 DP_TEST_PATTERN_PRBS7, 154 DP_TEST_PATTERN_80BIT_CUSTOM, 155 DP_TEST_PATTERN_CP2520_1, 156 DP_TEST_PATTERN_CP2520_2, 157 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2, 158 DP_TEST_PATTERN_CP2520_3, 159 DP_TEST_PATTERN_128b_132b_TPS1, 160 DP_TEST_PATTERN_128b_132b_TPS2, 161 DP_TEST_PATTERN_PRBS9, 162 DP_TEST_PATTERN_PRBS11, 163 DP_TEST_PATTERN_PRBS15, 164 DP_TEST_PATTERN_PRBS23, 165 DP_TEST_PATTERN_PRBS31, 166 DP_TEST_PATTERN_264BIT_CUSTOM, 167 DP_TEST_PATTERN_SQUARE_PULSE, 168 169 /* Link Training Patterns */ 170 DP_TEST_PATTERN_TRAINING_PATTERN1, 171 DP_TEST_PATTERN_TRAINING_PATTERN2, 172 DP_TEST_PATTERN_TRAINING_PATTERN3, 173 DP_TEST_PATTERN_TRAINING_PATTERN4, 174 DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE, 175 DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, 176 DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, 177 178 /* link test patterns*/ 179 DP_TEST_PATTERN_COLOR_SQUARES, 180 DP_TEST_PATTERN_COLOR_SQUARES_CEA, 181 DP_TEST_PATTERN_VERTICAL_BARS, 182 DP_TEST_PATTERN_HORIZONTAL_BARS, 183 DP_TEST_PATTERN_COLOR_RAMP, 184 185 /* audio test patterns*/ 186 DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED, 187 DP_TEST_PATTERN_AUDIO_SAWTOOTH, 188 189 DP_TEST_PATTERN_UNSUPPORTED 190 }; 191 192 enum dp_test_pattern_color_space { 193 DP_TEST_PATTERN_COLOR_SPACE_RGB, 194 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601, 195 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709, 196 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED 197 }; 198 199 enum dp_panel_mode { 200 /* not required */ 201 DP_PANEL_MODE_DEFAULT, 202 /* standard mode for eDP */ 203 DP_PANEL_MODE_EDP, 204 /* external chips specific settings */ 205 DP_PANEL_MODE_SPECIAL 206 }; 207 208 enum dpcd_source_sequence { 209 DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG = 1, /*done in apply_single_controller_ctx_to_hw */ 210 DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR, /*done in core_link_enable_stream */ 211 DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME, /*done in core_link_enable_stream/dcn20_enable_stream */ 212 DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE, /*done in perform_link_training_with_retries/dcn20_enable_stream */ 213 DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY, /*done in dp_enable_link_phy */ 214 DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN, /*done in dp_set_hw_test_pattern */ 215 DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM, /*done in dce110_enable_audio_stream */ 216 DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_unblank */ 217 DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_blank */ 218 DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET, /*done in enc1_stream_encoder_dp_blank */ 219 DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM, /*done in dce110_disable_audio_stream */ 220 DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY, /*done in dp_disable_link_phy */ 221 DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE, /*done in dce110_disable_stream */ 222 }; 223 224 /* DPCD_ADDR_TRAINING_LANEx_SET registers value */ 225 union dpcd_training_lane_set { 226 struct { 227 #if defined(LITTLEENDIAN_CPU) 228 uint8_t VOLTAGE_SWING_SET:2; 229 uint8_t MAX_SWING_REACHED:1; 230 uint8_t PRE_EMPHASIS_SET:2; 231 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 232 /* following is reserved in DP 1.1 */ 233 uint8_t POST_CURSOR2_SET:2; 234 #elif defined(BIGENDIAN_CPU) 235 uint8_t POST_CURSOR2_SET:2; 236 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 237 uint8_t PRE_EMPHASIS_SET:2; 238 uint8_t MAX_SWING_REACHED:1; 239 uint8_t VOLTAGE_SWING_SET:2; 240 #else 241 #error ARCH not defined! 242 #endif 243 } bits; 244 245 uint8_t raw; 246 }; 247 248 249 /* DP MST stream allocation (payload bandwidth number) */ 250 struct dp_mst_stream_allocation { 251 uint8_t vcp_id; 252 /* number of slots required for the DP stream in 253 * transport packet */ 254 uint8_t slot_count; 255 }; 256 257 /* DP MST stream allocation table */ 258 struct dp_mst_stream_allocation_table { 259 /* number of DP video streams */ 260 int stream_count; 261 /* array of stream allocations */ 262 struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 263 }; 264 265 #endif /*__DAL_LINK_SERVICE_TYPES_H__*/ 266