1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_GRPH_OBJECT_ID_H__ 27 #define __DAL_GRPH_OBJECT_ID_H__ 28 29 /* Types of graphics objects */ 30 enum object_type { 31 OBJECT_TYPE_UNKNOWN = 0, 32 33 /* Direct ATOM BIOS translation */ 34 OBJECT_TYPE_GPU, 35 OBJECT_TYPE_ENCODER, 36 OBJECT_TYPE_CONNECTOR, 37 OBJECT_TYPE_ROUTER, 38 OBJECT_TYPE_GENERIC, 39 40 /* Driver specific */ 41 OBJECT_TYPE_AUDIO, 42 OBJECT_TYPE_CONTROLLER, 43 OBJECT_TYPE_CLOCK_SOURCE, 44 OBJECT_TYPE_ENGINE, 45 46 OBJECT_TYPE_COUNT 47 }; 48 49 /* Enumeration inside one type of graphics objects */ 50 enum object_enum_id { 51 ENUM_ID_UNKNOWN = 0, 52 ENUM_ID_1, 53 ENUM_ID_2, 54 ENUM_ID_3, 55 ENUM_ID_4, 56 ENUM_ID_5, 57 ENUM_ID_6, 58 ENUM_ID_7, 59 60 ENUM_ID_COUNT 61 }; 62 63 /* Generic object ids */ 64 enum generic_id { 65 GENERIC_ID_UNKNOWN = 0, 66 GENERIC_ID_MXM_OPM, 67 GENERIC_ID_GLSYNC, 68 GENERIC_ID_STEREO, 69 70 GENERIC_ID_COUNT 71 }; 72 73 /* Controller object ids */ 74 enum controller_id { 75 CONTROLLER_ID_UNDEFINED = 0, 76 CONTROLLER_ID_D0, 77 CONTROLLER_ID_D1, 78 CONTROLLER_ID_D2, 79 CONTROLLER_ID_D3, 80 CONTROLLER_ID_D4, 81 CONTROLLER_ID_D5, 82 CONTROLLER_ID_UNDERLAY0, 83 CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0 84 }; 85 86 #define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0) 87 88 /* 89 * ClockSource object ids. 90 * We maintain the order matching (more or less) ATOM BIOS 91 * to improve optimized acquire 92 */ 93 enum clock_source_id { 94 CLOCK_SOURCE_ID_UNDEFINED = 0, 95 CLOCK_SOURCE_ID_PLL0, 96 CLOCK_SOURCE_ID_PLL1, 97 CLOCK_SOURCE_ID_PLL2, 98 CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */ 99 CLOCK_SOURCE_ID_DCPLL, 100 CLOCK_SOURCE_ID_DFS, /* DENTIST */ 101 CLOCK_SOURCE_ID_VCE, /* VCE does not need a real PLL */ 102 /* Used to distinguish between programming pixel clock and ID (Phy) clock */ 103 CLOCK_SOURCE_ID_DP_DTO, 104 105 CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/ 106 CLOCK_SOURCE_COMBO_PHY_PLL1, 107 CLOCK_SOURCE_COMBO_PHY_PLL2, 108 CLOCK_SOURCE_COMBO_PHY_PLL3, 109 CLOCK_SOURCE_COMBO_PHY_PLL4, 110 CLOCK_SOURCE_COMBO_PHY_PLL5, 111 CLOCK_SOURCE_COMBO_DISPLAY_PLL0 112 }; 113 114 /* Encoder object ids */ 115 enum encoder_id { 116 ENCODER_ID_UNKNOWN = 0, 117 118 /* Radeon Class Display Hardware */ 119 ENCODER_ID_INTERNAL_LVDS, 120 ENCODER_ID_INTERNAL_TMDS1, 121 ENCODER_ID_INTERNAL_TMDS2, 122 ENCODER_ID_INTERNAL_DAC1, 123 ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */ 124 125 /* External Third Party Encoders */ 126 ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */ 127 ENCODER_ID_INTERNAL_HDMI, 128 129 /* Kaledisope (KLDSCP) Class Display Hardware */ 130 ENCODER_ID_INTERNAL_KLDSCP_TMDS1, 131 ENCODER_ID_INTERNAL_KLDSCP_DAC1, 132 ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */ 133 /* External TMDS (dual link) */ 134 ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */ 135 ENCODER_ID_INTERNAL_DDI, 136 ENCODER_ID_INTERNAL_UNIPHY, 137 ENCODER_ID_INTERNAL_KLDSCP_LVTMA, 138 ENCODER_ID_INTERNAL_UNIPHY1, 139 ENCODER_ID_INTERNAL_UNIPHY2, 140 ENCODER_ID_EXTERNAL_NUTMEG, 141 ENCODER_ID_EXTERNAL_TRAVIS, 142 143 ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */ 144 ENCODER_ID_INTERNAL_UNIPHY3, 145 ENCODER_ID_INTERNAL_VIRTUAL, 146 }; 147 148 /* Connector object ids */ 149 enum connector_id { 150 CONNECTOR_ID_UNKNOWN = 0, 151 CONNECTOR_ID_SINGLE_LINK_DVII = 1, 152 CONNECTOR_ID_DUAL_LINK_DVII = 2, 153 CONNECTOR_ID_SINGLE_LINK_DVID = 3, 154 CONNECTOR_ID_DUAL_LINK_DVID = 4, 155 CONNECTOR_ID_VGA = 5, 156 CONNECTOR_ID_HDMI_TYPE_A = 12, 157 CONNECTOR_ID_LVDS = 14, 158 CONNECTOR_ID_PCIE = 16, 159 CONNECTOR_ID_HARDCODE_DVI = 18, 160 CONNECTOR_ID_DISPLAY_PORT = 19, 161 CONNECTOR_ID_EDP = 20, 162 CONNECTOR_ID_MXM = 21, 163 CONNECTOR_ID_WIRELESS = 22, 164 CONNECTOR_ID_MIRACAST = 23, 165 166 CONNECTOR_ID_VIRTUAL = 100 167 }; 168 169 /* Audio object ids */ 170 enum audio_id { 171 AUDIO_ID_UNKNOWN = 0, 172 AUDIO_ID_INTERNAL_AZALIA 173 }; 174 175 /* Engine object ids */ 176 enum engine_id { 177 ENGINE_ID_DIGA, 178 ENGINE_ID_DIGB, 179 ENGINE_ID_DIGC, 180 ENGINE_ID_DIGD, 181 ENGINE_ID_DIGE, 182 ENGINE_ID_DIGF, 183 ENGINE_ID_DIGG, 184 ENGINE_ID_DACA, 185 ENGINE_ID_DACB, 186 ENGINE_ID_VCE, /* wireless display pseudo-encoder */ 187 #if defined(CONFIG_DRM_AMD_DC_DCN) 188 ENGINE_ID_HPO_0, 189 ENGINE_ID_HPO_1, 190 ENGINE_ID_HPO_DP_0, 191 ENGINE_ID_HPO_DP_1, 192 ENGINE_ID_HPO_DP_2, 193 ENGINE_ID_HPO_DP_3, 194 #endif 195 ENGINE_ID_VIRTUAL, 196 197 ENGINE_ID_COUNT, 198 ENGINE_ID_UNKNOWN = (-1L) 199 }; 200 201 enum transmitter_color_depth { 202 TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */ 203 TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */ 204 TRANSMITTER_COLOR_DEPTH_36, /* 12 bits */ 205 TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */ 206 }; 207 208 enum dp_alt_mode { 209 DP_Alt_mode__Unknown = 0, 210 DP_Alt_mode__Connect, 211 DP_Alt_mode__NoConnect, 212 }; 213 /* 214 ***************************************************************************** 215 * graphics_object_id struct 216 * 217 * graphics_object_id is a very simple struct wrapping 32bit Graphics 218 * Object identication 219 * 220 * This struct should stay very simple 221 * No dependencies at all (no includes) 222 * No debug messages or asserts 223 * No #ifndef and preprocessor directives 224 * No grow in space (no more data member) 225 ***************************************************************************** 226 */ 227 228 struct graphics_object_id { 229 uint32_t id:8; 230 uint32_t enum_id:4; 231 uint32_t type:4; 232 uint32_t reserved:16; /* for padding. total size should be u32 */ 233 }; 234 235 /* some simple functions for convenient graphics_object_id handle */ 236 237 static inline struct graphics_object_id dal_graphics_object_id_init( 238 uint32_t id, 239 enum object_enum_id enum_id, 240 enum object_type type) 241 { 242 struct graphics_object_id result = { 243 id, enum_id, type, 0 244 }; 245 246 return result; 247 } 248 249 /* Based on internal data members memory layout */ 250 static inline uint32_t dal_graphics_object_id_to_uint( 251 struct graphics_object_id id) 252 { 253 return id.id + (id.enum_id << 0x8) + (id.type << 0xc); 254 } 255 256 static inline enum controller_id dal_graphics_object_id_get_controller_id( 257 struct graphics_object_id id) 258 { 259 if (id.type == OBJECT_TYPE_CONTROLLER) 260 return (enum controller_id) id.id; 261 return CONTROLLER_ID_UNDEFINED; 262 } 263 264 static inline enum clock_source_id dal_graphics_object_id_get_clock_source_id( 265 struct graphics_object_id id) 266 { 267 if (id.type == OBJECT_TYPE_CLOCK_SOURCE) 268 return (enum clock_source_id) id.id; 269 return CLOCK_SOURCE_ID_UNDEFINED; 270 } 271 272 static inline enum encoder_id dal_graphics_object_id_get_encoder_id( 273 struct graphics_object_id id) 274 { 275 if (id.type == OBJECT_TYPE_ENCODER) 276 return (enum encoder_id) id.id; 277 return ENCODER_ID_UNKNOWN; 278 } 279 280 static inline enum connector_id dal_graphics_object_id_get_connector_id( 281 struct graphics_object_id id) 282 { 283 if (id.type == OBJECT_TYPE_CONNECTOR) 284 return (enum connector_id) id.id; 285 return CONNECTOR_ID_UNKNOWN; 286 } 287 288 static inline enum audio_id dal_graphics_object_id_get_audio_id( 289 struct graphics_object_id id) 290 { 291 if (id.type == OBJECT_TYPE_AUDIO) 292 return (enum audio_id) id.id; 293 return AUDIO_ID_UNKNOWN; 294 } 295 296 static inline enum engine_id dal_graphics_object_id_get_engine_id( 297 struct graphics_object_id id) 298 { 299 if (id.type == OBJECT_TYPE_ENGINE) 300 return (enum engine_id) id.id; 301 return ENGINE_ID_UNKNOWN; 302 } 303 304 static inline bool dal_graphics_object_id_equal( 305 struct graphics_object_id id_1, 306 struct graphics_object_id id_2) 307 { 308 if ((id_1.id == id_2.id) && (id_1.enum_id == id_2.enum_id) && 309 (id_1.type == id_2.type)) { 310 return true; 311 } 312 return false; 313 } 314 #endif 315