1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DPCD_DEFS_H__ 27 #define __DAL_DPCD_DEFS_H__ 28 29 #include <drm/drm_dp_helper.h> 30 31 enum dpcd_revision { 32 DPCD_REV_10 = 0x10, 33 DPCD_REV_11 = 0x11, 34 DPCD_REV_12 = 0x12, 35 DPCD_REV_13 = 0x13, 36 DPCD_REV_14 = 0x14 37 }; 38 39 /* these are the types stored at DOWNSTREAMPORT_PRESENT */ 40 enum dpcd_downstream_port_type { 41 DOWNSTREAM_DP = 0, 42 DOWNSTREAM_VGA, 43 DOWNSTREAM_DVI_HDMI, 44 DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ 45 }; 46 47 enum dpcd_link_test_patterns { 48 LINK_TEST_PATTERN_NONE = 0, 49 LINK_TEST_PATTERN_COLOR_RAMP, 50 LINK_TEST_PATTERN_VERTICAL_BARS, 51 LINK_TEST_PATTERN_COLOR_SQUARES 52 }; 53 54 enum dpcd_test_color_format { 55 TEST_COLOR_FORMAT_RGB = 0, 56 TEST_COLOR_FORMAT_YCBCR422, 57 TEST_COLOR_FORMAT_YCBCR444 58 }; 59 60 enum dpcd_test_bit_depth { 61 TEST_BIT_DEPTH_6 = 0, 62 TEST_BIT_DEPTH_8, 63 TEST_BIT_DEPTH_10, 64 TEST_BIT_DEPTH_12, 65 TEST_BIT_DEPTH_16 66 }; 67 68 /* PHY (encoder) test patterns 69 The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248) 70 */ 71 enum dpcd_phy_test_patterns { 72 PHY_TEST_PATTERN_NONE = 0, 73 PHY_TEST_PATTERN_D10_2, 74 PHY_TEST_PATTERN_SYMBOL_ERROR, 75 PHY_TEST_PATTERN_PRBS7, 76 PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */ 77 PHY_TEST_PATTERN_CP2520_1, 78 PHY_TEST_PATTERN_CP2520_2, 79 PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */ 80 }; 81 82 enum dpcd_test_dyn_range { 83 TEST_DYN_RANGE_VESA = 0, 84 TEST_DYN_RANGE_CEA 85 }; 86 87 enum dpcd_audio_test_pattern { 88 AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */ 89 AUDIO_TEST_PATTERN_SAWTOOTH 90 }; 91 92 enum dpcd_audio_sampling_rate { 93 AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */ 94 AUDIO_SAMPLING_RATE_44_1KHZ, 95 AUDIO_SAMPLING_RATE_48KHZ, 96 AUDIO_SAMPLING_RATE_88_2KHZ, 97 AUDIO_SAMPLING_RATE_96KHZ, 98 AUDIO_SAMPLING_RATE_176_4KHZ, 99 AUDIO_SAMPLING_RATE_192KHZ 100 }; 101 102 enum dpcd_audio_channels { 103 AUDIO_CHANNELS_1 = 0,/* direct HW translation */ 104 AUDIO_CHANNELS_2, 105 AUDIO_CHANNELS_3, 106 AUDIO_CHANNELS_4, 107 AUDIO_CHANNELS_5, 108 AUDIO_CHANNELS_6, 109 AUDIO_CHANNELS_7, 110 AUDIO_CHANNELS_8, 111 112 AUDIO_CHANNELS_COUNT 113 }; 114 115 enum dpcd_audio_test_pattern_periods { 116 DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */ 117 DPCD_AUDIO_TEST_PATTERN_PERIOD_3, 118 DPCD_AUDIO_TEST_PATTERN_PERIOD_6, 119 DPCD_AUDIO_TEST_PATTERN_PERIOD_12, 120 DPCD_AUDIO_TEST_PATTERN_PERIOD_24, 121 DPCD_AUDIO_TEST_PATTERN_PERIOD_48, 122 DPCD_AUDIO_TEST_PATTERN_PERIOD_96, 123 DPCD_AUDIO_TEST_PATTERN_PERIOD_192, 124 DPCD_AUDIO_TEST_PATTERN_PERIOD_384, 125 DPCD_AUDIO_TEST_PATTERN_PERIOD_768, 126 DPCD_AUDIO_TEST_PATTERN_PERIOD_1536 127 }; 128 129 /* This enum is for programming DPCD TRAINING_PATTERN_SET */ 130 enum dpcd_training_patterns { 131 DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */ 132 DPCD_TRAINING_PATTERN_1, 133 DPCD_TRAINING_PATTERN_2, 134 DPCD_TRAINING_PATTERN_3, 135 DPCD_TRAINING_PATTERN_4 = 7 136 }; 137 138 /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus 139 It defines the possible PSR states. */ 140 enum dpcd_psr_sink_states { 141 PSR_SINK_STATE_INACTIVE = 0, 142 PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1, 143 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2, 144 PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3, 145 PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4, 146 PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, 147 }; 148 149 #endif /* __DAL_DPCD_DEFS_H__ */ 150