14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef __DAL_DPCD_DEFS_H__ 274562236bSHarry Wentland #define __DAL_DPCD_DEFS_H__ 284562236bSHarry Wentland 293a340294SDave Airlie #include <drm/drm_dp_helper.h> 304b99affbSAlvin lee #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h 314b99affbSAlvin lee #define DP_SINK_HW_REVISION_START 0x409 324b99affbSAlvin lee #endif 334562236bSHarry Wentland 344562236bSHarry Wentland enum dpcd_revision { 354562236bSHarry Wentland DPCD_REV_10 = 0x10, 364562236bSHarry Wentland DPCD_REV_11 = 0x11, 374562236bSHarry Wentland DPCD_REV_12 = 0x12, 384562236bSHarry Wentland DPCD_REV_13 = 0x13, 394562236bSHarry Wentland DPCD_REV_14 = 0x14 404562236bSHarry Wentland }; 414562236bSHarry Wentland 424562236bSHarry Wentland /* these are the types stored at DOWNSTREAMPORT_PRESENT */ 434562236bSHarry Wentland enum dpcd_downstream_port_type { 444562236bSHarry Wentland DOWNSTREAM_DP = 0, 454562236bSHarry Wentland DOWNSTREAM_VGA, 46b7066693SDale Zhao DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */ 474562236bSHarry Wentland DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ 484562236bSHarry Wentland }; 494562236bSHarry Wentland 504562236bSHarry Wentland enum dpcd_link_test_patterns { 514562236bSHarry Wentland LINK_TEST_PATTERN_NONE = 0, 524562236bSHarry Wentland LINK_TEST_PATTERN_COLOR_RAMP, 534562236bSHarry Wentland LINK_TEST_PATTERN_VERTICAL_BARS, 544562236bSHarry Wentland LINK_TEST_PATTERN_COLOR_SQUARES 554562236bSHarry Wentland }; 564562236bSHarry Wentland 574562236bSHarry Wentland enum dpcd_test_color_format { 584562236bSHarry Wentland TEST_COLOR_FORMAT_RGB = 0, 594562236bSHarry Wentland TEST_COLOR_FORMAT_YCBCR422, 604562236bSHarry Wentland TEST_COLOR_FORMAT_YCBCR444 614562236bSHarry Wentland }; 624562236bSHarry Wentland 634562236bSHarry Wentland enum dpcd_test_bit_depth { 644562236bSHarry Wentland TEST_BIT_DEPTH_6 = 0, 654562236bSHarry Wentland TEST_BIT_DEPTH_8, 664562236bSHarry Wentland TEST_BIT_DEPTH_10, 674562236bSHarry Wentland TEST_BIT_DEPTH_12, 684562236bSHarry Wentland TEST_BIT_DEPTH_16 694562236bSHarry Wentland }; 704562236bSHarry Wentland 714562236bSHarry Wentland /* PHY (encoder) test patterns 724562236bSHarry Wentland The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248) 734562236bSHarry Wentland */ 744562236bSHarry Wentland enum dpcd_phy_test_patterns { 754562236bSHarry Wentland PHY_TEST_PATTERN_NONE = 0, 764562236bSHarry Wentland PHY_TEST_PATTERN_D10_2, 774562236bSHarry Wentland PHY_TEST_PATTERN_SYMBOL_ERROR, 784562236bSHarry Wentland PHY_TEST_PATTERN_PRBS7, 794562236bSHarry Wentland PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */ 800e19401fSTony Cheng PHY_TEST_PATTERN_CP2520_1, 810e19401fSTony Cheng PHY_TEST_PATTERN_CP2520_2, 820e19401fSTony Cheng PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */ 834562236bSHarry Wentland }; 844562236bSHarry Wentland 854562236bSHarry Wentland enum dpcd_test_dyn_range { 864562236bSHarry Wentland TEST_DYN_RANGE_VESA = 0, 874562236bSHarry Wentland TEST_DYN_RANGE_CEA 884562236bSHarry Wentland }; 894562236bSHarry Wentland 904562236bSHarry Wentland enum dpcd_audio_test_pattern { 914562236bSHarry Wentland AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */ 924562236bSHarry Wentland AUDIO_TEST_PATTERN_SAWTOOTH 934562236bSHarry Wentland }; 944562236bSHarry Wentland 954562236bSHarry Wentland enum dpcd_audio_sampling_rate { 964562236bSHarry Wentland AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */ 974562236bSHarry Wentland AUDIO_SAMPLING_RATE_44_1KHZ, 984562236bSHarry Wentland AUDIO_SAMPLING_RATE_48KHZ, 994562236bSHarry Wentland AUDIO_SAMPLING_RATE_88_2KHZ, 1004562236bSHarry Wentland AUDIO_SAMPLING_RATE_96KHZ, 1014562236bSHarry Wentland AUDIO_SAMPLING_RATE_176_4KHZ, 1024562236bSHarry Wentland AUDIO_SAMPLING_RATE_192KHZ 1034562236bSHarry Wentland }; 1044562236bSHarry Wentland 1054562236bSHarry Wentland enum dpcd_audio_channels { 1064562236bSHarry Wentland AUDIO_CHANNELS_1 = 0,/* direct HW translation */ 1074562236bSHarry Wentland AUDIO_CHANNELS_2, 1084562236bSHarry Wentland AUDIO_CHANNELS_3, 1094562236bSHarry Wentland AUDIO_CHANNELS_4, 1104562236bSHarry Wentland AUDIO_CHANNELS_5, 1114562236bSHarry Wentland AUDIO_CHANNELS_6, 1124562236bSHarry Wentland AUDIO_CHANNELS_7, 1134562236bSHarry Wentland AUDIO_CHANNELS_8, 1144562236bSHarry Wentland 1154562236bSHarry Wentland AUDIO_CHANNELS_COUNT 1164562236bSHarry Wentland }; 1174562236bSHarry Wentland 1184562236bSHarry Wentland enum dpcd_audio_test_pattern_periods { 1194562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */ 1204562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_3, 1214562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_6, 1224562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_12, 1234562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_24, 1244562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_48, 1254562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_96, 1264562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_192, 1274562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_384, 1284562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_768, 1294562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_1536 1304562236bSHarry Wentland }; 1314562236bSHarry Wentland 1324562236bSHarry Wentland /* This enum is for programming DPCD TRAINING_PATTERN_SET */ 1334562236bSHarry Wentland enum dpcd_training_patterns { 1344562236bSHarry Wentland DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */ 1354562236bSHarry Wentland DPCD_TRAINING_PATTERN_1, 1364562236bSHarry Wentland DPCD_TRAINING_PATTERN_2, 1374562236bSHarry Wentland DPCD_TRAINING_PATTERN_3, 1384562236bSHarry Wentland DPCD_TRAINING_PATTERN_4 = 7 1394562236bSHarry Wentland }; 1404562236bSHarry Wentland 1414562236bSHarry Wentland /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus 1424562236bSHarry Wentland It defines the possible PSR states. */ 1434562236bSHarry Wentland enum dpcd_psr_sink_states { 1444562236bSHarry Wentland PSR_SINK_STATE_INACTIVE = 0, 1454562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1, 1464562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2, 1474562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3, 1484562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4, 1494562236bSHarry Wentland PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, 1504562236bSHarry Wentland }; 1514562236bSHarry Wentland 1528a683eb6SRodrigo Siqueira #define DP_SOURCE_TABLE_REVISION 0x310 1538a683eb6SRodrigo Siqueira #define DP_SOURCE_PAYLOAD_SIZE 0x311 1548a683eb6SRodrigo Siqueira #define DP_SOURCE_SINK_CAP 0x317 1558a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_LEVEL 0x320 1568a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326 1578a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_CONTROL 0x32E 1588a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_ENABLE 0x32F 1598a683eb6SRodrigo Siqueira 1604562236bSHarry Wentland #endif /* __DAL_DPCD_DEFS_H__ */ 161