14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef __DAL_DPCD_DEFS_H__ 274562236bSHarry Wentland #define __DAL_DPCD_DEFS_H__ 284562236bSHarry Wentland 293a340294SDave Airlie #include <drm/drm_dp_helper.h> 304562236bSHarry Wentland 314562236bSHarry Wentland enum dpcd_revision { 324562236bSHarry Wentland DPCD_REV_10 = 0x10, 334562236bSHarry Wentland DPCD_REV_11 = 0x11, 344562236bSHarry Wentland DPCD_REV_12 = 0x12, 354562236bSHarry Wentland DPCD_REV_13 = 0x13, 364562236bSHarry Wentland DPCD_REV_14 = 0x14 374562236bSHarry Wentland }; 384562236bSHarry Wentland 394562236bSHarry Wentland /* these are the types stored at DOWNSTREAMPORT_PRESENT */ 404562236bSHarry Wentland enum dpcd_downstream_port_type { 414562236bSHarry Wentland DOWNSTREAM_DP = 0, 424562236bSHarry Wentland DOWNSTREAM_VGA, 434562236bSHarry Wentland DOWNSTREAM_DVI_HDMI, 444562236bSHarry Wentland DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ 454562236bSHarry Wentland }; 464562236bSHarry Wentland 474562236bSHarry Wentland enum dpcd_link_test_patterns { 484562236bSHarry Wentland LINK_TEST_PATTERN_NONE = 0, 494562236bSHarry Wentland LINK_TEST_PATTERN_COLOR_RAMP, 504562236bSHarry Wentland LINK_TEST_PATTERN_VERTICAL_BARS, 514562236bSHarry Wentland LINK_TEST_PATTERN_COLOR_SQUARES 524562236bSHarry Wentland }; 534562236bSHarry Wentland 544562236bSHarry Wentland enum dpcd_test_color_format { 554562236bSHarry Wentland TEST_COLOR_FORMAT_RGB = 0, 564562236bSHarry Wentland TEST_COLOR_FORMAT_YCBCR422, 574562236bSHarry Wentland TEST_COLOR_FORMAT_YCBCR444 584562236bSHarry Wentland }; 594562236bSHarry Wentland 604562236bSHarry Wentland enum dpcd_test_bit_depth { 614562236bSHarry Wentland TEST_BIT_DEPTH_6 = 0, 624562236bSHarry Wentland TEST_BIT_DEPTH_8, 634562236bSHarry Wentland TEST_BIT_DEPTH_10, 644562236bSHarry Wentland TEST_BIT_DEPTH_12, 654562236bSHarry Wentland TEST_BIT_DEPTH_16 664562236bSHarry Wentland }; 674562236bSHarry Wentland 684562236bSHarry Wentland /* PHY (encoder) test patterns 694562236bSHarry Wentland The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248) 704562236bSHarry Wentland */ 714562236bSHarry Wentland enum dpcd_phy_test_patterns { 724562236bSHarry Wentland PHY_TEST_PATTERN_NONE = 0, 734562236bSHarry Wentland PHY_TEST_PATTERN_D10_2, 744562236bSHarry Wentland PHY_TEST_PATTERN_SYMBOL_ERROR, 754562236bSHarry Wentland PHY_TEST_PATTERN_PRBS7, 764562236bSHarry Wentland PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */ 774562236bSHarry Wentland PHY_TEST_PATTERN_HBR2_COMPLIANCE_EYE/* For DP1.2 only */ 784562236bSHarry Wentland }; 794562236bSHarry Wentland 804562236bSHarry Wentland enum dpcd_test_dyn_range { 814562236bSHarry Wentland TEST_DYN_RANGE_VESA = 0, 824562236bSHarry Wentland TEST_DYN_RANGE_CEA 834562236bSHarry Wentland }; 844562236bSHarry Wentland 854562236bSHarry Wentland enum dpcd_audio_test_pattern { 864562236bSHarry Wentland AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */ 874562236bSHarry Wentland AUDIO_TEST_PATTERN_SAWTOOTH 884562236bSHarry Wentland }; 894562236bSHarry Wentland 904562236bSHarry Wentland enum dpcd_audio_sampling_rate { 914562236bSHarry Wentland AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */ 924562236bSHarry Wentland AUDIO_SAMPLING_RATE_44_1KHZ, 934562236bSHarry Wentland AUDIO_SAMPLING_RATE_48KHZ, 944562236bSHarry Wentland AUDIO_SAMPLING_RATE_88_2KHZ, 954562236bSHarry Wentland AUDIO_SAMPLING_RATE_96KHZ, 964562236bSHarry Wentland AUDIO_SAMPLING_RATE_176_4KHZ, 974562236bSHarry Wentland AUDIO_SAMPLING_RATE_192KHZ 984562236bSHarry Wentland }; 994562236bSHarry Wentland 1004562236bSHarry Wentland enum dpcd_audio_channels { 1014562236bSHarry Wentland AUDIO_CHANNELS_1 = 0,/* direct HW translation */ 1024562236bSHarry Wentland AUDIO_CHANNELS_2, 1034562236bSHarry Wentland AUDIO_CHANNELS_3, 1044562236bSHarry Wentland AUDIO_CHANNELS_4, 1054562236bSHarry Wentland AUDIO_CHANNELS_5, 1064562236bSHarry Wentland AUDIO_CHANNELS_6, 1074562236bSHarry Wentland AUDIO_CHANNELS_7, 1084562236bSHarry Wentland AUDIO_CHANNELS_8, 1094562236bSHarry Wentland 1104562236bSHarry Wentland AUDIO_CHANNELS_COUNT 1114562236bSHarry Wentland }; 1124562236bSHarry Wentland 1134562236bSHarry Wentland enum dpcd_audio_test_pattern_periods { 1144562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */ 1154562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_3, 1164562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_6, 1174562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_12, 1184562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_24, 1194562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_48, 1204562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_96, 1214562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_192, 1224562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_384, 1234562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_768, 1244562236bSHarry Wentland DPCD_AUDIO_TEST_PATTERN_PERIOD_1536 1254562236bSHarry Wentland }; 1264562236bSHarry Wentland 1274562236bSHarry Wentland /* This enum is for programming DPCD TRAINING_PATTERN_SET */ 1284562236bSHarry Wentland enum dpcd_training_patterns { 1294562236bSHarry Wentland DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */ 1304562236bSHarry Wentland DPCD_TRAINING_PATTERN_1, 1314562236bSHarry Wentland DPCD_TRAINING_PATTERN_2, 1324562236bSHarry Wentland DPCD_TRAINING_PATTERN_3, 1334562236bSHarry Wentland DPCD_TRAINING_PATTERN_4 = 7 1344562236bSHarry Wentland }; 1354562236bSHarry Wentland 1364562236bSHarry Wentland /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus 1374562236bSHarry Wentland It defines the possible PSR states. */ 1384562236bSHarry Wentland enum dpcd_psr_sink_states { 1394562236bSHarry Wentland PSR_SINK_STATE_INACTIVE = 0, 1404562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1, 1414562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2, 1424562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3, 1434562236bSHarry Wentland PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4, 1444562236bSHarry Wentland PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, 1454562236bSHarry Wentland }; 1464562236bSHarry Wentland 1474562236bSHarry Wentland /* This enum defines the Panel's eDP revision at DPCD 700h 1484562236bSHarry Wentland * 00h = eDP v1.1 or lower 1494562236bSHarry Wentland * 01h = eDP v1.2 1504562236bSHarry Wentland * 02h = eDP v1.3 (PSR support starts here) 1514562236bSHarry Wentland * 03h = eDP v1.4 1524562236bSHarry Wentland * If unknown revision, treat as eDP v1.1, meaning least functionality set. 1534562236bSHarry Wentland * This enum has values matched to eDP spec, thus values should not change. 1544562236bSHarry Wentland */ 1554562236bSHarry Wentland enum dpcd_edp_revision { 1564562236bSHarry Wentland DPCD_EDP_REVISION_EDP_V1_1 = 0, 1574562236bSHarry Wentland DPCD_EDP_REVISION_EDP_V1_2 = 1, 1584562236bSHarry Wentland DPCD_EDP_REVISION_EDP_V1_3 = 2, 1594562236bSHarry Wentland DPCD_EDP_REVISION_EDP_V1_4 = 3, 1604562236bSHarry Wentland DPCD_EDP_REVISION_EDP_UNKNOWN = DPCD_EDP_REVISION_EDP_V1_1, 1614562236bSHarry Wentland }; 1624562236bSHarry Wentland 1634562236bSHarry Wentland #endif /* __DAL_DPCD_DEFS_H__ */ 164