1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../inc/dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_fw_meta.h" 30 #include "os_types.h" 31 /* 32 * Note: the DMUB service is standalone. No additional headers should be 33 * added below or above this line unless they reside within the DMUB 34 * folder. 35 */ 36 37 /* Alignment for framebuffer memory. */ 38 #define DMUB_FB_ALIGNMENT (1024 * 1024) 39 40 /* Stack size. */ 41 #define DMUB_STACK_SIZE (128 * 1024) 42 43 /* Context size. */ 44 #define DMUB_CONTEXT_SIZE (512 * 1024) 45 46 /* Mailbox size */ 47 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 48 49 /* Default state size if meta is absent. */ 50 #define DMUB_FW_STATE_SIZE (1024) 51 52 /* Default tracebuffer size if meta is absent. */ 53 #define DMUB_TRACE_BUFFER_SIZE (1024) 54 55 /* Number of windows in use. */ 56 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1) 57 /* Base addresses. */ 58 59 #define DMUB_CW0_BASE (0x60000000) 60 #define DMUB_CW1_BASE (0x61000000) 61 #define DMUB_CW3_BASE (0x63000000) 62 #define DMUB_CW5_BASE (0x65000000) 63 #define DMUB_CW6_BASE (0x66000000) 64 65 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 66 { 67 return (val + factor - 1) / factor * factor; 68 } 69 70 static void dmub_flush_buffer_mem(const struct dmub_fb *fb) 71 { 72 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 73 uint8_t buf[64]; 74 uint32_t pos, end; 75 76 /** 77 * Read 64-byte chunks since we don't want to store a 78 * large temporary buffer for this purpose. 79 */ 80 end = fb->size / sizeof(buf) * sizeof(buf); 81 82 for (pos = 0; pos < end; pos += sizeof(buf)) 83 dmub_memcpy(buf, base + pos, sizeof(buf)); 84 85 /* Read anything leftover into the buffer. */ 86 if (end < fb->size) 87 dmub_memcpy(buf, base + pos, fb->size - end); 88 } 89 90 static const struct dmub_fw_meta_info * 91 dmub_get_fw_meta_info(const uint8_t *fw_bss_data, uint32_t fw_bss_data_size) 92 { 93 const union dmub_fw_meta *meta; 94 95 if (fw_bss_data == NULL) 96 return NULL; 97 98 if (fw_bss_data_size < sizeof(union dmub_fw_meta) + DMUB_FW_META_OFFSET) 99 return NULL; 100 101 meta = (const union dmub_fw_meta *)(fw_bss_data + fw_bss_data_size - 102 DMUB_FW_META_OFFSET - 103 sizeof(union dmub_fw_meta)); 104 105 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 106 return NULL; 107 108 return &meta->info; 109 } 110 111 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 112 { 113 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 114 115 switch (asic) { 116 case DMUB_ASIC_DCN20: 117 case DMUB_ASIC_DCN21: 118 dmub->regs = &dmub_srv_dcn20_regs; 119 120 funcs->reset = dmub_dcn20_reset; 121 funcs->reset_release = dmub_dcn20_reset_release; 122 funcs->backdoor_load = dmub_dcn20_backdoor_load; 123 funcs->setup_windows = dmub_dcn20_setup_windows; 124 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 125 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 126 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 127 funcs->is_supported = dmub_dcn20_is_supported; 128 funcs->is_hw_init = dmub_dcn20_is_hw_init; 129 130 if (asic == DMUB_ASIC_DCN21) { 131 dmub->regs = &dmub_srv_dcn21_regs; 132 133 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 134 funcs->is_phy_init = dmub_dcn21_is_phy_init; 135 } 136 break; 137 138 default: 139 return false; 140 } 141 142 return true; 143 } 144 145 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 146 const struct dmub_srv_create_params *params) 147 { 148 enum dmub_status status = DMUB_STATUS_OK; 149 150 dmub_memset(dmub, 0, sizeof(*dmub)); 151 152 dmub->funcs = params->funcs; 153 dmub->user_ctx = params->user_ctx; 154 dmub->asic = params->asic; 155 dmub->is_virtual = params->is_virtual; 156 157 /* Setup asic dependent hardware funcs. */ 158 if (!dmub_srv_hw_setup(dmub, params->asic)) { 159 status = DMUB_STATUS_INVALID; 160 goto cleanup; 161 } 162 163 /* Override (some) hardware funcs based on user params. */ 164 if (params->hw_funcs) { 165 if (params->hw_funcs->get_inbox1_rptr) 166 dmub->hw_funcs.get_inbox1_rptr = 167 params->hw_funcs->get_inbox1_rptr; 168 169 if (params->hw_funcs->set_inbox1_wptr) 170 dmub->hw_funcs.set_inbox1_wptr = 171 params->hw_funcs->set_inbox1_wptr; 172 173 if (params->hw_funcs->is_supported) 174 dmub->hw_funcs.is_supported = 175 params->hw_funcs->is_supported; 176 } 177 178 /* Sanity checks for required hw func pointers. */ 179 if (!dmub->hw_funcs.get_inbox1_rptr || 180 !dmub->hw_funcs.set_inbox1_wptr) { 181 status = DMUB_STATUS_INVALID; 182 goto cleanup; 183 } 184 185 cleanup: 186 if (status == DMUB_STATUS_OK) 187 dmub->sw_init = true; 188 else 189 dmub_srv_destroy(dmub); 190 191 return status; 192 } 193 194 void dmub_srv_destroy(struct dmub_srv *dmub) 195 { 196 dmub_memset(dmub, 0, sizeof(*dmub)); 197 } 198 199 enum dmub_status 200 dmub_srv_calc_region_info(struct dmub_srv *dmub, 201 const struct dmub_srv_region_params *params, 202 struct dmub_srv_region_info *out) 203 { 204 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 205 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 206 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 207 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 208 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 209 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 210 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 211 const struct dmub_fw_meta_info *fw_info; 212 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 213 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 214 215 if (!dmub->sw_init) 216 return DMUB_STATUS_INVALID; 217 218 memset(out, 0, sizeof(*out)); 219 220 out->num_regions = DMUB_NUM_WINDOWS; 221 222 inst->base = 0x0; 223 inst->top = inst->base + params->inst_const_size; 224 225 data->base = dmub_align(inst->top, 256); 226 data->top = data->base + params->bss_data_size; 227 228 /* 229 * All cache windows below should be aligned to the size 230 * of the DMCUB cache line, 64 bytes. 231 */ 232 233 stack->base = dmub_align(data->top, 256); 234 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 235 236 bios->base = dmub_align(stack->top, 256); 237 bios->top = bios->base + params->vbios_size; 238 239 mail->base = dmub_align(bios->top, 256); 240 mail->top = mail->base + DMUB_MAILBOX_SIZE; 241 242 fw_info = dmub_get_fw_meta_info(params->fw_bss_data, 243 params->bss_data_size); 244 245 if (fw_info) { 246 fw_state_size = fw_info->fw_region_size; 247 trace_buffer_size = fw_info->trace_buffer_size; 248 } 249 250 trace_buff->base = dmub_align(mail->top, 256); 251 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 252 253 fw_state->base = dmub_align(trace_buff->top, 256); 254 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 255 256 out->fb_size = dmub_align(fw_state->top, 4096); 257 258 return DMUB_STATUS_OK; 259 } 260 261 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 262 const struct dmub_srv_fb_params *params, 263 struct dmub_srv_fb_info *out) 264 { 265 uint8_t *cpu_base; 266 uint64_t gpu_base; 267 uint32_t i; 268 269 if (!dmub->sw_init) 270 return DMUB_STATUS_INVALID; 271 272 memset(out, 0, sizeof(*out)); 273 274 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 275 return DMUB_STATUS_INVALID; 276 277 cpu_base = (uint8_t *)params->cpu_addr; 278 gpu_base = params->gpu_addr; 279 280 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 281 const struct dmub_region *reg = 282 ¶ms->region_info->regions[i]; 283 284 out->fb[i].cpu_addr = cpu_base + reg->base; 285 out->fb[i].gpu_addr = gpu_base + reg->base; 286 out->fb[i].size = reg->top - reg->base; 287 } 288 289 out->num_fb = DMUB_NUM_WINDOWS; 290 291 return DMUB_STATUS_OK; 292 } 293 294 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 295 bool *is_supported) 296 { 297 *is_supported = false; 298 299 if (!dmub->sw_init) 300 return DMUB_STATUS_INVALID; 301 302 if (dmub->hw_funcs.is_supported) 303 *is_supported = dmub->hw_funcs.is_supported(dmub); 304 305 return DMUB_STATUS_OK; 306 } 307 308 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 309 { 310 *is_hw_init = false; 311 312 if (!dmub->sw_init) 313 return DMUB_STATUS_INVALID; 314 315 if (dmub->hw_funcs.is_hw_init) 316 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 317 318 return DMUB_STATUS_OK; 319 } 320 321 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 322 const struct dmub_srv_hw_params *params) 323 { 324 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 325 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 326 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 327 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 328 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 329 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 330 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 331 332 struct dmub_rb_init_params rb_params; 333 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 334 struct dmub_region inbox1; 335 336 if (!dmub->sw_init) 337 return DMUB_STATUS_INVALID; 338 339 dmub->fb_base = params->fb_base; 340 dmub->fb_offset = params->fb_offset; 341 dmub->psp_version = params->psp_version; 342 343 if (inst_fb && data_fb) { 344 cw0.offset.quad_part = inst_fb->gpu_addr; 345 cw0.region.base = DMUB_CW0_BASE; 346 cw0.region.top = cw0.region.base + inst_fb->size - 1; 347 348 cw1.offset.quad_part = stack_fb->gpu_addr; 349 cw1.region.base = DMUB_CW1_BASE; 350 cw1.region.top = cw1.region.base + stack_fb->size - 1; 351 352 /** 353 * Read back all the instruction memory so we don't hang the 354 * DMCUB when backdoor loading if the write from x86 hasn't been 355 * flushed yet. This only occurs in backdoor loading. 356 */ 357 dmub_flush_buffer_mem(inst_fb); 358 359 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) 360 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 361 } 362 363 if (dmub->hw_funcs.reset) 364 dmub->hw_funcs.reset(dmub); 365 366 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 367 fw_state_fb) { 368 cw2.offset.quad_part = data_fb->gpu_addr; 369 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 370 cw2.region.top = cw2.region.base + data_fb->size; 371 372 cw3.offset.quad_part = bios_fb->gpu_addr; 373 cw3.region.base = DMUB_CW3_BASE; 374 cw3.region.top = cw3.region.base + bios_fb->size; 375 376 cw4.offset.quad_part = mail_fb->gpu_addr; 377 cw4.region.base = cw3.region.top + 1; 378 cw4.region.top = cw4.region.base + mail_fb->size; 379 380 inbox1.base = cw4.region.base; 381 inbox1.top = cw4.region.top; 382 383 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 384 cw5.region.base = DMUB_CW5_BASE; 385 cw5.region.top = cw5.region.base + tracebuff_fb->size; 386 387 cw6.offset.quad_part = fw_state_fb->gpu_addr; 388 cw6.region.base = DMUB_CW6_BASE; 389 cw6.region.top = cw6.region.base + fw_state_fb->size; 390 391 dmub->fw_state = fw_state_fb->cpu_addr; 392 393 if (dmub->hw_funcs.setup_windows) 394 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 395 &cw5, &cw6); 396 397 if (dmub->hw_funcs.setup_mailbox) 398 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 399 } 400 401 if (mail_fb) { 402 dmub_memset(&rb_params, 0, sizeof(rb_params)); 403 rb_params.ctx = dmub; 404 rb_params.base_address = mail_fb->cpu_addr; 405 rb_params.capacity = DMUB_RB_SIZE; 406 407 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 408 } 409 410 if (dmub->hw_funcs.reset_release) 411 dmub->hw_funcs.reset_release(dmub); 412 413 dmub->hw_init = true; 414 415 return DMUB_STATUS_OK; 416 } 417 418 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 419 const struct dmub_cmd_header *cmd) 420 { 421 if (!dmub->hw_init) 422 return DMUB_STATUS_INVALID; 423 424 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 425 return DMUB_STATUS_OK; 426 427 return DMUB_STATUS_QUEUE_FULL; 428 } 429 430 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 431 { 432 if (!dmub->hw_init) 433 return DMUB_STATUS_INVALID; 434 435 /** 436 * Read back all the queued commands to ensure that they've 437 * been flushed to framebuffer memory. Otherwise DMCUB might 438 * read back stale, fully invalid or partially invalid data. 439 */ 440 dmub_rb_flush_pending(&dmub->inbox1_rb); 441 442 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 443 return DMUB_STATUS_OK; 444 } 445 446 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 447 uint32_t timeout_us) 448 { 449 uint32_t i; 450 451 if (!dmub->hw_init) 452 return DMUB_STATUS_INVALID; 453 454 if (!dmub->hw_funcs.is_auto_load_done) 455 return DMUB_STATUS_OK; 456 457 for (i = 0; i <= timeout_us; i += 100) { 458 if (dmub->hw_funcs.is_auto_load_done(dmub)) 459 return DMUB_STATUS_OK; 460 461 udelay(100); 462 } 463 464 return DMUB_STATUS_TIMEOUT; 465 } 466 467 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 468 uint32_t timeout_us) 469 { 470 uint32_t i = 0; 471 472 if (!dmub->hw_init) 473 return DMUB_STATUS_INVALID; 474 475 if (!dmub->hw_funcs.is_phy_init) 476 return DMUB_STATUS_OK; 477 478 for (i = 0; i <= timeout_us; i += 10) { 479 if (dmub->hw_funcs.is_phy_init(dmub)) 480 return DMUB_STATUS_OK; 481 482 udelay(10); 483 } 484 485 return DMUB_STATUS_TIMEOUT; 486 } 487 488 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 489 uint32_t timeout_us) 490 { 491 uint32_t i; 492 493 if (!dmub->hw_init) 494 return DMUB_STATUS_INVALID; 495 496 for (i = 0; i <= timeout_us; ++i) { 497 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 498 if (dmub_rb_empty(&dmub->inbox1_rb)) 499 return DMUB_STATUS_OK; 500 501 udelay(1); 502 } 503 504 return DMUB_STATUS_TIMEOUT; 505 } 506