1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 31 #include "dmub_dcn30.h" 32 #endif 33 #include "os_types.h" 34 /* 35 * Note: the DMUB service is standalone. No additional headers should be 36 * added below or above this line unless they reside within the DMUB 37 * folder. 38 */ 39 40 /* Alignment for framebuffer memory. */ 41 #define DMUB_FB_ALIGNMENT (1024 * 1024) 42 43 /* Stack size. */ 44 #define DMUB_STACK_SIZE (128 * 1024) 45 46 /* Context size. */ 47 #define DMUB_CONTEXT_SIZE (512 * 1024) 48 49 /* Mailbox size */ 50 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 51 52 /* Default state size if meta is absent. */ 53 #define DMUB_FW_STATE_SIZE (64 * 1024) 54 55 /* Default tracebuffer size if meta is absent. */ 56 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 57 58 /* Default scratch mem size. */ 59 #define DMUB_SCRATCH_MEM_SIZE (256) 60 61 /* Number of windows in use. */ 62 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 63 /* Base addresses. */ 64 65 #define DMUB_CW0_BASE (0x60000000) 66 #define DMUB_CW1_BASE (0x61000000) 67 #define DMUB_CW3_BASE (0x63000000) 68 #define DMUB_CW4_BASE (0x64000000) 69 #define DMUB_CW5_BASE (0x65000000) 70 #define DMUB_CW6_BASE (0x66000000) 71 72 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 73 { 74 return (val + factor - 1) / factor * factor; 75 } 76 77 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 78 { 79 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 80 uint8_t buf[64]; 81 uint32_t pos, end; 82 83 /** 84 * Read 64-byte chunks since we don't want to store a 85 * large temporary buffer for this purpose. 86 */ 87 end = fb->size / sizeof(buf) * sizeof(buf); 88 89 for (pos = 0; pos < end; pos += sizeof(buf)) 90 dmub_memcpy(buf, base + pos, sizeof(buf)); 91 92 /* Read anything leftover into the buffer. */ 93 if (end < fb->size) 94 dmub_memcpy(buf, base + pos, fb->size - end); 95 } 96 97 static const struct dmub_fw_meta_info * 98 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 99 { 100 const union dmub_fw_meta *meta; 101 const uint8_t *blob = NULL; 102 uint32_t blob_size = 0; 103 uint32_t meta_offset = 0; 104 105 if (params->fw_bss_data && params->bss_data_size) { 106 /* Legacy metadata region. */ 107 blob = params->fw_bss_data; 108 blob_size = params->bss_data_size; 109 meta_offset = DMUB_FW_META_OFFSET; 110 } else if (params->fw_inst_const && params->inst_const_size) { 111 /* Combined metadata region. */ 112 blob = params->fw_inst_const; 113 blob_size = params->inst_const_size; 114 meta_offset = 0; 115 } 116 117 if (!blob || !blob_size) 118 return NULL; 119 120 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 121 return NULL; 122 123 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 124 sizeof(union dmub_fw_meta)); 125 126 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 127 return NULL; 128 129 return &meta->info; 130 } 131 132 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 133 { 134 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 135 136 switch (asic) { 137 case DMUB_ASIC_DCN20: 138 case DMUB_ASIC_DCN21: 139 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 140 case DMUB_ASIC_DCN30: 141 #endif 142 dmub->regs = &dmub_srv_dcn20_regs; 143 144 funcs->reset = dmub_dcn20_reset; 145 funcs->reset_release = dmub_dcn20_reset_release; 146 funcs->backdoor_load = dmub_dcn20_backdoor_load; 147 funcs->setup_windows = dmub_dcn20_setup_windows; 148 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 149 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 150 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 151 funcs->is_supported = dmub_dcn20_is_supported; 152 funcs->is_hw_init = dmub_dcn20_is_hw_init; 153 funcs->set_gpint = dmub_dcn20_set_gpint; 154 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 155 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 156 157 if (asic == DMUB_ASIC_DCN21) { 158 dmub->regs = &dmub_srv_dcn21_regs; 159 160 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 161 funcs->is_phy_init = dmub_dcn21_is_phy_init; 162 } 163 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 164 if (asic == DMUB_ASIC_DCN30) { 165 dmub->regs = &dmub_srv_dcn30_regs; 166 167 funcs->is_auto_load_done = dmub_dcn30_is_auto_load_done; 168 funcs->backdoor_load = dmub_dcn30_backdoor_load; 169 funcs->setup_windows = dmub_dcn30_setup_windows; 170 } 171 #endif 172 break; 173 174 default: 175 return false; 176 } 177 178 return true; 179 } 180 181 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 182 const struct dmub_srv_create_params *params) 183 { 184 enum dmub_status status = DMUB_STATUS_OK; 185 186 dmub_memset(dmub, 0, sizeof(*dmub)); 187 188 dmub->funcs = params->funcs; 189 dmub->user_ctx = params->user_ctx; 190 dmub->asic = params->asic; 191 dmub->fw_version = params->fw_version; 192 dmub->is_virtual = params->is_virtual; 193 194 /* Setup asic dependent hardware funcs. */ 195 if (!dmub_srv_hw_setup(dmub, params->asic)) { 196 status = DMUB_STATUS_INVALID; 197 goto cleanup; 198 } 199 200 /* Override (some) hardware funcs based on user params. */ 201 if (params->hw_funcs) { 202 if (params->hw_funcs->emul_get_inbox1_rptr) 203 dmub->hw_funcs.emul_get_inbox1_rptr = 204 params->hw_funcs->emul_get_inbox1_rptr; 205 206 if (params->hw_funcs->emul_set_inbox1_wptr) 207 dmub->hw_funcs.emul_set_inbox1_wptr = 208 params->hw_funcs->emul_set_inbox1_wptr; 209 210 if (params->hw_funcs->is_supported) 211 dmub->hw_funcs.is_supported = 212 params->hw_funcs->is_supported; 213 } 214 215 /* Sanity checks for required hw func pointers. */ 216 if (!dmub->hw_funcs.get_inbox1_rptr || 217 !dmub->hw_funcs.set_inbox1_wptr) { 218 status = DMUB_STATUS_INVALID; 219 goto cleanup; 220 } 221 222 cleanup: 223 if (status == DMUB_STATUS_OK) 224 dmub->sw_init = true; 225 else 226 dmub_srv_destroy(dmub); 227 228 return status; 229 } 230 231 void dmub_srv_destroy(struct dmub_srv *dmub) 232 { 233 dmub_memset(dmub, 0, sizeof(*dmub)); 234 } 235 236 enum dmub_status 237 dmub_srv_calc_region_info(struct dmub_srv *dmub, 238 const struct dmub_srv_region_params *params, 239 struct dmub_srv_region_info *out) 240 { 241 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 242 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 243 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 244 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 245 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 246 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 247 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 248 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 249 const struct dmub_fw_meta_info *fw_info; 250 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 251 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 252 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 253 254 if (!dmub->sw_init) 255 return DMUB_STATUS_INVALID; 256 257 memset(out, 0, sizeof(*out)); 258 259 out->num_regions = DMUB_NUM_WINDOWS; 260 261 inst->base = 0x0; 262 inst->top = inst->base + params->inst_const_size; 263 264 data->base = dmub_align(inst->top, 256); 265 data->top = data->base + params->bss_data_size; 266 267 /* 268 * All cache windows below should be aligned to the size 269 * of the DMCUB cache line, 64 bytes. 270 */ 271 272 stack->base = dmub_align(data->top, 256); 273 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 274 275 bios->base = dmub_align(stack->top, 256); 276 bios->top = bios->base + params->vbios_size; 277 278 mail->base = dmub_align(bios->top, 256); 279 mail->top = mail->base + DMUB_MAILBOX_SIZE; 280 281 fw_info = dmub_get_fw_meta_info(params); 282 283 if (fw_info) { 284 fw_state_size = fw_info->fw_region_size; 285 trace_buffer_size = fw_info->trace_buffer_size; 286 287 /** 288 * If DM didn't fill in a version, then fill it in based on 289 * the firmware meta now that we have it. 290 * 291 * TODO: Make it easier for driver to extract this out to 292 * pass during creation. 293 */ 294 if (dmub->fw_version == 0) 295 dmub->fw_version = fw_info->fw_version; 296 } 297 298 trace_buff->base = dmub_align(mail->top, 256); 299 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 300 301 fw_state->base = dmub_align(trace_buff->top, 256); 302 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 303 304 scratch_mem->base = dmub_align(fw_state->top, 256); 305 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 306 307 out->fb_size = dmub_align(scratch_mem->top, 4096); 308 309 return DMUB_STATUS_OK; 310 } 311 312 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 313 const struct dmub_srv_fb_params *params, 314 struct dmub_srv_fb_info *out) 315 { 316 uint8_t *cpu_base; 317 uint64_t gpu_base; 318 uint32_t i; 319 320 if (!dmub->sw_init) 321 return DMUB_STATUS_INVALID; 322 323 memset(out, 0, sizeof(*out)); 324 325 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 326 return DMUB_STATUS_INVALID; 327 328 cpu_base = (uint8_t *)params->cpu_addr; 329 gpu_base = params->gpu_addr; 330 331 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 332 const struct dmub_region *reg = 333 ¶ms->region_info->regions[i]; 334 335 out->fb[i].cpu_addr = cpu_base + reg->base; 336 out->fb[i].gpu_addr = gpu_base + reg->base; 337 out->fb[i].size = reg->top - reg->base; 338 } 339 340 out->num_fb = DMUB_NUM_WINDOWS; 341 342 return DMUB_STATUS_OK; 343 } 344 345 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 346 bool *is_supported) 347 { 348 *is_supported = false; 349 350 if (!dmub->sw_init) 351 return DMUB_STATUS_INVALID; 352 353 if (dmub->hw_funcs.is_supported) 354 *is_supported = dmub->hw_funcs.is_supported(dmub); 355 356 return DMUB_STATUS_OK; 357 } 358 359 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 360 { 361 *is_hw_init = false; 362 363 if (!dmub->sw_init) 364 return DMUB_STATUS_INVALID; 365 366 if (!dmub->hw_init) 367 return DMUB_STATUS_OK; 368 369 if (dmub->hw_funcs.is_hw_init) 370 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 371 372 return DMUB_STATUS_OK; 373 } 374 375 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 376 const struct dmub_srv_hw_params *params) 377 { 378 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 379 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 380 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 381 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 382 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 383 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 384 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 385 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 386 387 struct dmub_rb_init_params rb_params; 388 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 389 struct dmub_region inbox1; 390 391 if (!dmub->sw_init) 392 return DMUB_STATUS_INVALID; 393 394 dmub->fb_base = params->fb_base; 395 dmub->fb_offset = params->fb_offset; 396 dmub->psp_version = params->psp_version; 397 398 if (inst_fb && data_fb) { 399 cw0.offset.quad_part = inst_fb->gpu_addr; 400 cw0.region.base = DMUB_CW0_BASE; 401 cw0.region.top = cw0.region.base + inst_fb->size - 1; 402 403 cw1.offset.quad_part = stack_fb->gpu_addr; 404 cw1.region.base = DMUB_CW1_BASE; 405 cw1.region.top = cw1.region.base + stack_fb->size - 1; 406 407 /** 408 * Read back all the instruction memory so we don't hang the 409 * DMCUB when backdoor loading if the write from x86 hasn't been 410 * flushed yet. This only occurs in backdoor loading. 411 */ 412 dmub_flush_buffer_mem(inst_fb); 413 414 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) 415 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 416 } 417 418 if (dmub->hw_funcs.reset) 419 dmub->hw_funcs.reset(dmub); 420 421 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 422 fw_state_fb && scratch_mem_fb) { 423 cw2.offset.quad_part = data_fb->gpu_addr; 424 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 425 cw2.region.top = cw2.region.base + data_fb->size; 426 427 cw3.offset.quad_part = bios_fb->gpu_addr; 428 cw3.region.base = DMUB_CW3_BASE; 429 cw3.region.top = cw3.region.base + bios_fb->size; 430 431 cw4.offset.quad_part = mail_fb->gpu_addr; 432 cw4.region.base = DMUB_CW4_BASE; 433 cw4.region.top = cw4.region.base + mail_fb->size; 434 435 inbox1.base = cw4.region.base; 436 inbox1.top = cw4.region.top; 437 438 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 439 cw5.region.base = DMUB_CW5_BASE; 440 cw5.region.top = cw5.region.base + tracebuff_fb->size; 441 442 cw6.offset.quad_part = fw_state_fb->gpu_addr; 443 cw6.region.base = DMUB_CW6_BASE; 444 cw6.region.top = cw6.region.base + fw_state_fb->size; 445 446 dmub->fw_state = fw_state_fb->cpu_addr; 447 448 dmub->scratch_mem_fb = *scratch_mem_fb; 449 450 if (dmub->hw_funcs.setup_windows) 451 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 452 &cw5, &cw6); 453 454 if (dmub->hw_funcs.setup_mailbox) 455 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 456 } 457 458 if (mail_fb) { 459 dmub_memset(&rb_params, 0, sizeof(rb_params)); 460 rb_params.ctx = dmub; 461 rb_params.base_address = mail_fb->cpu_addr; 462 rb_params.capacity = DMUB_RB_SIZE; 463 464 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 465 } 466 467 if (dmub->hw_funcs.reset_release) 468 dmub->hw_funcs.reset_release(dmub); 469 470 dmub->hw_init = true; 471 472 return DMUB_STATUS_OK; 473 } 474 475 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 476 { 477 if (!dmub->sw_init) 478 return DMUB_STATUS_INVALID; 479 480 if (dmub->hw_init == false) 481 return DMUB_STATUS_OK; 482 483 if (dmub->hw_funcs.reset) 484 dmub->hw_funcs.reset(dmub); 485 486 dmub->hw_init = false; 487 488 return DMUB_STATUS_OK; 489 } 490 491 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 492 const union dmub_rb_cmd *cmd) 493 { 494 if (!dmub->hw_init) 495 return DMUB_STATUS_INVALID; 496 497 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 498 return DMUB_STATUS_OK; 499 500 return DMUB_STATUS_QUEUE_FULL; 501 } 502 503 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 504 { 505 if (!dmub->hw_init) 506 return DMUB_STATUS_INVALID; 507 508 /** 509 * Read back all the queued commands to ensure that they've 510 * been flushed to framebuffer memory. Otherwise DMCUB might 511 * read back stale, fully invalid or partially invalid data. 512 */ 513 dmub_rb_flush_pending(&dmub->inbox1_rb); 514 515 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 516 return DMUB_STATUS_OK; 517 } 518 519 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 520 uint32_t timeout_us) 521 { 522 uint32_t i; 523 524 if (!dmub->hw_init) 525 return DMUB_STATUS_INVALID; 526 527 if (!dmub->hw_funcs.is_auto_load_done) 528 return DMUB_STATUS_OK; 529 530 for (i = 0; i <= timeout_us; i += 100) { 531 if (dmub->hw_funcs.is_auto_load_done(dmub)) 532 return DMUB_STATUS_OK; 533 534 udelay(100); 535 } 536 537 return DMUB_STATUS_TIMEOUT; 538 } 539 540 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 541 uint32_t timeout_us) 542 { 543 uint32_t i = 0; 544 545 if (!dmub->hw_init) 546 return DMUB_STATUS_INVALID; 547 548 if (!dmub->hw_funcs.is_phy_init) 549 return DMUB_STATUS_OK; 550 551 for (i = 0; i <= timeout_us; i += 10) { 552 if (dmub->hw_funcs.is_phy_init(dmub)) 553 return DMUB_STATUS_OK; 554 555 udelay(10); 556 } 557 558 return DMUB_STATUS_TIMEOUT; 559 } 560 561 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 562 uint32_t timeout_us) 563 { 564 uint32_t i; 565 566 if (!dmub->hw_init) 567 return DMUB_STATUS_INVALID; 568 569 for (i = 0; i <= timeout_us; ++i) { 570 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 571 if (dmub_rb_empty(&dmub->inbox1_rb)) 572 return DMUB_STATUS_OK; 573 574 udelay(1); 575 } 576 577 return DMUB_STATUS_TIMEOUT; 578 } 579 580 enum dmub_status 581 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 582 enum dmub_gpint_command command_code, 583 uint16_t param, uint32_t timeout_us) 584 { 585 union dmub_gpint_data_register reg; 586 uint32_t i; 587 588 if (!dmub->sw_init) 589 return DMUB_STATUS_INVALID; 590 591 if (!dmub->hw_funcs.set_gpint) 592 return DMUB_STATUS_INVALID; 593 594 if (!dmub->hw_funcs.is_gpint_acked) 595 return DMUB_STATUS_INVALID; 596 597 reg.bits.status = 1; 598 reg.bits.command_code = command_code; 599 reg.bits.param = param; 600 601 dmub->hw_funcs.set_gpint(dmub, reg); 602 603 for (i = 0; i < timeout_us; ++i) { 604 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 605 return DMUB_STATUS_OK; 606 } 607 608 return DMUB_STATUS_TIMEOUT; 609 } 610 611 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 612 uint32_t *response) 613 { 614 *response = 0; 615 616 if (!dmub->sw_init) 617 return DMUB_STATUS_INVALID; 618 619 if (!dmub->hw_funcs.get_gpint_response) 620 return DMUB_STATUS_INVALID; 621 622 *response = dmub->hw_funcs.get_gpint_response(dmub); 623 624 return DMUB_STATUS_OK; 625 } 626