1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "os_types.h" 40 /* 41 * Note: the DMUB service is standalone. No additional headers should be 42 * added below or above this line unless they reside within the DMUB 43 * folder. 44 */ 45 46 /* Alignment for framebuffer memory. */ 47 #define DMUB_FB_ALIGNMENT (1024 * 1024) 48 49 /* Stack size. */ 50 #define DMUB_STACK_SIZE (128 * 1024) 51 52 /* Context size. */ 53 #define DMUB_CONTEXT_SIZE (512 * 1024) 54 55 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 57 58 /* Default state size if meta is absent. */ 59 #define DMUB_FW_STATE_SIZE (64 * 1024) 60 61 /* Default tracebuffer size if meta is absent. */ 62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 63 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (256) 67 68 /* Number of windows in use. */ 69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 70 /* Base addresses. */ 71 72 #define DMUB_CW0_BASE (0x60000000) 73 #define DMUB_CW1_BASE (0x61000000) 74 #define DMUB_CW3_BASE (0x63000000) 75 #define DMUB_CW4_BASE (0x64000000) 76 #define DMUB_CW5_BASE (0x65000000) 77 #define DMUB_CW6_BASE (0x66000000) 78 79 #define DMUB_REGION5_BASE (0xA0000000) 80 81 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 82 { 83 return (val + factor - 1) / factor * factor; 84 } 85 86 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 87 { 88 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 89 uint8_t buf[64]; 90 uint32_t pos, end; 91 92 /** 93 * Read 64-byte chunks since we don't want to store a 94 * large temporary buffer for this purpose. 95 */ 96 end = fb->size / sizeof(buf) * sizeof(buf); 97 98 for (pos = 0; pos < end; pos += sizeof(buf)) 99 dmub_memcpy(buf, base + pos, sizeof(buf)); 100 101 /* Read anything leftover into the buffer. */ 102 if (end < fb->size) 103 dmub_memcpy(buf, base + pos, fb->size - end); 104 } 105 106 static const struct dmub_fw_meta_info * 107 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 108 { 109 const union dmub_fw_meta *meta; 110 111 if (!blob || !blob_size) 112 return NULL; 113 114 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 115 return NULL; 116 117 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 118 sizeof(union dmub_fw_meta)); 119 120 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 121 return NULL; 122 123 return &meta->info; 124 } 125 126 static const struct dmub_fw_meta_info * 127 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 128 { 129 const struct dmub_fw_meta_info *info = NULL; 130 131 if (params->fw_bss_data && params->bss_data_size) { 132 /* Legacy metadata region. */ 133 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 134 params->bss_data_size, 135 DMUB_FW_META_OFFSET); 136 } else if (params->fw_inst_const && params->inst_const_size) { 137 /* Combined metadata region - can be aligned to 16-bytes. */ 138 uint32_t i; 139 140 for (i = 0; i < 16; ++i) { 141 info = dmub_get_fw_meta_info_from_blob( 142 params->fw_inst_const, params->inst_const_size, i); 143 144 if (info) 145 break; 146 } 147 } 148 149 return info; 150 } 151 152 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 153 { 154 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 155 156 switch (asic) { 157 case DMUB_ASIC_DCN20: 158 case DMUB_ASIC_DCN21: 159 case DMUB_ASIC_DCN30: 160 case DMUB_ASIC_DCN301: 161 case DMUB_ASIC_DCN302: 162 case DMUB_ASIC_DCN303: 163 dmub->regs = &dmub_srv_dcn20_regs; 164 165 funcs->reset = dmub_dcn20_reset; 166 funcs->reset_release = dmub_dcn20_reset_release; 167 funcs->backdoor_load = dmub_dcn20_backdoor_load; 168 funcs->setup_windows = dmub_dcn20_setup_windows; 169 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 170 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 171 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 172 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 173 funcs->is_supported = dmub_dcn20_is_supported; 174 funcs->is_hw_init = dmub_dcn20_is_hw_init; 175 funcs->set_gpint = dmub_dcn20_set_gpint; 176 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 177 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 178 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 179 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 180 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 181 funcs->get_current_time = dmub_dcn20_get_current_time; 182 183 // Out mailbox register access functions for RN and above 184 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 185 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 186 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 187 188 //outbox0 call stacks 189 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 190 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 191 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 192 193 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 194 195 if (asic == DMUB_ASIC_DCN21) 196 dmub->regs = &dmub_srv_dcn21_regs; 197 198 if (asic == DMUB_ASIC_DCN30) { 199 dmub->regs = &dmub_srv_dcn30_regs; 200 201 funcs->backdoor_load = dmub_dcn30_backdoor_load; 202 funcs->setup_windows = dmub_dcn30_setup_windows; 203 } 204 if (asic == DMUB_ASIC_DCN301) { 205 dmub->regs = &dmub_srv_dcn301_regs; 206 207 funcs->backdoor_load = dmub_dcn30_backdoor_load; 208 funcs->setup_windows = dmub_dcn30_setup_windows; 209 } 210 if (asic == DMUB_ASIC_DCN302) { 211 dmub->regs = &dmub_srv_dcn302_regs; 212 213 funcs->backdoor_load = dmub_dcn30_backdoor_load; 214 funcs->setup_windows = dmub_dcn30_setup_windows; 215 } 216 if (asic == DMUB_ASIC_DCN303) { 217 dmub->regs = &dmub_srv_dcn303_regs; 218 219 funcs->backdoor_load = dmub_dcn30_backdoor_load; 220 funcs->setup_windows = dmub_dcn30_setup_windows; 221 } 222 break; 223 224 case DMUB_ASIC_DCN31: 225 case DMUB_ASIC_DCN31B: 226 case DMUB_ASIC_DCN314: 227 case DMUB_ASIC_DCN315: 228 case DMUB_ASIC_DCN316: 229 if (asic == DMUB_ASIC_DCN314) 230 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 231 else if (asic == DMUB_ASIC_DCN315) 232 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 233 else if (asic == DMUB_ASIC_DCN316) 234 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 235 else 236 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 237 funcs->reset = dmub_dcn31_reset; 238 funcs->reset_release = dmub_dcn31_reset_release; 239 funcs->backdoor_load = dmub_dcn31_backdoor_load; 240 funcs->setup_windows = dmub_dcn31_setup_windows; 241 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 242 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 243 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 244 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 245 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 246 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 247 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 248 funcs->is_supported = dmub_dcn31_is_supported; 249 funcs->is_hw_init = dmub_dcn31_is_hw_init; 250 funcs->set_gpint = dmub_dcn31_set_gpint; 251 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 252 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 253 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 254 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 255 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 256 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 257 //outbox0 call stacks 258 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 259 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 260 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 261 262 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 263 funcs->should_detect = dmub_dcn31_should_detect; 264 funcs->get_current_time = dmub_dcn31_get_current_time; 265 266 break; 267 268 case DMUB_ASIC_DCN32: 269 case DMUB_ASIC_DCN321: 270 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 271 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 272 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 273 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 274 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 275 funcs->reset = dmub_dcn32_reset; 276 funcs->reset_release = dmub_dcn32_reset_release; 277 funcs->backdoor_load = dmub_dcn32_backdoor_load; 278 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 279 funcs->setup_windows = dmub_dcn32_setup_windows; 280 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 281 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 282 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 283 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 284 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 285 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 286 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 287 funcs->is_supported = dmub_dcn32_is_supported; 288 funcs->is_hw_init = dmub_dcn32_is_hw_init; 289 funcs->set_gpint = dmub_dcn32_set_gpint; 290 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 291 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 292 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 293 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 294 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 295 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 296 297 /* outbox0 call stacks */ 298 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 299 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 300 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 301 funcs->get_current_time = dmub_dcn32_get_current_time; 302 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 303 304 break; 305 306 default: 307 return false; 308 } 309 310 return true; 311 } 312 313 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 314 const struct dmub_srv_create_params *params) 315 { 316 enum dmub_status status = DMUB_STATUS_OK; 317 318 dmub_memset(dmub, 0, sizeof(*dmub)); 319 320 dmub->funcs = params->funcs; 321 dmub->user_ctx = params->user_ctx; 322 dmub->asic = params->asic; 323 dmub->fw_version = params->fw_version; 324 dmub->is_virtual = params->is_virtual; 325 326 /* Setup asic dependent hardware funcs. */ 327 if (!dmub_srv_hw_setup(dmub, params->asic)) { 328 status = DMUB_STATUS_INVALID; 329 goto cleanup; 330 } 331 332 /* Override (some) hardware funcs based on user params. */ 333 if (params->hw_funcs) { 334 if (params->hw_funcs->emul_get_inbox1_rptr) 335 dmub->hw_funcs.emul_get_inbox1_rptr = 336 params->hw_funcs->emul_get_inbox1_rptr; 337 338 if (params->hw_funcs->emul_set_inbox1_wptr) 339 dmub->hw_funcs.emul_set_inbox1_wptr = 340 params->hw_funcs->emul_set_inbox1_wptr; 341 342 if (params->hw_funcs->is_supported) 343 dmub->hw_funcs.is_supported = 344 params->hw_funcs->is_supported; 345 } 346 347 /* Sanity checks for required hw func pointers. */ 348 if (!dmub->hw_funcs.get_inbox1_rptr || 349 !dmub->hw_funcs.set_inbox1_wptr) { 350 status = DMUB_STATUS_INVALID; 351 goto cleanup; 352 } 353 354 cleanup: 355 if (status == DMUB_STATUS_OK) 356 dmub->sw_init = true; 357 else 358 dmub_srv_destroy(dmub); 359 360 return status; 361 } 362 363 void dmub_srv_destroy(struct dmub_srv *dmub) 364 { 365 dmub_memset(dmub, 0, sizeof(*dmub)); 366 } 367 368 enum dmub_status 369 dmub_srv_calc_region_info(struct dmub_srv *dmub, 370 const struct dmub_srv_region_params *params, 371 struct dmub_srv_region_info *out) 372 { 373 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 374 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 375 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 376 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 377 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 378 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 379 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 380 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 381 const struct dmub_fw_meta_info *fw_info; 382 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 383 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 384 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 385 386 if (!dmub->sw_init) 387 return DMUB_STATUS_INVALID; 388 389 memset(out, 0, sizeof(*out)); 390 391 out->num_regions = DMUB_NUM_WINDOWS; 392 393 inst->base = 0x0; 394 inst->top = inst->base + params->inst_const_size; 395 396 data->base = dmub_align(inst->top, 256); 397 data->top = data->base + params->bss_data_size; 398 399 /* 400 * All cache windows below should be aligned to the size 401 * of the DMCUB cache line, 64 bytes. 402 */ 403 404 stack->base = dmub_align(data->top, 256); 405 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 406 407 bios->base = dmub_align(stack->top, 256); 408 bios->top = bios->base + params->vbios_size; 409 410 mail->base = dmub_align(bios->top, 256); 411 mail->top = mail->base + DMUB_MAILBOX_SIZE; 412 413 fw_info = dmub_get_fw_meta_info(params); 414 415 if (fw_info) { 416 fw_state_size = fw_info->fw_region_size; 417 trace_buffer_size = fw_info->trace_buffer_size; 418 419 /** 420 * If DM didn't fill in a version, then fill it in based on 421 * the firmware meta now that we have it. 422 * 423 * TODO: Make it easier for driver to extract this out to 424 * pass during creation. 425 */ 426 if (dmub->fw_version == 0) 427 dmub->fw_version = fw_info->fw_version; 428 } 429 430 trace_buff->base = dmub_align(mail->top, 256); 431 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 432 433 fw_state->base = dmub_align(trace_buff->top, 256); 434 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 435 436 scratch_mem->base = dmub_align(fw_state->top, 256); 437 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 438 439 out->fb_size = dmub_align(scratch_mem->top, 4096); 440 441 return DMUB_STATUS_OK; 442 } 443 444 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 445 const struct dmub_srv_fb_params *params, 446 struct dmub_srv_fb_info *out) 447 { 448 uint8_t *cpu_base; 449 uint64_t gpu_base; 450 uint32_t i; 451 452 if (!dmub->sw_init) 453 return DMUB_STATUS_INVALID; 454 455 memset(out, 0, sizeof(*out)); 456 457 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 458 return DMUB_STATUS_INVALID; 459 460 cpu_base = (uint8_t *)params->cpu_addr; 461 gpu_base = params->gpu_addr; 462 463 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 464 const struct dmub_region *reg = 465 ¶ms->region_info->regions[i]; 466 467 out->fb[i].cpu_addr = cpu_base + reg->base; 468 out->fb[i].gpu_addr = gpu_base + reg->base; 469 out->fb[i].size = reg->top - reg->base; 470 } 471 472 out->num_fb = DMUB_NUM_WINDOWS; 473 474 return DMUB_STATUS_OK; 475 } 476 477 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 478 bool *is_supported) 479 { 480 *is_supported = false; 481 482 if (!dmub->sw_init) 483 return DMUB_STATUS_INVALID; 484 485 if (dmub->hw_funcs.is_supported) 486 *is_supported = dmub->hw_funcs.is_supported(dmub); 487 488 return DMUB_STATUS_OK; 489 } 490 491 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 492 { 493 *is_hw_init = false; 494 495 if (!dmub->sw_init) 496 return DMUB_STATUS_INVALID; 497 498 if (!dmub->hw_init) 499 return DMUB_STATUS_OK; 500 501 if (dmub->hw_funcs.is_hw_init) 502 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 503 504 return DMUB_STATUS_OK; 505 } 506 507 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 508 const struct dmub_srv_hw_params *params) 509 { 510 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 511 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 512 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 513 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 514 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 515 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 516 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 517 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 518 519 struct dmub_rb_init_params rb_params, outbox0_rb_params; 520 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 521 struct dmub_region inbox1, outbox1, outbox0; 522 523 if (!dmub->sw_init) 524 return DMUB_STATUS_INVALID; 525 526 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 527 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 528 ASSERT(0); 529 return DMUB_STATUS_INVALID; 530 } 531 532 dmub->fb_base = params->fb_base; 533 dmub->fb_offset = params->fb_offset; 534 dmub->psp_version = params->psp_version; 535 536 if (dmub->hw_funcs.reset) 537 dmub->hw_funcs.reset(dmub); 538 539 /* reset the cache of the last wptr as well now that hw is reset */ 540 dmub->inbox1_last_wptr = 0; 541 542 cw0.offset.quad_part = inst_fb->gpu_addr; 543 cw0.region.base = DMUB_CW0_BASE; 544 cw0.region.top = cw0.region.base + inst_fb->size - 1; 545 546 cw1.offset.quad_part = stack_fb->gpu_addr; 547 cw1.region.base = DMUB_CW1_BASE; 548 cw1.region.top = cw1.region.base + stack_fb->size - 1; 549 550 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 551 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 552 553 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 554 /** 555 * Read back all the instruction memory so we don't hang the 556 * DMCUB when backdoor loading if the write from x86 hasn't been 557 * flushed yet. This only occurs in backdoor loading. 558 */ 559 dmub_flush_buffer_mem(inst_fb); 560 561 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 562 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 563 else 564 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 565 } 566 567 cw2.offset.quad_part = data_fb->gpu_addr; 568 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 569 cw2.region.top = cw2.region.base + data_fb->size; 570 571 cw3.offset.quad_part = bios_fb->gpu_addr; 572 cw3.region.base = DMUB_CW3_BASE; 573 cw3.region.top = cw3.region.base + bios_fb->size; 574 575 cw4.offset.quad_part = mail_fb->gpu_addr; 576 cw4.region.base = DMUB_CW4_BASE; 577 cw4.region.top = cw4.region.base + mail_fb->size; 578 579 /** 580 * Doubled the mailbox region to accomodate inbox and outbox. 581 * Note: Currently, currently total mailbox size is 16KB. It is split 582 * equally into 8KB between inbox and outbox. If this config is 583 * changed, then uncached base address configuration of outbox1 584 * has to be updated in funcs->setup_out_mailbox. 585 */ 586 inbox1.base = cw4.region.base; 587 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 588 outbox1.base = inbox1.top; 589 outbox1.top = cw4.region.top; 590 591 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 592 cw5.region.base = DMUB_CW5_BASE; 593 cw5.region.top = cw5.region.base + tracebuff_fb->size; 594 595 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 596 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 597 598 cw6.offset.quad_part = fw_state_fb->gpu_addr; 599 cw6.region.base = DMUB_CW6_BASE; 600 cw6.region.top = cw6.region.base + fw_state_fb->size; 601 602 dmub->fw_state = fw_state_fb->cpu_addr; 603 604 dmub->scratch_mem_fb = *scratch_mem_fb; 605 606 if (dmub->hw_funcs.setup_windows) 607 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 608 609 if (dmub->hw_funcs.setup_outbox0) 610 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 611 612 if (dmub->hw_funcs.setup_mailbox) 613 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 614 if (dmub->hw_funcs.setup_out_mailbox) 615 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 616 617 dmub_memset(&rb_params, 0, sizeof(rb_params)); 618 rb_params.ctx = dmub; 619 rb_params.base_address = mail_fb->cpu_addr; 620 rb_params.capacity = DMUB_RB_SIZE; 621 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 622 623 // Initialize outbox1 ring buffer 624 rb_params.ctx = dmub; 625 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 626 rb_params.capacity = DMUB_RB_SIZE; 627 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 628 629 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 630 outbox0_rb_params.ctx = dmub; 631 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 632 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 633 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 634 635 /* Report to DMUB what features are supported by current driver */ 636 if (dmub->hw_funcs.enable_dmub_boot_options) 637 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 638 639 if (dmub->hw_funcs.skip_dmub_panel_power_sequence) 640 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 641 params->skip_panel_power_sequence); 642 643 if (dmub->hw_funcs.reset_release) 644 dmub->hw_funcs.reset_release(dmub); 645 646 dmub->hw_init = true; 647 648 return DMUB_STATUS_OK; 649 } 650 651 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 652 { 653 if (!dmub->sw_init) 654 return DMUB_STATUS_INVALID; 655 656 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 657 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 658 dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 659 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 660 } 661 662 return DMUB_STATUS_OK; 663 } 664 665 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 666 { 667 if (!dmub->sw_init) 668 return DMUB_STATUS_INVALID; 669 670 if (dmub->hw_funcs.reset) 671 dmub->hw_funcs.reset(dmub); 672 673 /* mailboxes have been reset in hw, so reset the sw state as well */ 674 dmub->inbox1_last_wptr = 0; 675 dmub->inbox1_rb.wrpt = 0; 676 dmub->inbox1_rb.rptr = 0; 677 dmub->outbox0_rb.wrpt = 0; 678 dmub->outbox0_rb.rptr = 0; 679 dmub->outbox1_rb.wrpt = 0; 680 dmub->outbox1_rb.rptr = 0; 681 682 dmub->hw_init = false; 683 684 return DMUB_STATUS_OK; 685 } 686 687 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 688 const union dmub_rb_cmd *cmd) 689 { 690 if (!dmub->hw_init) 691 return DMUB_STATUS_INVALID; 692 693 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 694 return DMUB_STATUS_OK; 695 696 return DMUB_STATUS_QUEUE_FULL; 697 } 698 699 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 700 { 701 struct dmub_rb flush_rb; 702 703 if (!dmub->hw_init) 704 return DMUB_STATUS_INVALID; 705 706 /** 707 * Read back all the queued commands to ensure that they've 708 * been flushed to framebuffer memory. Otherwise DMCUB might 709 * read back stale, fully invalid or partially invalid data. 710 */ 711 flush_rb = dmub->inbox1_rb; 712 flush_rb.rptr = dmub->inbox1_last_wptr; 713 dmub_rb_flush_pending(&flush_rb); 714 715 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 716 717 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 718 719 return DMUB_STATUS_OK; 720 } 721 722 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 723 uint32_t timeout_us) 724 { 725 uint32_t i; 726 727 if (!dmub->hw_init) 728 return DMUB_STATUS_INVALID; 729 730 for (i = 0; i <= timeout_us; i += 100) { 731 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 732 733 if (status.bits.dal_fw && status.bits.mailbox_rdy) 734 return DMUB_STATUS_OK; 735 736 udelay(100); 737 } 738 739 return DMUB_STATUS_TIMEOUT; 740 } 741 742 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 743 uint32_t timeout_us) 744 { 745 uint32_t i, rptr; 746 747 if (!dmub->hw_init) 748 return DMUB_STATUS_INVALID; 749 750 for (i = 0; i <= timeout_us; ++i) { 751 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 752 753 if (rptr > dmub->inbox1_rb.capacity) 754 return DMUB_STATUS_HW_FAILURE; 755 756 dmub->inbox1_rb.rptr = rptr; 757 758 if (dmub_rb_empty(&dmub->inbox1_rb)) 759 return DMUB_STATUS_OK; 760 761 udelay(1); 762 } 763 764 return DMUB_STATUS_TIMEOUT; 765 } 766 767 enum dmub_status 768 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 769 enum dmub_gpint_command command_code, 770 uint16_t param, uint32_t timeout_us) 771 { 772 union dmub_gpint_data_register reg; 773 uint32_t i; 774 775 if (!dmub->sw_init) 776 return DMUB_STATUS_INVALID; 777 778 if (!dmub->hw_funcs.set_gpint) 779 return DMUB_STATUS_INVALID; 780 781 if (!dmub->hw_funcs.is_gpint_acked) 782 return DMUB_STATUS_INVALID; 783 784 reg.bits.status = 1; 785 reg.bits.command_code = command_code; 786 reg.bits.param = param; 787 788 dmub->hw_funcs.set_gpint(dmub, reg); 789 790 for (i = 0; i < timeout_us; ++i) { 791 udelay(1); 792 793 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 794 return DMUB_STATUS_OK; 795 } 796 797 return DMUB_STATUS_TIMEOUT; 798 } 799 800 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 801 uint32_t *response) 802 { 803 *response = 0; 804 805 if (!dmub->sw_init) 806 return DMUB_STATUS_INVALID; 807 808 if (!dmub->hw_funcs.get_gpint_response) 809 return DMUB_STATUS_INVALID; 810 811 *response = dmub->hw_funcs.get_gpint_response(dmub); 812 813 return DMUB_STATUS_OK; 814 } 815 816 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 817 uint32_t *dataout) 818 { 819 *dataout = 0; 820 821 if (!dmub->sw_init) 822 return DMUB_STATUS_INVALID; 823 824 if (!dmub->hw_funcs.get_gpint_dataout) 825 return DMUB_STATUS_INVALID; 826 827 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 828 829 return DMUB_STATUS_OK; 830 } 831 832 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 833 union dmub_fw_boot_status *status) 834 { 835 status->all = 0; 836 837 if (!dmub->sw_init) 838 return DMUB_STATUS_INVALID; 839 840 if (dmub->hw_funcs.get_fw_status) 841 *status = dmub->hw_funcs.get_fw_status(dmub); 842 843 return DMUB_STATUS_OK; 844 } 845 846 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 847 union dmub_rb_cmd *cmd) 848 { 849 enum dmub_status status = DMUB_STATUS_OK; 850 851 // Queue command 852 status = dmub_srv_cmd_queue(dmub, cmd); 853 854 if (status != DMUB_STATUS_OK) 855 return status; 856 857 // Execute command 858 status = dmub_srv_cmd_execute(dmub); 859 860 if (status != DMUB_STATUS_OK) 861 return status; 862 863 // Wait for DMUB to process command 864 status = dmub_srv_wait_for_idle(dmub, 100000); 865 866 if (status != DMUB_STATUS_OK) 867 return status; 868 869 // Copy data back from ring buffer into command 870 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 871 872 return status; 873 } 874 875 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 876 void *entry) 877 { 878 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 879 uint64_t *dst = (uint64_t *)entry; 880 uint8_t i; 881 uint8_t loop_count; 882 883 if (rb->rptr == rb->wrpt) 884 return false; 885 886 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 887 // copying data 888 for (i = 0; i < loop_count; i++) 889 *dst++ = *src++; 890 891 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 892 893 rb->rptr %= rb->capacity; 894 895 return true; 896 } 897 898 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 899 { 900 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 901 902 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 903 } 904 905 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 906 { 907 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 908 return false; 909 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 910 return true; 911 } 912 913 bool dmub_srv_should_detect(struct dmub_srv *dmub) 914 { 915 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 916 return false; 917 918 return dmub->hw_funcs.should_detect(dmub); 919 } 920 921 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 922 { 923 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 924 return DMUB_STATUS_INVALID; 925 926 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 927 return DMUB_STATUS_OK; 928 } 929 930 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 931 { 932 uint32_t i = 0; 933 uint32_t ack = 0; 934 935 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 936 return DMUB_STATUS_INVALID; 937 938 for (i = 0; i <= timeout_us; i++) { 939 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 940 if (ack) 941 return DMUB_STATUS_OK; 942 } 943 return DMUB_STATUS_TIMEOUT; 944 } 945 946 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 947 union dmub_inbox0_data_register data) 948 { 949 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 950 return DMUB_STATUS_INVALID; 951 952 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 953 return DMUB_STATUS_OK; 954 } 955