1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "os_types.h" 36 /* 37 * Note: the DMUB service is standalone. No additional headers should be 38 * added below or above this line unless they reside within the DMUB 39 * folder. 40 */ 41 42 /* Alignment for framebuffer memory. */ 43 #define DMUB_FB_ALIGNMENT (1024 * 1024) 44 45 /* Stack size. */ 46 #define DMUB_STACK_SIZE (128 * 1024) 47 48 /* Context size. */ 49 #define DMUB_CONTEXT_SIZE (512 * 1024) 50 51 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 52 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 53 54 /* Default state size if meta is absent. */ 55 #define DMUB_FW_STATE_SIZE (64 * 1024) 56 57 /* Default tracebuffer size if meta is absent. */ 58 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 59 60 61 /* Default scratch mem size. */ 62 #define DMUB_SCRATCH_MEM_SIZE (256) 63 64 /* Number of windows in use. */ 65 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 66 /* Base addresses. */ 67 68 #define DMUB_CW0_BASE (0x60000000) 69 #define DMUB_CW1_BASE (0x61000000) 70 #define DMUB_CW3_BASE (0x63000000) 71 #define DMUB_CW4_BASE (0x64000000) 72 #define DMUB_CW5_BASE (0x65000000) 73 #define DMUB_CW6_BASE (0x66000000) 74 75 #define DMUB_REGION5_BASE (0xA0000000) 76 77 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 78 { 79 return (val + factor - 1) / factor * factor; 80 } 81 82 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 83 { 84 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 85 uint8_t buf[64]; 86 uint32_t pos, end; 87 88 /** 89 * Read 64-byte chunks since we don't want to store a 90 * large temporary buffer for this purpose. 91 */ 92 end = fb->size / sizeof(buf) * sizeof(buf); 93 94 for (pos = 0; pos < end; pos += sizeof(buf)) 95 dmub_memcpy(buf, base + pos, sizeof(buf)); 96 97 /* Read anything leftover into the buffer. */ 98 if (end < fb->size) 99 dmub_memcpy(buf, base + pos, fb->size - end); 100 } 101 102 static const struct dmub_fw_meta_info * 103 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 104 { 105 const union dmub_fw_meta *meta; 106 107 if (!blob || !blob_size) 108 return NULL; 109 110 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 111 return NULL; 112 113 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 114 sizeof(union dmub_fw_meta)); 115 116 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 117 return NULL; 118 119 return &meta->info; 120 } 121 122 static const struct dmub_fw_meta_info * 123 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 124 { 125 const struct dmub_fw_meta_info *info = NULL; 126 127 if (params->fw_bss_data && params->bss_data_size) { 128 /* Legacy metadata region. */ 129 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 130 params->bss_data_size, 131 DMUB_FW_META_OFFSET); 132 } else if (params->fw_inst_const && params->inst_const_size) { 133 /* Combined metadata region - can be aligned to 16-bytes. */ 134 uint32_t i; 135 136 for (i = 0; i < 16; ++i) { 137 info = dmub_get_fw_meta_info_from_blob( 138 params->fw_inst_const, params->inst_const_size, i); 139 140 if (info) 141 break; 142 } 143 } 144 145 return info; 146 } 147 148 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 149 { 150 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 151 152 switch (asic) { 153 case DMUB_ASIC_DCN20: 154 case DMUB_ASIC_DCN21: 155 case DMUB_ASIC_DCN30: 156 case DMUB_ASIC_DCN301: 157 case DMUB_ASIC_DCN302: 158 case DMUB_ASIC_DCN303: 159 dmub->regs = &dmub_srv_dcn20_regs; 160 161 funcs->reset = dmub_dcn20_reset; 162 funcs->reset_release = dmub_dcn20_reset_release; 163 funcs->backdoor_load = dmub_dcn20_backdoor_load; 164 funcs->setup_windows = dmub_dcn20_setup_windows; 165 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 166 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 167 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 168 funcs->is_supported = dmub_dcn20_is_supported; 169 funcs->is_hw_init = dmub_dcn20_is_hw_init; 170 funcs->set_gpint = dmub_dcn20_set_gpint; 171 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 172 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 173 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 174 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 175 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 176 funcs->get_current_time = dmub_dcn20_get_current_time; 177 178 // Out mailbox register access functions for RN and above 179 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 180 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 181 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 182 183 //outbox0 call stacks 184 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 185 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 186 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 187 188 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 189 190 if (asic == DMUB_ASIC_DCN21) { 191 dmub->regs = &dmub_srv_dcn21_regs; 192 193 funcs->is_phy_init = dmub_dcn21_is_phy_init; 194 } 195 if (asic == DMUB_ASIC_DCN30) { 196 dmub->regs = &dmub_srv_dcn30_regs; 197 198 funcs->backdoor_load = dmub_dcn30_backdoor_load; 199 funcs->setup_windows = dmub_dcn30_setup_windows; 200 } 201 if (asic == DMUB_ASIC_DCN301) { 202 dmub->regs = &dmub_srv_dcn301_regs; 203 204 funcs->backdoor_load = dmub_dcn30_backdoor_load; 205 funcs->setup_windows = dmub_dcn30_setup_windows; 206 } 207 if (asic == DMUB_ASIC_DCN302) { 208 dmub->regs = &dmub_srv_dcn302_regs; 209 210 funcs->backdoor_load = dmub_dcn30_backdoor_load; 211 funcs->setup_windows = dmub_dcn30_setup_windows; 212 } 213 if (asic == DMUB_ASIC_DCN303) { 214 dmub->regs = &dmub_srv_dcn303_regs; 215 216 funcs->backdoor_load = dmub_dcn30_backdoor_load; 217 funcs->setup_windows = dmub_dcn30_setup_windows; 218 } 219 break; 220 221 case DMUB_ASIC_DCN31: 222 case DMUB_ASIC_DCN31B: 223 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 224 funcs->reset = dmub_dcn31_reset; 225 funcs->reset_release = dmub_dcn31_reset_release; 226 funcs->backdoor_load = dmub_dcn31_backdoor_load; 227 funcs->setup_windows = dmub_dcn31_setup_windows; 228 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 229 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 230 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 231 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 232 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 233 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 234 funcs->is_supported = dmub_dcn31_is_supported; 235 funcs->is_hw_init = dmub_dcn31_is_hw_init; 236 funcs->set_gpint = dmub_dcn31_set_gpint; 237 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 238 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 239 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 240 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 241 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 242 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 243 //outbox0 call stacks 244 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 245 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 246 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 247 248 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 249 funcs->should_detect = dmub_dcn31_should_detect; 250 funcs->get_current_time = dmub_dcn31_get_current_time; 251 252 break; 253 254 default: 255 return false; 256 } 257 258 return true; 259 } 260 261 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 262 const struct dmub_srv_create_params *params) 263 { 264 enum dmub_status status = DMUB_STATUS_OK; 265 266 dmub_memset(dmub, 0, sizeof(*dmub)); 267 268 dmub->funcs = params->funcs; 269 dmub->user_ctx = params->user_ctx; 270 dmub->asic = params->asic; 271 dmub->fw_version = params->fw_version; 272 dmub->is_virtual = params->is_virtual; 273 274 /* Setup asic dependent hardware funcs. */ 275 if (!dmub_srv_hw_setup(dmub, params->asic)) { 276 status = DMUB_STATUS_INVALID; 277 goto cleanup; 278 } 279 280 /* Override (some) hardware funcs based on user params. */ 281 if (params->hw_funcs) { 282 if (params->hw_funcs->emul_get_inbox1_rptr) 283 dmub->hw_funcs.emul_get_inbox1_rptr = 284 params->hw_funcs->emul_get_inbox1_rptr; 285 286 if (params->hw_funcs->emul_set_inbox1_wptr) 287 dmub->hw_funcs.emul_set_inbox1_wptr = 288 params->hw_funcs->emul_set_inbox1_wptr; 289 290 if (params->hw_funcs->is_supported) 291 dmub->hw_funcs.is_supported = 292 params->hw_funcs->is_supported; 293 } 294 295 /* Sanity checks for required hw func pointers. */ 296 if (!dmub->hw_funcs.get_inbox1_rptr || 297 !dmub->hw_funcs.set_inbox1_wptr) { 298 status = DMUB_STATUS_INVALID; 299 goto cleanup; 300 } 301 302 cleanup: 303 if (status == DMUB_STATUS_OK) 304 dmub->sw_init = true; 305 else 306 dmub_srv_destroy(dmub); 307 308 return status; 309 } 310 311 void dmub_srv_destroy(struct dmub_srv *dmub) 312 { 313 dmub_memset(dmub, 0, sizeof(*dmub)); 314 } 315 316 enum dmub_status 317 dmub_srv_calc_region_info(struct dmub_srv *dmub, 318 const struct dmub_srv_region_params *params, 319 struct dmub_srv_region_info *out) 320 { 321 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 322 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 323 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 324 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 325 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 326 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 327 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 328 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 329 const struct dmub_fw_meta_info *fw_info; 330 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 331 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 332 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 333 334 if (!dmub->sw_init) 335 return DMUB_STATUS_INVALID; 336 337 memset(out, 0, sizeof(*out)); 338 339 out->num_regions = DMUB_NUM_WINDOWS; 340 341 inst->base = 0x0; 342 inst->top = inst->base + params->inst_const_size; 343 344 data->base = dmub_align(inst->top, 256); 345 data->top = data->base + params->bss_data_size; 346 347 /* 348 * All cache windows below should be aligned to the size 349 * of the DMCUB cache line, 64 bytes. 350 */ 351 352 stack->base = dmub_align(data->top, 256); 353 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 354 355 bios->base = dmub_align(stack->top, 256); 356 bios->top = bios->base + params->vbios_size; 357 358 mail->base = dmub_align(bios->top, 256); 359 mail->top = mail->base + DMUB_MAILBOX_SIZE; 360 361 fw_info = dmub_get_fw_meta_info(params); 362 363 if (fw_info) { 364 fw_state_size = fw_info->fw_region_size; 365 trace_buffer_size = fw_info->trace_buffer_size; 366 367 /** 368 * If DM didn't fill in a version, then fill it in based on 369 * the firmware meta now that we have it. 370 * 371 * TODO: Make it easier for driver to extract this out to 372 * pass during creation. 373 */ 374 if (dmub->fw_version == 0) 375 dmub->fw_version = fw_info->fw_version; 376 } 377 378 trace_buff->base = dmub_align(mail->top, 256); 379 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 380 381 fw_state->base = dmub_align(trace_buff->top, 256); 382 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 383 384 scratch_mem->base = dmub_align(fw_state->top, 256); 385 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 386 387 out->fb_size = dmub_align(scratch_mem->top, 4096); 388 389 return DMUB_STATUS_OK; 390 } 391 392 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 393 const struct dmub_srv_fb_params *params, 394 struct dmub_srv_fb_info *out) 395 { 396 uint8_t *cpu_base; 397 uint64_t gpu_base; 398 uint32_t i; 399 400 if (!dmub->sw_init) 401 return DMUB_STATUS_INVALID; 402 403 memset(out, 0, sizeof(*out)); 404 405 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 406 return DMUB_STATUS_INVALID; 407 408 cpu_base = (uint8_t *)params->cpu_addr; 409 gpu_base = params->gpu_addr; 410 411 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 412 const struct dmub_region *reg = 413 ¶ms->region_info->regions[i]; 414 415 out->fb[i].cpu_addr = cpu_base + reg->base; 416 out->fb[i].gpu_addr = gpu_base + reg->base; 417 out->fb[i].size = reg->top - reg->base; 418 } 419 420 out->num_fb = DMUB_NUM_WINDOWS; 421 422 return DMUB_STATUS_OK; 423 } 424 425 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 426 bool *is_supported) 427 { 428 *is_supported = false; 429 430 if (!dmub->sw_init) 431 return DMUB_STATUS_INVALID; 432 433 if (dmub->hw_funcs.is_supported) 434 *is_supported = dmub->hw_funcs.is_supported(dmub); 435 436 return DMUB_STATUS_OK; 437 } 438 439 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 440 { 441 *is_hw_init = false; 442 443 if (!dmub->sw_init) 444 return DMUB_STATUS_INVALID; 445 446 if (!dmub->hw_init) 447 return DMUB_STATUS_OK; 448 449 if (dmub->hw_funcs.is_hw_init) 450 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 451 452 return DMUB_STATUS_OK; 453 } 454 455 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 456 const struct dmub_srv_hw_params *params) 457 { 458 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 459 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 460 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 461 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 462 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 463 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 464 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 465 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 466 467 struct dmub_rb_init_params rb_params, outbox0_rb_params; 468 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 469 struct dmub_region inbox1, outbox1, outbox0; 470 471 if (!dmub->sw_init) 472 return DMUB_STATUS_INVALID; 473 474 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 475 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 476 ASSERT(0); 477 return DMUB_STATUS_INVALID; 478 } 479 480 dmub->fb_base = params->fb_base; 481 dmub->fb_offset = params->fb_offset; 482 dmub->psp_version = params->psp_version; 483 484 if (dmub->hw_funcs.reset) 485 dmub->hw_funcs.reset(dmub); 486 487 cw0.offset.quad_part = inst_fb->gpu_addr; 488 cw0.region.base = DMUB_CW0_BASE; 489 cw0.region.top = cw0.region.base + inst_fb->size - 1; 490 491 cw1.offset.quad_part = stack_fb->gpu_addr; 492 cw1.region.base = DMUB_CW1_BASE; 493 cw1.region.top = cw1.region.base + stack_fb->size - 1; 494 495 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 496 /** 497 * Read back all the instruction memory so we don't hang the 498 * DMCUB when backdoor loading if the write from x86 hasn't been 499 * flushed yet. This only occurs in backdoor loading. 500 */ 501 dmub_flush_buffer_mem(inst_fb); 502 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 503 } 504 505 cw2.offset.quad_part = data_fb->gpu_addr; 506 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 507 cw2.region.top = cw2.region.base + data_fb->size; 508 509 cw3.offset.quad_part = bios_fb->gpu_addr; 510 cw3.region.base = DMUB_CW3_BASE; 511 cw3.region.top = cw3.region.base + bios_fb->size; 512 513 cw4.offset.quad_part = mail_fb->gpu_addr; 514 cw4.region.base = DMUB_CW4_BASE; 515 cw4.region.top = cw4.region.base + mail_fb->size; 516 517 /** 518 * Doubled the mailbox region to accomodate inbox and outbox. 519 * Note: Currently, currently total mailbox size is 16KB. It is split 520 * equally into 8KB between inbox and outbox. If this config is 521 * changed, then uncached base address configuration of outbox1 522 * has to be updated in funcs->setup_out_mailbox. 523 */ 524 inbox1.base = cw4.region.base; 525 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 526 outbox1.base = inbox1.top; 527 outbox1.top = cw4.region.top; 528 529 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 530 cw5.region.base = DMUB_CW5_BASE; 531 cw5.region.top = cw5.region.base + tracebuff_fb->size; 532 533 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 534 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 535 536 cw6.offset.quad_part = fw_state_fb->gpu_addr; 537 cw6.region.base = DMUB_CW6_BASE; 538 cw6.region.top = cw6.region.base + fw_state_fb->size; 539 540 dmub->fw_state = fw_state_fb->cpu_addr; 541 542 dmub->scratch_mem_fb = *scratch_mem_fb; 543 544 if (dmub->hw_funcs.setup_windows) 545 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 546 547 if (dmub->hw_funcs.setup_outbox0) 548 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 549 550 if (dmub->hw_funcs.setup_mailbox) 551 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 552 if (dmub->hw_funcs.setup_out_mailbox) 553 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 554 555 dmub_memset(&rb_params, 0, sizeof(rb_params)); 556 rb_params.ctx = dmub; 557 rb_params.base_address = mail_fb->cpu_addr; 558 rb_params.capacity = DMUB_RB_SIZE; 559 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 560 561 // Initialize outbox1 ring buffer 562 rb_params.ctx = dmub; 563 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 564 rb_params.capacity = DMUB_RB_SIZE; 565 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 566 567 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 568 outbox0_rb_params.ctx = dmub; 569 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 570 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 571 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 572 573 /* Report to DMUB what features are supported by current driver */ 574 if (dmub->hw_funcs.enable_dmub_boot_options) 575 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 576 577 if (dmub->hw_funcs.reset_release) 578 dmub->hw_funcs.reset_release(dmub); 579 580 dmub->hw_init = true; 581 582 return DMUB_STATUS_OK; 583 } 584 585 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 586 { 587 if (!dmub->sw_init) 588 return DMUB_STATUS_INVALID; 589 590 if (dmub->hw_funcs.reset) 591 dmub->hw_funcs.reset(dmub); 592 593 dmub->hw_init = false; 594 595 return DMUB_STATUS_OK; 596 } 597 598 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 599 const union dmub_rb_cmd *cmd) 600 { 601 if (!dmub->hw_init) 602 return DMUB_STATUS_INVALID; 603 604 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 605 return DMUB_STATUS_OK; 606 607 return DMUB_STATUS_QUEUE_FULL; 608 } 609 610 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 611 { 612 struct dmub_rb flush_rb; 613 614 if (!dmub->hw_init) 615 return DMUB_STATUS_INVALID; 616 617 /** 618 * Read back all the queued commands to ensure that they've 619 * been flushed to framebuffer memory. Otherwise DMCUB might 620 * read back stale, fully invalid or partially invalid data. 621 */ 622 flush_rb = dmub->inbox1_rb; 623 flush_rb.rptr = dmub->inbox1_last_wptr; 624 dmub_rb_flush_pending(&flush_rb); 625 626 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 627 628 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 629 630 return DMUB_STATUS_OK; 631 } 632 633 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 634 uint32_t timeout_us) 635 { 636 uint32_t i; 637 638 if (!dmub->hw_init) 639 return DMUB_STATUS_INVALID; 640 641 for (i = 0; i <= timeout_us; i += 100) { 642 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 643 644 if (status.bits.dal_fw && status.bits.mailbox_rdy) 645 return DMUB_STATUS_OK; 646 647 udelay(100); 648 } 649 650 return DMUB_STATUS_TIMEOUT; 651 } 652 653 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 654 uint32_t timeout_us) 655 { 656 uint32_t i = 0; 657 658 if (!dmub->hw_init) 659 return DMUB_STATUS_INVALID; 660 661 if (!dmub->hw_funcs.is_phy_init) 662 return DMUB_STATUS_OK; 663 664 for (i = 0; i <= timeout_us; i += 10) { 665 if (dmub->hw_funcs.is_phy_init(dmub)) 666 return DMUB_STATUS_OK; 667 668 udelay(10); 669 } 670 671 return DMUB_STATUS_TIMEOUT; 672 } 673 674 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 675 uint32_t timeout_us) 676 { 677 uint32_t i, rptr; 678 679 if (!dmub->hw_init) 680 return DMUB_STATUS_INVALID; 681 682 for (i = 0; i <= timeout_us; ++i) { 683 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 684 685 if (rptr > dmub->inbox1_rb.capacity) 686 return DMUB_STATUS_HW_FAILURE; 687 688 dmub->inbox1_rb.rptr = rptr; 689 690 if (dmub_rb_empty(&dmub->inbox1_rb)) 691 return DMUB_STATUS_OK; 692 693 udelay(1); 694 } 695 696 return DMUB_STATUS_TIMEOUT; 697 } 698 699 enum dmub_status 700 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 701 enum dmub_gpint_command command_code, 702 uint16_t param, uint32_t timeout_us) 703 { 704 union dmub_gpint_data_register reg; 705 uint32_t i; 706 707 if (!dmub->sw_init) 708 return DMUB_STATUS_INVALID; 709 710 if (!dmub->hw_funcs.set_gpint) 711 return DMUB_STATUS_INVALID; 712 713 if (!dmub->hw_funcs.is_gpint_acked) 714 return DMUB_STATUS_INVALID; 715 716 reg.bits.status = 1; 717 reg.bits.command_code = command_code; 718 reg.bits.param = param; 719 720 dmub->hw_funcs.set_gpint(dmub, reg); 721 722 for (i = 0; i < timeout_us; ++i) { 723 udelay(1); 724 725 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 726 return DMUB_STATUS_OK; 727 } 728 729 return DMUB_STATUS_TIMEOUT; 730 } 731 732 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 733 uint32_t *response) 734 { 735 *response = 0; 736 737 if (!dmub->sw_init) 738 return DMUB_STATUS_INVALID; 739 740 if (!dmub->hw_funcs.get_gpint_response) 741 return DMUB_STATUS_INVALID; 742 743 *response = dmub->hw_funcs.get_gpint_response(dmub); 744 745 return DMUB_STATUS_OK; 746 } 747 748 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 749 uint32_t *dataout) 750 { 751 *dataout = 0; 752 753 if (!dmub->sw_init) 754 return DMUB_STATUS_INVALID; 755 756 if (!dmub->hw_funcs.get_gpint_dataout) 757 return DMUB_STATUS_INVALID; 758 759 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 760 761 return DMUB_STATUS_OK; 762 } 763 764 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 765 union dmub_fw_boot_status *status) 766 { 767 status->all = 0; 768 769 if (!dmub->sw_init) 770 return DMUB_STATUS_INVALID; 771 772 if (dmub->hw_funcs.get_fw_status) 773 *status = dmub->hw_funcs.get_fw_status(dmub); 774 775 return DMUB_STATUS_OK; 776 } 777 778 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 779 union dmub_rb_cmd *cmd) 780 { 781 enum dmub_status status = DMUB_STATUS_OK; 782 783 // Queue command 784 status = dmub_srv_cmd_queue(dmub, cmd); 785 786 if (status != DMUB_STATUS_OK) 787 return status; 788 789 // Execute command 790 status = dmub_srv_cmd_execute(dmub); 791 792 if (status != DMUB_STATUS_OK) 793 return status; 794 795 // Wait for DMUB to process command 796 status = dmub_srv_wait_for_idle(dmub, 100000); 797 798 if (status != DMUB_STATUS_OK) 799 return status; 800 801 // Copy data back from ring buffer into command 802 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 803 804 return status; 805 } 806 807 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 808 void *entry) 809 { 810 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 811 uint64_t *dst = (uint64_t *)entry; 812 uint8_t i; 813 uint8_t loop_count; 814 815 if (rb->rptr == rb->wrpt) 816 return false; 817 818 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 819 // copying data 820 for (i = 0; i < loop_count; i++) 821 *dst++ = *src++; 822 823 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 824 825 rb->rptr %= rb->capacity; 826 827 return true; 828 } 829 830 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 831 { 832 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 833 834 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 835 } 836 837 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 838 { 839 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 840 return false; 841 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 842 return true; 843 } 844 845 bool dmub_srv_should_detect(struct dmub_srv *dmub) 846 { 847 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 848 return false; 849 850 return dmub->hw_funcs.should_detect(dmub); 851 } 852 853 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 854 { 855 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 856 return DMUB_STATUS_INVALID; 857 858 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 859 return DMUB_STATUS_OK; 860 } 861 862 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 863 { 864 uint32_t i = 0; 865 uint32_t ack = 0; 866 867 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 868 return DMUB_STATUS_INVALID; 869 870 for (i = 0; i <= timeout_us; i++) { 871 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 872 if (ack) 873 return DMUB_STATUS_OK; 874 } 875 return DMUB_STATUS_TIMEOUT; 876 } 877 878 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 879 union dmub_inbox0_data_register data) 880 { 881 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 882 return DMUB_STATUS_INVALID; 883 884 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 885 return DMUB_STATUS_OK; 886 } 887