1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "os_types.h" 34 #include "dmub_trace_buffer.h" 35 /* 36 * Note: the DMUB service is standalone. No additional headers should be 37 * added below or above this line unless they reside within the DMUB 38 * folder. 39 */ 40 41 /* Alignment for framebuffer memory. */ 42 #define DMUB_FB_ALIGNMENT (1024 * 1024) 43 44 /* Stack size. */ 45 #define DMUB_STACK_SIZE (128 * 1024) 46 47 /* Context size. */ 48 #define DMUB_CONTEXT_SIZE (512 * 1024) 49 50 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 51 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 52 53 /* Default state size if meta is absent. */ 54 #define DMUB_FW_STATE_SIZE (64 * 1024) 55 56 /* Default tracebuffer size if meta is absent. */ 57 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 58 59 60 /* Default scratch mem size. */ 61 #define DMUB_SCRATCH_MEM_SIZE (256) 62 63 /* Number of windows in use. */ 64 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 65 /* Base addresses. */ 66 67 #define DMUB_CW0_BASE (0x60000000) 68 #define DMUB_CW1_BASE (0x61000000) 69 #define DMUB_CW3_BASE (0x63000000) 70 #define DMUB_CW4_BASE (0x64000000) 71 #define DMUB_CW5_BASE (0x65000000) 72 #define DMUB_CW6_BASE (0x66000000) 73 74 #define DMUB_REGION5_BASE (0xA0000000) 75 76 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 77 { 78 return (val + factor - 1) / factor * factor; 79 } 80 81 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 82 { 83 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 84 uint8_t buf[64]; 85 uint32_t pos, end; 86 87 /** 88 * Read 64-byte chunks since we don't want to store a 89 * large temporary buffer for this purpose. 90 */ 91 end = fb->size / sizeof(buf) * sizeof(buf); 92 93 for (pos = 0; pos < end; pos += sizeof(buf)) 94 dmub_memcpy(buf, base + pos, sizeof(buf)); 95 96 /* Read anything leftover into the buffer. */ 97 if (end < fb->size) 98 dmub_memcpy(buf, base + pos, fb->size - end); 99 } 100 101 static const struct dmub_fw_meta_info * 102 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 103 { 104 const union dmub_fw_meta *meta; 105 const uint8_t *blob = NULL; 106 uint32_t blob_size = 0; 107 uint32_t meta_offset = 0; 108 109 if (params->fw_bss_data && params->bss_data_size) { 110 /* Legacy metadata region. */ 111 blob = params->fw_bss_data; 112 blob_size = params->bss_data_size; 113 meta_offset = DMUB_FW_META_OFFSET; 114 } else if (params->fw_inst_const && params->inst_const_size) { 115 /* Combined metadata region. */ 116 blob = params->fw_inst_const; 117 blob_size = params->inst_const_size; 118 meta_offset = 0; 119 } 120 121 if (!blob || !blob_size) 122 return NULL; 123 124 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 125 return NULL; 126 127 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 128 sizeof(union dmub_fw_meta)); 129 130 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 131 return NULL; 132 133 return &meta->info; 134 } 135 136 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 137 { 138 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 139 140 switch (asic) { 141 case DMUB_ASIC_DCN20: 142 case DMUB_ASIC_DCN21: 143 case DMUB_ASIC_DCN30: 144 case DMUB_ASIC_DCN301: 145 case DMUB_ASIC_DCN302: 146 dmub->regs = &dmub_srv_dcn20_regs; 147 148 funcs->reset = dmub_dcn20_reset; 149 funcs->reset_release = dmub_dcn20_reset_release; 150 funcs->backdoor_load = dmub_dcn20_backdoor_load; 151 funcs->setup_windows = dmub_dcn20_setup_windows; 152 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 153 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 154 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 155 funcs->is_supported = dmub_dcn20_is_supported; 156 funcs->is_hw_init = dmub_dcn20_is_hw_init; 157 funcs->set_gpint = dmub_dcn20_set_gpint; 158 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 159 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 160 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 161 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 162 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 163 164 // Out mailbox register access functions for RN and above 165 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 166 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 167 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 168 169 //outbox0 call stacks 170 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 171 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 172 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 173 174 if (asic == DMUB_ASIC_DCN21) { 175 dmub->regs = &dmub_srv_dcn21_regs; 176 177 funcs->is_phy_init = dmub_dcn21_is_phy_init; 178 } 179 if (asic == DMUB_ASIC_DCN30) { 180 dmub->regs = &dmub_srv_dcn30_regs; 181 182 funcs->backdoor_load = dmub_dcn30_backdoor_load; 183 funcs->setup_windows = dmub_dcn30_setup_windows; 184 } 185 if (asic == DMUB_ASIC_DCN301) { 186 dmub->regs = &dmub_srv_dcn301_regs; 187 188 funcs->backdoor_load = dmub_dcn30_backdoor_load; 189 funcs->setup_windows = dmub_dcn30_setup_windows; 190 } 191 if (asic == DMUB_ASIC_DCN302) { 192 dmub->regs = &dmub_srv_dcn302_regs; 193 194 funcs->backdoor_load = dmub_dcn30_backdoor_load; 195 funcs->setup_windows = dmub_dcn30_setup_windows; 196 } 197 break; 198 199 default: 200 return false; 201 } 202 203 return true; 204 } 205 206 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 207 const struct dmub_srv_create_params *params) 208 { 209 enum dmub_status status = DMUB_STATUS_OK; 210 211 dmub_memset(dmub, 0, sizeof(*dmub)); 212 213 dmub->funcs = params->funcs; 214 dmub->user_ctx = params->user_ctx; 215 dmub->asic = params->asic; 216 dmub->fw_version = params->fw_version; 217 dmub->is_virtual = params->is_virtual; 218 219 /* Setup asic dependent hardware funcs. */ 220 if (!dmub_srv_hw_setup(dmub, params->asic)) { 221 status = DMUB_STATUS_INVALID; 222 goto cleanup; 223 } 224 225 /* Override (some) hardware funcs based on user params. */ 226 if (params->hw_funcs) { 227 if (params->hw_funcs->emul_get_inbox1_rptr) 228 dmub->hw_funcs.emul_get_inbox1_rptr = 229 params->hw_funcs->emul_get_inbox1_rptr; 230 231 if (params->hw_funcs->emul_set_inbox1_wptr) 232 dmub->hw_funcs.emul_set_inbox1_wptr = 233 params->hw_funcs->emul_set_inbox1_wptr; 234 235 if (params->hw_funcs->is_supported) 236 dmub->hw_funcs.is_supported = 237 params->hw_funcs->is_supported; 238 } 239 240 /* Sanity checks for required hw func pointers. */ 241 if (!dmub->hw_funcs.get_inbox1_rptr || 242 !dmub->hw_funcs.set_inbox1_wptr) { 243 status = DMUB_STATUS_INVALID; 244 goto cleanup; 245 } 246 247 cleanup: 248 if (status == DMUB_STATUS_OK) 249 dmub->sw_init = true; 250 else 251 dmub_srv_destroy(dmub); 252 253 return status; 254 } 255 256 void dmub_srv_destroy(struct dmub_srv *dmub) 257 { 258 dmub_memset(dmub, 0, sizeof(*dmub)); 259 } 260 261 enum dmub_status 262 dmub_srv_calc_region_info(struct dmub_srv *dmub, 263 const struct dmub_srv_region_params *params, 264 struct dmub_srv_region_info *out) 265 { 266 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 267 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 268 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 269 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 270 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 271 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 272 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 273 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 274 const struct dmub_fw_meta_info *fw_info; 275 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 276 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 277 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 278 279 if (!dmub->sw_init) 280 return DMUB_STATUS_INVALID; 281 282 memset(out, 0, sizeof(*out)); 283 284 out->num_regions = DMUB_NUM_WINDOWS; 285 286 inst->base = 0x0; 287 inst->top = inst->base + params->inst_const_size; 288 289 data->base = dmub_align(inst->top, 256); 290 data->top = data->base + params->bss_data_size; 291 292 /* 293 * All cache windows below should be aligned to the size 294 * of the DMCUB cache line, 64 bytes. 295 */ 296 297 stack->base = dmub_align(data->top, 256); 298 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 299 300 bios->base = dmub_align(stack->top, 256); 301 bios->top = bios->base + params->vbios_size; 302 303 mail->base = dmub_align(bios->top, 256); 304 mail->top = mail->base + DMUB_MAILBOX_SIZE; 305 306 fw_info = dmub_get_fw_meta_info(params); 307 308 if (fw_info) { 309 fw_state_size = fw_info->fw_region_size; 310 trace_buffer_size = fw_info->trace_buffer_size; 311 312 /** 313 * If DM didn't fill in a version, then fill it in based on 314 * the firmware meta now that we have it. 315 * 316 * TODO: Make it easier for driver to extract this out to 317 * pass during creation. 318 */ 319 if (dmub->fw_version == 0) 320 dmub->fw_version = fw_info->fw_version; 321 } 322 323 trace_buff->base = dmub_align(mail->top, 256); 324 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 325 326 fw_state->base = dmub_align(trace_buff->top, 256); 327 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 328 329 scratch_mem->base = dmub_align(fw_state->top, 256); 330 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 331 332 out->fb_size = dmub_align(scratch_mem->top, 4096); 333 334 return DMUB_STATUS_OK; 335 } 336 337 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 338 const struct dmub_srv_fb_params *params, 339 struct dmub_srv_fb_info *out) 340 { 341 uint8_t *cpu_base; 342 uint64_t gpu_base; 343 uint32_t i; 344 345 if (!dmub->sw_init) 346 return DMUB_STATUS_INVALID; 347 348 memset(out, 0, sizeof(*out)); 349 350 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 351 return DMUB_STATUS_INVALID; 352 353 cpu_base = (uint8_t *)params->cpu_addr; 354 gpu_base = params->gpu_addr; 355 356 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 357 const struct dmub_region *reg = 358 ¶ms->region_info->regions[i]; 359 360 out->fb[i].cpu_addr = cpu_base + reg->base; 361 out->fb[i].gpu_addr = gpu_base + reg->base; 362 out->fb[i].size = reg->top - reg->base; 363 } 364 365 out->num_fb = DMUB_NUM_WINDOWS; 366 367 return DMUB_STATUS_OK; 368 } 369 370 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 371 bool *is_supported) 372 { 373 *is_supported = false; 374 375 if (!dmub->sw_init) 376 return DMUB_STATUS_INVALID; 377 378 if (dmub->hw_funcs.is_supported) 379 *is_supported = dmub->hw_funcs.is_supported(dmub); 380 381 return DMUB_STATUS_OK; 382 } 383 384 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 385 { 386 *is_hw_init = false; 387 388 if (!dmub->sw_init) 389 return DMUB_STATUS_INVALID; 390 391 if (!dmub->hw_init) 392 return DMUB_STATUS_OK; 393 394 if (dmub->hw_funcs.is_hw_init) 395 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 396 397 return DMUB_STATUS_OK; 398 } 399 400 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 401 const struct dmub_srv_hw_params *params) 402 { 403 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 404 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 405 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 406 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 407 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 408 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 409 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 410 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 411 412 struct dmub_rb_init_params rb_params, outbox0_rb_params; 413 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 414 struct dmub_region inbox1, outbox1, outbox0; 415 416 if (!dmub->sw_init) 417 return DMUB_STATUS_INVALID; 418 419 dmub->fb_base = params->fb_base; 420 dmub->fb_offset = params->fb_offset; 421 dmub->psp_version = params->psp_version; 422 423 if (dmub->hw_funcs.reset) 424 dmub->hw_funcs.reset(dmub); 425 426 if (inst_fb && data_fb) { 427 cw0.offset.quad_part = inst_fb->gpu_addr; 428 cw0.region.base = DMUB_CW0_BASE; 429 cw0.region.top = cw0.region.base + inst_fb->size - 1; 430 431 cw1.offset.quad_part = stack_fb->gpu_addr; 432 cw1.region.base = DMUB_CW1_BASE; 433 cw1.region.top = cw1.region.base + stack_fb->size - 1; 434 435 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 436 /** 437 * Read back all the instruction memory so we don't hang the 438 * DMCUB when backdoor loading if the write from x86 hasn't been 439 * flushed yet. This only occurs in backdoor loading. 440 */ 441 dmub_flush_buffer_mem(inst_fb); 442 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 443 } 444 445 } 446 447 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 448 fw_state_fb && scratch_mem_fb) { 449 cw2.offset.quad_part = data_fb->gpu_addr; 450 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 451 cw2.region.top = cw2.region.base + data_fb->size; 452 453 cw3.offset.quad_part = bios_fb->gpu_addr; 454 cw3.region.base = DMUB_CW3_BASE; 455 cw3.region.top = cw3.region.base + bios_fb->size; 456 457 cw4.offset.quad_part = mail_fb->gpu_addr; 458 cw4.region.base = DMUB_CW4_BASE; 459 cw4.region.top = cw4.region.base + mail_fb->size; 460 461 /** 462 * Doubled the mailbox region to accomodate inbox and outbox. 463 * Note: Currently, currently total mailbox size is 16KB. It is split 464 * equally into 8KB between inbox and outbox. If this config is 465 * changed, then uncached base address configuration of outbox1 466 * has to be updated in funcs->setup_out_mailbox. 467 */ 468 inbox1.base = cw4.region.base; 469 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 470 outbox1.base = inbox1.top; 471 outbox1.top = cw4.region.top; 472 473 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 474 cw5.region.base = DMUB_CW5_BASE; 475 cw5.region.top = cw5.region.base + tracebuff_fb->size; 476 477 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 478 outbox0.top = outbox0.base + sizeof(struct dmcub_trace_buf_entry) * PERF_TRACE_MAX_ENTRY; 479 480 481 cw6.offset.quad_part = fw_state_fb->gpu_addr; 482 cw6.region.base = DMUB_CW6_BASE; 483 cw6.region.top = cw6.region.base + fw_state_fb->size; 484 485 dmub->fw_state = fw_state_fb->cpu_addr; 486 487 dmub->scratch_mem_fb = *scratch_mem_fb; 488 489 if (dmub->hw_funcs.setup_windows) 490 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 491 &cw5, &cw6); 492 493 if (dmub->hw_funcs.setup_outbox0) 494 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 495 496 if (dmub->hw_funcs.setup_mailbox) 497 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 498 if (dmub->hw_funcs.setup_out_mailbox) 499 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 500 } 501 502 if (mail_fb) { 503 dmub_memset(&rb_params, 0, sizeof(rb_params)); 504 rb_params.ctx = dmub; 505 rb_params.base_address = mail_fb->cpu_addr; 506 rb_params.capacity = DMUB_RB_SIZE; 507 508 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 509 510 // Initialize outbox1 ring buffer 511 rb_params.ctx = dmub; 512 rb_params.base_address = (void *) ((uint64_t) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 513 rb_params.capacity = DMUB_RB_SIZE; 514 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 515 516 } 517 518 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 519 outbox0_rb_params.ctx = dmub; 520 outbox0_rb_params.base_address = (void *)((uint64_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 521 outbox0_rb_params.capacity = sizeof(struct dmcub_trace_buf_entry) * PERF_TRACE_MAX_ENTRY; 522 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 523 524 if (dmub->hw_funcs.reset_release) 525 dmub->hw_funcs.reset_release(dmub); 526 527 dmub->hw_init = true; 528 529 return DMUB_STATUS_OK; 530 } 531 532 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 533 { 534 if (!dmub->sw_init) 535 return DMUB_STATUS_INVALID; 536 537 if (dmub->hw_funcs.reset) 538 dmub->hw_funcs.reset(dmub); 539 540 dmub->hw_init = false; 541 542 return DMUB_STATUS_OK; 543 } 544 545 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 546 const union dmub_rb_cmd *cmd) 547 { 548 if (!dmub->hw_init) 549 return DMUB_STATUS_INVALID; 550 551 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 552 return DMUB_STATUS_OK; 553 554 return DMUB_STATUS_QUEUE_FULL; 555 } 556 557 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 558 { 559 if (!dmub->hw_init) 560 return DMUB_STATUS_INVALID; 561 562 /** 563 * Read back all the queued commands to ensure that they've 564 * been flushed to framebuffer memory. Otherwise DMCUB might 565 * read back stale, fully invalid or partially invalid data. 566 */ 567 dmub_rb_flush_pending(&dmub->inbox1_rb); 568 569 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 570 return DMUB_STATUS_OK; 571 } 572 573 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 574 uint32_t timeout_us) 575 { 576 uint32_t i; 577 578 if (!dmub->hw_init) 579 return DMUB_STATUS_INVALID; 580 581 for (i = 0; i <= timeout_us; i += 100) { 582 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 583 584 if (status.bits.dal_fw && status.bits.mailbox_rdy) 585 return DMUB_STATUS_OK; 586 587 udelay(100); 588 } 589 590 return DMUB_STATUS_TIMEOUT; 591 } 592 593 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 594 uint32_t timeout_us) 595 { 596 uint32_t i = 0; 597 598 if (!dmub->hw_init) 599 return DMUB_STATUS_INVALID; 600 601 if (!dmub->hw_funcs.is_phy_init) 602 return DMUB_STATUS_OK; 603 604 for (i = 0; i <= timeout_us; i += 10) { 605 if (dmub->hw_funcs.is_phy_init(dmub)) 606 return DMUB_STATUS_OK; 607 608 udelay(10); 609 } 610 611 return DMUB_STATUS_TIMEOUT; 612 } 613 614 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 615 uint32_t timeout_us) 616 { 617 uint32_t i; 618 619 if (!dmub->hw_init) 620 return DMUB_STATUS_INVALID; 621 622 for (i = 0; i <= timeout_us; ++i) { 623 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 624 if (dmub_rb_empty(&dmub->inbox1_rb)) 625 return DMUB_STATUS_OK; 626 627 udelay(1); 628 } 629 630 return DMUB_STATUS_TIMEOUT; 631 } 632 633 enum dmub_status 634 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 635 enum dmub_gpint_command command_code, 636 uint16_t param, uint32_t timeout_us) 637 { 638 union dmub_gpint_data_register reg; 639 uint32_t i; 640 641 if (!dmub->sw_init) 642 return DMUB_STATUS_INVALID; 643 644 if (!dmub->hw_funcs.set_gpint) 645 return DMUB_STATUS_INVALID; 646 647 if (!dmub->hw_funcs.is_gpint_acked) 648 return DMUB_STATUS_INVALID; 649 650 reg.bits.status = 1; 651 reg.bits.command_code = command_code; 652 reg.bits.param = param; 653 654 dmub->hw_funcs.set_gpint(dmub, reg); 655 656 for (i = 0; i < timeout_us; ++i) { 657 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 658 return DMUB_STATUS_OK; 659 } 660 661 return DMUB_STATUS_TIMEOUT; 662 } 663 664 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 665 uint32_t *response) 666 { 667 *response = 0; 668 669 if (!dmub->sw_init) 670 return DMUB_STATUS_INVALID; 671 672 if (!dmub->hw_funcs.get_gpint_response) 673 return DMUB_STATUS_INVALID; 674 675 *response = dmub->hw_funcs.get_gpint_response(dmub); 676 677 return DMUB_STATUS_OK; 678 } 679 680 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 681 union dmub_fw_boot_status *status) 682 { 683 status->all = 0; 684 685 if (!dmub->sw_init) 686 return DMUB_STATUS_INVALID; 687 688 if (dmub->hw_funcs.get_fw_status) 689 *status = dmub->hw_funcs.get_fw_status(dmub); 690 691 return DMUB_STATUS_OK; 692 } 693 694 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 695 union dmub_rb_cmd *cmd) 696 { 697 enum dmub_status status = DMUB_STATUS_OK; 698 699 // Queue command 700 status = dmub_srv_cmd_queue(dmub, cmd); 701 702 if (status != DMUB_STATUS_OK) 703 return status; 704 705 // Execute command 706 status = dmub_srv_cmd_execute(dmub); 707 708 if (status != DMUB_STATUS_OK) 709 return status; 710 711 // Wait for DMUB to process command 712 status = dmub_srv_wait_for_idle(dmub, 100000); 713 714 if (status != DMUB_STATUS_OK) 715 return status; 716 717 // Copy data back from ring buffer into command 718 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 719 720 return status; 721 } 722 723 static inline void dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 724 void *entry) 725 { 726 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 727 uint64_t *dst = (uint64_t *)entry; 728 uint8_t i; 729 730 // copying data 731 for (i = 0; i < sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); i++) 732 *dst++ = *src++; 733 734 } 735 736 enum dmub_status dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 737 { 738 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 739 740 dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 741 742 return DMUB_STATUS_OK; 743 } 744