1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 35 #include "dmub_dcn31.h" 36 #endif 37 #include "os_types.h" 38 /* 39 * Note: the DMUB service is standalone. No additional headers should be 40 * added below or above this line unless they reside within the DMUB 41 * folder. 42 */ 43 44 /* Alignment for framebuffer memory. */ 45 #define DMUB_FB_ALIGNMENT (1024 * 1024) 46 47 /* Stack size. */ 48 #define DMUB_STACK_SIZE (128 * 1024) 49 50 /* Context size. */ 51 #define DMUB_CONTEXT_SIZE (512 * 1024) 52 53 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 54 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 55 56 /* Default state size if meta is absent. */ 57 #define DMUB_FW_STATE_SIZE (64 * 1024) 58 59 /* Default tracebuffer size if meta is absent. */ 60 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 61 62 63 /* Default scratch mem size. */ 64 #define DMUB_SCRATCH_MEM_SIZE (256) 65 66 /* Number of windows in use. */ 67 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 68 /* Base addresses. */ 69 70 #define DMUB_CW0_BASE (0x60000000) 71 #define DMUB_CW1_BASE (0x61000000) 72 #define DMUB_CW3_BASE (0x63000000) 73 #define DMUB_CW4_BASE (0x64000000) 74 #define DMUB_CW5_BASE (0x65000000) 75 #define DMUB_CW6_BASE (0x66000000) 76 77 #define DMUB_REGION5_BASE (0xA0000000) 78 79 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 80 { 81 return (val + factor - 1) / factor * factor; 82 } 83 84 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 85 { 86 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 87 uint8_t buf[64]; 88 uint32_t pos, end; 89 90 /** 91 * Read 64-byte chunks since we don't want to store a 92 * large temporary buffer for this purpose. 93 */ 94 end = fb->size / sizeof(buf) * sizeof(buf); 95 96 for (pos = 0; pos < end; pos += sizeof(buf)) 97 dmub_memcpy(buf, base + pos, sizeof(buf)); 98 99 /* Read anything leftover into the buffer. */ 100 if (end < fb->size) 101 dmub_memcpy(buf, base + pos, fb->size - end); 102 } 103 104 static const struct dmub_fw_meta_info * 105 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 106 { 107 const union dmub_fw_meta *meta; 108 const uint8_t *blob = NULL; 109 uint32_t blob_size = 0; 110 uint32_t meta_offset = 0; 111 112 if (params->fw_bss_data && params->bss_data_size) { 113 /* Legacy metadata region. */ 114 blob = params->fw_bss_data; 115 blob_size = params->bss_data_size; 116 meta_offset = DMUB_FW_META_OFFSET; 117 } else if (params->fw_inst_const && params->inst_const_size) { 118 /* Combined metadata region. */ 119 blob = params->fw_inst_const; 120 blob_size = params->inst_const_size; 121 meta_offset = 0; 122 } 123 124 if (!blob || !blob_size) 125 return NULL; 126 127 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 128 return NULL; 129 130 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 131 sizeof(union dmub_fw_meta)); 132 133 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 134 return NULL; 135 136 return &meta->info; 137 } 138 139 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 140 { 141 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 142 143 switch (asic) { 144 case DMUB_ASIC_DCN20: 145 case DMUB_ASIC_DCN21: 146 case DMUB_ASIC_DCN30: 147 case DMUB_ASIC_DCN301: 148 case DMUB_ASIC_DCN302: 149 case DMUB_ASIC_DCN303: 150 dmub->regs = &dmub_srv_dcn20_regs; 151 152 funcs->reset = dmub_dcn20_reset; 153 funcs->reset_release = dmub_dcn20_reset_release; 154 funcs->backdoor_load = dmub_dcn20_backdoor_load; 155 funcs->setup_windows = dmub_dcn20_setup_windows; 156 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 157 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 158 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 159 funcs->is_supported = dmub_dcn20_is_supported; 160 funcs->is_hw_init = dmub_dcn20_is_hw_init; 161 funcs->set_gpint = dmub_dcn20_set_gpint; 162 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 163 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 164 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 165 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 166 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 167 funcs->get_current_time = dmub_dcn20_get_current_time; 168 169 // Out mailbox register access functions for RN and above 170 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 171 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 172 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 173 174 //outbox0 call stacks 175 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 176 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 177 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 178 179 if (asic == DMUB_ASIC_DCN21) { 180 dmub->regs = &dmub_srv_dcn21_regs; 181 182 funcs->is_phy_init = dmub_dcn21_is_phy_init; 183 } 184 if (asic == DMUB_ASIC_DCN30) { 185 dmub->regs = &dmub_srv_dcn30_regs; 186 187 funcs->backdoor_load = dmub_dcn30_backdoor_load; 188 funcs->setup_windows = dmub_dcn30_setup_windows; 189 } 190 if (asic == DMUB_ASIC_DCN301) { 191 dmub->regs = &dmub_srv_dcn301_regs; 192 193 funcs->backdoor_load = dmub_dcn30_backdoor_load; 194 funcs->setup_windows = dmub_dcn30_setup_windows; 195 } 196 if (asic == DMUB_ASIC_DCN302) { 197 dmub->regs = &dmub_srv_dcn302_regs; 198 199 funcs->backdoor_load = dmub_dcn30_backdoor_load; 200 funcs->setup_windows = dmub_dcn30_setup_windows; 201 } 202 if (asic == DMUB_ASIC_DCN303) { 203 dmub->regs = &dmub_srv_dcn303_regs; 204 205 funcs->backdoor_load = dmub_dcn30_backdoor_load; 206 funcs->setup_windows = dmub_dcn30_setup_windows; 207 } 208 break; 209 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 210 211 case DMUB_ASIC_DCN31: 212 funcs->reset = dmub_dcn31_reset; 213 funcs->reset_release = dmub_dcn31_reset_release; 214 funcs->backdoor_load = dmub_dcn31_backdoor_load; 215 funcs->setup_windows = dmub_dcn31_setup_windows; 216 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 217 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 218 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 219 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 220 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 221 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 222 funcs->is_supported = dmub_dcn31_is_supported; 223 funcs->is_hw_init = dmub_dcn31_is_hw_init; 224 funcs->set_gpint = dmub_dcn31_set_gpint; 225 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 226 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 227 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 228 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 229 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 230 //outbox0 call stacks 231 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 232 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 233 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 234 235 if (asic == DMUB_ASIC_DCN31) { 236 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 237 } 238 239 funcs->get_current_time = dmub_dcn31_get_current_time; 240 241 break; 242 #endif 243 244 default: 245 return false; 246 } 247 248 return true; 249 } 250 251 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 252 const struct dmub_srv_create_params *params) 253 { 254 enum dmub_status status = DMUB_STATUS_OK; 255 256 dmub_memset(dmub, 0, sizeof(*dmub)); 257 258 dmub->funcs = params->funcs; 259 dmub->user_ctx = params->user_ctx; 260 dmub->asic = params->asic; 261 dmub->fw_version = params->fw_version; 262 dmub->is_virtual = params->is_virtual; 263 264 /* Setup asic dependent hardware funcs. */ 265 if (!dmub_srv_hw_setup(dmub, params->asic)) { 266 status = DMUB_STATUS_INVALID; 267 goto cleanup; 268 } 269 270 /* Override (some) hardware funcs based on user params. */ 271 if (params->hw_funcs) { 272 if (params->hw_funcs->emul_get_inbox1_rptr) 273 dmub->hw_funcs.emul_get_inbox1_rptr = 274 params->hw_funcs->emul_get_inbox1_rptr; 275 276 if (params->hw_funcs->emul_set_inbox1_wptr) 277 dmub->hw_funcs.emul_set_inbox1_wptr = 278 params->hw_funcs->emul_set_inbox1_wptr; 279 280 if (params->hw_funcs->is_supported) 281 dmub->hw_funcs.is_supported = 282 params->hw_funcs->is_supported; 283 } 284 285 /* Sanity checks for required hw func pointers. */ 286 if (!dmub->hw_funcs.get_inbox1_rptr || 287 !dmub->hw_funcs.set_inbox1_wptr) { 288 status = DMUB_STATUS_INVALID; 289 goto cleanup; 290 } 291 292 cleanup: 293 if (status == DMUB_STATUS_OK) 294 dmub->sw_init = true; 295 else 296 dmub_srv_destroy(dmub); 297 298 return status; 299 } 300 301 void dmub_srv_destroy(struct dmub_srv *dmub) 302 { 303 dmub_memset(dmub, 0, sizeof(*dmub)); 304 } 305 306 enum dmub_status 307 dmub_srv_calc_region_info(struct dmub_srv *dmub, 308 const struct dmub_srv_region_params *params, 309 struct dmub_srv_region_info *out) 310 { 311 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 312 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 313 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 314 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 315 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 316 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 317 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 318 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 319 const struct dmub_fw_meta_info *fw_info; 320 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 321 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 322 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 323 324 if (!dmub->sw_init) 325 return DMUB_STATUS_INVALID; 326 327 memset(out, 0, sizeof(*out)); 328 329 out->num_regions = DMUB_NUM_WINDOWS; 330 331 inst->base = 0x0; 332 inst->top = inst->base + params->inst_const_size; 333 334 data->base = dmub_align(inst->top, 256); 335 data->top = data->base + params->bss_data_size; 336 337 /* 338 * All cache windows below should be aligned to the size 339 * of the DMCUB cache line, 64 bytes. 340 */ 341 342 stack->base = dmub_align(data->top, 256); 343 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 344 345 bios->base = dmub_align(stack->top, 256); 346 bios->top = bios->base + params->vbios_size; 347 348 mail->base = dmub_align(bios->top, 256); 349 mail->top = mail->base + DMUB_MAILBOX_SIZE; 350 351 fw_info = dmub_get_fw_meta_info(params); 352 353 if (fw_info) { 354 fw_state_size = fw_info->fw_region_size; 355 trace_buffer_size = fw_info->trace_buffer_size; 356 357 /** 358 * If DM didn't fill in a version, then fill it in based on 359 * the firmware meta now that we have it. 360 * 361 * TODO: Make it easier for driver to extract this out to 362 * pass during creation. 363 */ 364 if (dmub->fw_version == 0) 365 dmub->fw_version = fw_info->fw_version; 366 } 367 368 trace_buff->base = dmub_align(mail->top, 256); 369 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 370 371 fw_state->base = dmub_align(trace_buff->top, 256); 372 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 373 374 scratch_mem->base = dmub_align(fw_state->top, 256); 375 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 376 377 out->fb_size = dmub_align(scratch_mem->top, 4096); 378 379 return DMUB_STATUS_OK; 380 } 381 382 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 383 const struct dmub_srv_fb_params *params, 384 struct dmub_srv_fb_info *out) 385 { 386 uint8_t *cpu_base; 387 uint64_t gpu_base; 388 uint32_t i; 389 390 if (!dmub->sw_init) 391 return DMUB_STATUS_INVALID; 392 393 memset(out, 0, sizeof(*out)); 394 395 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 396 return DMUB_STATUS_INVALID; 397 398 cpu_base = (uint8_t *)params->cpu_addr; 399 gpu_base = params->gpu_addr; 400 401 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 402 const struct dmub_region *reg = 403 ¶ms->region_info->regions[i]; 404 405 out->fb[i].cpu_addr = cpu_base + reg->base; 406 out->fb[i].gpu_addr = gpu_base + reg->base; 407 out->fb[i].size = reg->top - reg->base; 408 } 409 410 out->num_fb = DMUB_NUM_WINDOWS; 411 412 return DMUB_STATUS_OK; 413 } 414 415 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 416 bool *is_supported) 417 { 418 *is_supported = false; 419 420 if (!dmub->sw_init) 421 return DMUB_STATUS_INVALID; 422 423 if (dmub->hw_funcs.is_supported) 424 *is_supported = dmub->hw_funcs.is_supported(dmub); 425 426 return DMUB_STATUS_OK; 427 } 428 429 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 430 { 431 *is_hw_init = false; 432 433 if (!dmub->sw_init) 434 return DMUB_STATUS_INVALID; 435 436 if (!dmub->hw_init) 437 return DMUB_STATUS_OK; 438 439 if (dmub->hw_funcs.is_hw_init) 440 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 441 442 return DMUB_STATUS_OK; 443 } 444 445 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 446 const struct dmub_srv_hw_params *params) 447 { 448 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 449 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 450 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 451 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 452 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 453 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 454 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 455 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 456 457 struct dmub_rb_init_params rb_params, outbox0_rb_params; 458 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 459 struct dmub_region inbox1, outbox1, outbox0; 460 461 if (!dmub->sw_init) 462 return DMUB_STATUS_INVALID; 463 464 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 465 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 466 ASSERT(0); 467 return DMUB_STATUS_INVALID; 468 } 469 470 dmub->fb_base = params->fb_base; 471 dmub->fb_offset = params->fb_offset; 472 dmub->psp_version = params->psp_version; 473 474 if (dmub->hw_funcs.reset) 475 dmub->hw_funcs.reset(dmub); 476 477 cw0.offset.quad_part = inst_fb->gpu_addr; 478 cw0.region.base = DMUB_CW0_BASE; 479 cw0.region.top = cw0.region.base + inst_fb->size - 1; 480 481 cw1.offset.quad_part = stack_fb->gpu_addr; 482 cw1.region.base = DMUB_CW1_BASE; 483 cw1.region.top = cw1.region.base + stack_fb->size - 1; 484 485 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 486 /** 487 * Read back all the instruction memory so we don't hang the 488 * DMCUB when backdoor loading if the write from x86 hasn't been 489 * flushed yet. This only occurs in backdoor loading. 490 */ 491 dmub_flush_buffer_mem(inst_fb); 492 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 493 } 494 495 cw2.offset.quad_part = data_fb->gpu_addr; 496 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 497 cw2.region.top = cw2.region.base + data_fb->size; 498 499 cw3.offset.quad_part = bios_fb->gpu_addr; 500 cw3.region.base = DMUB_CW3_BASE; 501 cw3.region.top = cw3.region.base + bios_fb->size; 502 503 cw4.offset.quad_part = mail_fb->gpu_addr; 504 cw4.region.base = DMUB_CW4_BASE; 505 cw4.region.top = cw4.region.base + mail_fb->size; 506 507 /** 508 * Doubled the mailbox region to accomodate inbox and outbox. 509 * Note: Currently, currently total mailbox size is 16KB. It is split 510 * equally into 8KB between inbox and outbox. If this config is 511 * changed, then uncached base address configuration of outbox1 512 * has to be updated in funcs->setup_out_mailbox. 513 */ 514 inbox1.base = cw4.region.base; 515 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 516 outbox1.base = inbox1.top; 517 outbox1.top = cw4.region.top; 518 519 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 520 cw5.region.base = DMUB_CW5_BASE; 521 cw5.region.top = cw5.region.base + tracebuff_fb->size; 522 523 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 524 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 525 526 cw6.offset.quad_part = fw_state_fb->gpu_addr; 527 cw6.region.base = DMUB_CW6_BASE; 528 cw6.region.top = cw6.region.base + fw_state_fb->size; 529 530 dmub->fw_state = fw_state_fb->cpu_addr; 531 532 dmub->scratch_mem_fb = *scratch_mem_fb; 533 534 if (dmub->hw_funcs.setup_windows) 535 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 536 537 if (dmub->hw_funcs.setup_outbox0) 538 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 539 540 if (dmub->hw_funcs.setup_mailbox) 541 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 542 if (dmub->hw_funcs.setup_out_mailbox) 543 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 544 545 dmub_memset(&rb_params, 0, sizeof(rb_params)); 546 rb_params.ctx = dmub; 547 rb_params.base_address = mail_fb->cpu_addr; 548 rb_params.capacity = DMUB_RB_SIZE; 549 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 550 551 // Initialize outbox1 ring buffer 552 rb_params.ctx = dmub; 553 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 554 rb_params.capacity = DMUB_RB_SIZE; 555 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 556 557 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 558 outbox0_rb_params.ctx = dmub; 559 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 560 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 561 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 562 563 /* Report to DMUB what features are supported by current driver */ 564 if (dmub->hw_funcs.enable_dmub_boot_options) 565 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 566 567 if (dmub->hw_funcs.reset_release) 568 dmub->hw_funcs.reset_release(dmub); 569 570 dmub->hw_init = true; 571 572 return DMUB_STATUS_OK; 573 } 574 575 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 576 { 577 if (!dmub->sw_init) 578 return DMUB_STATUS_INVALID; 579 580 if (dmub->hw_funcs.reset) 581 dmub->hw_funcs.reset(dmub); 582 583 dmub->hw_init = false; 584 585 return DMUB_STATUS_OK; 586 } 587 588 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 589 const union dmub_rb_cmd *cmd) 590 { 591 if (!dmub->hw_init) 592 return DMUB_STATUS_INVALID; 593 594 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 595 return DMUB_STATUS_OK; 596 597 return DMUB_STATUS_QUEUE_FULL; 598 } 599 600 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 601 { 602 if (!dmub->hw_init) 603 return DMUB_STATUS_INVALID; 604 605 /** 606 * Read back all the queued commands to ensure that they've 607 * been flushed to framebuffer memory. Otherwise DMCUB might 608 * read back stale, fully invalid or partially invalid data. 609 */ 610 dmub_rb_flush_pending(&dmub->inbox1_rb); 611 612 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 613 return DMUB_STATUS_OK; 614 } 615 616 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 617 uint32_t timeout_us) 618 { 619 uint32_t i; 620 621 if (!dmub->hw_init) 622 return DMUB_STATUS_INVALID; 623 624 for (i = 0; i <= timeout_us; i += 100) { 625 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 626 627 if (status.bits.dal_fw && status.bits.mailbox_rdy) 628 return DMUB_STATUS_OK; 629 630 udelay(100); 631 } 632 633 return DMUB_STATUS_TIMEOUT; 634 } 635 636 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 637 uint32_t timeout_us) 638 { 639 uint32_t i = 0; 640 641 if (!dmub->hw_init) 642 return DMUB_STATUS_INVALID; 643 644 if (!dmub->hw_funcs.is_phy_init) 645 return DMUB_STATUS_OK; 646 647 for (i = 0; i <= timeout_us; i += 10) { 648 if (dmub->hw_funcs.is_phy_init(dmub)) 649 return DMUB_STATUS_OK; 650 651 udelay(10); 652 } 653 654 return DMUB_STATUS_TIMEOUT; 655 } 656 657 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 658 uint32_t timeout_us) 659 { 660 uint32_t i; 661 662 if (!dmub->hw_init) 663 return DMUB_STATUS_INVALID; 664 665 for (i = 0; i <= timeout_us; ++i) { 666 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 667 if (dmub_rb_empty(&dmub->inbox1_rb)) 668 return DMUB_STATUS_OK; 669 670 udelay(1); 671 } 672 673 return DMUB_STATUS_TIMEOUT; 674 } 675 676 enum dmub_status 677 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 678 enum dmub_gpint_command command_code, 679 uint16_t param, uint32_t timeout_us) 680 { 681 union dmub_gpint_data_register reg; 682 uint32_t i; 683 684 if (!dmub->sw_init) 685 return DMUB_STATUS_INVALID; 686 687 if (!dmub->hw_funcs.set_gpint) 688 return DMUB_STATUS_INVALID; 689 690 if (!dmub->hw_funcs.is_gpint_acked) 691 return DMUB_STATUS_INVALID; 692 693 reg.bits.status = 1; 694 reg.bits.command_code = command_code; 695 reg.bits.param = param; 696 697 dmub->hw_funcs.set_gpint(dmub, reg); 698 699 for (i = 0; i < timeout_us; ++i) { 700 udelay(1); 701 702 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 703 return DMUB_STATUS_OK; 704 } 705 706 return DMUB_STATUS_TIMEOUT; 707 } 708 709 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 710 uint32_t *response) 711 { 712 *response = 0; 713 714 if (!dmub->sw_init) 715 return DMUB_STATUS_INVALID; 716 717 if (!dmub->hw_funcs.get_gpint_response) 718 return DMUB_STATUS_INVALID; 719 720 *response = dmub->hw_funcs.get_gpint_response(dmub); 721 722 return DMUB_STATUS_OK; 723 } 724 725 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 726 union dmub_fw_boot_status *status) 727 { 728 status->all = 0; 729 730 if (!dmub->sw_init) 731 return DMUB_STATUS_INVALID; 732 733 if (dmub->hw_funcs.get_fw_status) 734 *status = dmub->hw_funcs.get_fw_status(dmub); 735 736 return DMUB_STATUS_OK; 737 } 738 739 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 740 union dmub_rb_cmd *cmd) 741 { 742 enum dmub_status status = DMUB_STATUS_OK; 743 744 // Queue command 745 status = dmub_srv_cmd_queue(dmub, cmd); 746 747 if (status != DMUB_STATUS_OK) 748 return status; 749 750 // Execute command 751 status = dmub_srv_cmd_execute(dmub); 752 753 if (status != DMUB_STATUS_OK) 754 return status; 755 756 // Wait for DMUB to process command 757 status = dmub_srv_wait_for_idle(dmub, 100000); 758 759 if (status != DMUB_STATUS_OK) 760 return status; 761 762 // Copy data back from ring buffer into command 763 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 764 765 return status; 766 } 767 768 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 769 void *entry) 770 { 771 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 772 uint64_t *dst = (uint64_t *)entry; 773 uint8_t i; 774 uint8_t loop_count; 775 776 if (rb->rptr == rb->wrpt) 777 return false; 778 779 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 780 // copying data 781 for (i = 0; i < loop_count; i++) 782 *dst++ = *src++; 783 784 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 785 786 rb->rptr %= rb->capacity; 787 788 return true; 789 } 790 791 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 792 { 793 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 794 795 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 796 } 797