1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "os_types.h" 40 /* 41 * Note: the DMUB service is standalone. No additional headers should be 42 * added below or above this line unless they reside within the DMUB 43 * folder. 44 */ 45 46 /* Alignment for framebuffer memory. */ 47 #define DMUB_FB_ALIGNMENT (1024 * 1024) 48 49 /* Stack size. */ 50 #define DMUB_STACK_SIZE (128 * 1024) 51 52 /* Context size. */ 53 #define DMUB_CONTEXT_SIZE (512 * 1024) 54 55 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 57 58 /* Default state size if meta is absent. */ 59 #define DMUB_FW_STATE_SIZE (64 * 1024) 60 61 /* Default tracebuffer size if meta is absent. */ 62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 63 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (256) 67 68 /* Number of windows in use. */ 69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 70 /* Base addresses. */ 71 72 #define DMUB_CW0_BASE (0x60000000) 73 #define DMUB_CW1_BASE (0x61000000) 74 #define DMUB_CW3_BASE (0x63000000) 75 #define DMUB_CW4_BASE (0x64000000) 76 #define DMUB_CW5_BASE (0x65000000) 77 #define DMUB_CW6_BASE (0x66000000) 78 79 #define DMUB_REGION5_BASE (0xA0000000) 80 81 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 82 { 83 return (val + factor - 1) / factor * factor; 84 } 85 86 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 87 { 88 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 89 uint8_t buf[64]; 90 uint32_t pos, end; 91 92 /** 93 * Read 64-byte chunks since we don't want to store a 94 * large temporary buffer for this purpose. 95 */ 96 end = fb->size / sizeof(buf) * sizeof(buf); 97 98 for (pos = 0; pos < end; pos += sizeof(buf)) 99 dmub_memcpy(buf, base + pos, sizeof(buf)); 100 101 /* Read anything leftover into the buffer. */ 102 if (end < fb->size) 103 dmub_memcpy(buf, base + pos, fb->size - end); 104 } 105 106 static const struct dmub_fw_meta_info * 107 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 108 { 109 const union dmub_fw_meta *meta; 110 111 if (!blob || !blob_size) 112 return NULL; 113 114 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 115 return NULL; 116 117 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 118 sizeof(union dmub_fw_meta)); 119 120 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 121 return NULL; 122 123 return &meta->info; 124 } 125 126 static const struct dmub_fw_meta_info * 127 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 128 { 129 const struct dmub_fw_meta_info *info = NULL; 130 131 if (params->fw_bss_data && params->bss_data_size) { 132 /* Legacy metadata region. */ 133 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 134 params->bss_data_size, 135 DMUB_FW_META_OFFSET); 136 } else if (params->fw_inst_const && params->inst_const_size) { 137 /* Combined metadata region - can be aligned to 16-bytes. */ 138 uint32_t i; 139 140 for (i = 0; i < 16; ++i) { 141 info = dmub_get_fw_meta_info_from_blob( 142 params->fw_inst_const, params->inst_const_size, i); 143 144 if (info) 145 break; 146 } 147 } 148 149 return info; 150 } 151 152 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 153 { 154 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 155 156 switch (asic) { 157 case DMUB_ASIC_DCN20: 158 case DMUB_ASIC_DCN21: 159 case DMUB_ASIC_DCN30: 160 case DMUB_ASIC_DCN301: 161 case DMUB_ASIC_DCN302: 162 case DMUB_ASIC_DCN303: 163 dmub->regs = &dmub_srv_dcn20_regs; 164 165 funcs->reset = dmub_dcn20_reset; 166 funcs->reset_release = dmub_dcn20_reset_release; 167 funcs->backdoor_load = dmub_dcn20_backdoor_load; 168 funcs->setup_windows = dmub_dcn20_setup_windows; 169 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 170 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 171 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 172 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 173 funcs->is_supported = dmub_dcn20_is_supported; 174 funcs->is_hw_init = dmub_dcn20_is_hw_init; 175 funcs->set_gpint = dmub_dcn20_set_gpint; 176 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 177 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 178 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 179 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 180 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 181 funcs->get_current_time = dmub_dcn20_get_current_time; 182 183 // Out mailbox register access functions for RN and above 184 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 185 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 186 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 187 188 //outbox0 call stacks 189 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 190 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 191 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 192 193 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 194 195 if (asic == DMUB_ASIC_DCN21) 196 dmub->regs = &dmub_srv_dcn21_regs; 197 198 if (asic == DMUB_ASIC_DCN30) { 199 dmub->regs = &dmub_srv_dcn30_regs; 200 201 funcs->backdoor_load = dmub_dcn30_backdoor_load; 202 funcs->setup_windows = dmub_dcn30_setup_windows; 203 } 204 if (asic == DMUB_ASIC_DCN301) { 205 dmub->regs = &dmub_srv_dcn301_regs; 206 207 funcs->backdoor_load = dmub_dcn30_backdoor_load; 208 funcs->setup_windows = dmub_dcn30_setup_windows; 209 } 210 if (asic == DMUB_ASIC_DCN302) { 211 dmub->regs = &dmub_srv_dcn302_regs; 212 213 funcs->backdoor_load = dmub_dcn30_backdoor_load; 214 funcs->setup_windows = dmub_dcn30_setup_windows; 215 } 216 if (asic == DMUB_ASIC_DCN303) { 217 dmub->regs = &dmub_srv_dcn303_regs; 218 219 funcs->backdoor_load = dmub_dcn30_backdoor_load; 220 funcs->setup_windows = dmub_dcn30_setup_windows; 221 } 222 break; 223 224 case DMUB_ASIC_DCN31: 225 case DMUB_ASIC_DCN31B: 226 case DMUB_ASIC_DCN314: 227 case DMUB_ASIC_DCN315: 228 case DMUB_ASIC_DCN316: 229 if (asic == DMUB_ASIC_DCN314) { 230 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 231 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 232 } else if (asic == DMUB_ASIC_DCN315) { 233 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 234 } else if (asic == DMUB_ASIC_DCN316) { 235 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 236 } else { 237 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 238 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 239 } 240 funcs->reset = dmub_dcn31_reset; 241 funcs->reset_release = dmub_dcn31_reset_release; 242 funcs->backdoor_load = dmub_dcn31_backdoor_load; 243 funcs->setup_windows = dmub_dcn31_setup_windows; 244 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 245 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 246 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 247 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 248 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 249 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 250 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 251 funcs->is_supported = dmub_dcn31_is_supported; 252 funcs->is_hw_init = dmub_dcn31_is_hw_init; 253 funcs->set_gpint = dmub_dcn31_set_gpint; 254 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 255 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 256 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 257 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 258 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 259 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 260 //outbox0 call stacks 261 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 262 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 263 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 264 265 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 266 funcs->should_detect = dmub_dcn31_should_detect; 267 funcs->get_current_time = dmub_dcn31_get_current_time; 268 269 break; 270 271 case DMUB_ASIC_DCN32: 272 case DMUB_ASIC_DCN321: 273 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 274 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 275 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 276 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 277 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 278 funcs->reset = dmub_dcn32_reset; 279 funcs->reset_release = dmub_dcn32_reset_release; 280 funcs->backdoor_load = dmub_dcn32_backdoor_load; 281 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 282 funcs->setup_windows = dmub_dcn32_setup_windows; 283 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 284 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 285 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 286 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 287 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 288 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 289 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 290 funcs->is_supported = dmub_dcn32_is_supported; 291 funcs->is_hw_init = dmub_dcn32_is_hw_init; 292 funcs->set_gpint = dmub_dcn32_set_gpint; 293 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 294 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 295 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 296 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 297 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 298 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 299 300 /* outbox0 call stacks */ 301 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 302 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 303 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 304 funcs->get_current_time = dmub_dcn32_get_current_time; 305 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 306 307 break; 308 309 default: 310 return false; 311 } 312 313 return true; 314 } 315 316 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 317 const struct dmub_srv_create_params *params) 318 { 319 enum dmub_status status = DMUB_STATUS_OK; 320 321 dmub_memset(dmub, 0, sizeof(*dmub)); 322 323 dmub->funcs = params->funcs; 324 dmub->user_ctx = params->user_ctx; 325 dmub->asic = params->asic; 326 dmub->fw_version = params->fw_version; 327 dmub->is_virtual = params->is_virtual; 328 329 /* Setup asic dependent hardware funcs. */ 330 if (!dmub_srv_hw_setup(dmub, params->asic)) { 331 status = DMUB_STATUS_INVALID; 332 goto cleanup; 333 } 334 335 /* Override (some) hardware funcs based on user params. */ 336 if (params->hw_funcs) { 337 if (params->hw_funcs->emul_get_inbox1_rptr) 338 dmub->hw_funcs.emul_get_inbox1_rptr = 339 params->hw_funcs->emul_get_inbox1_rptr; 340 341 if (params->hw_funcs->emul_set_inbox1_wptr) 342 dmub->hw_funcs.emul_set_inbox1_wptr = 343 params->hw_funcs->emul_set_inbox1_wptr; 344 345 if (params->hw_funcs->is_supported) 346 dmub->hw_funcs.is_supported = 347 params->hw_funcs->is_supported; 348 } 349 350 /* Sanity checks for required hw func pointers. */ 351 if (!dmub->hw_funcs.get_inbox1_rptr || 352 !dmub->hw_funcs.set_inbox1_wptr) { 353 status = DMUB_STATUS_INVALID; 354 goto cleanup; 355 } 356 357 cleanup: 358 if (status == DMUB_STATUS_OK) 359 dmub->sw_init = true; 360 else 361 dmub_srv_destroy(dmub); 362 363 return status; 364 } 365 366 void dmub_srv_destroy(struct dmub_srv *dmub) 367 { 368 dmub_memset(dmub, 0, sizeof(*dmub)); 369 } 370 371 enum dmub_status 372 dmub_srv_calc_region_info(struct dmub_srv *dmub, 373 const struct dmub_srv_region_params *params, 374 struct dmub_srv_region_info *out) 375 { 376 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 377 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 378 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 379 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 380 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 381 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 382 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 383 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 384 const struct dmub_fw_meta_info *fw_info; 385 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 386 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 387 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 388 389 if (!dmub->sw_init) 390 return DMUB_STATUS_INVALID; 391 392 memset(out, 0, sizeof(*out)); 393 394 out->num_regions = DMUB_NUM_WINDOWS; 395 396 inst->base = 0x0; 397 inst->top = inst->base + params->inst_const_size; 398 399 data->base = dmub_align(inst->top, 256); 400 data->top = data->base + params->bss_data_size; 401 402 /* 403 * All cache windows below should be aligned to the size 404 * of the DMCUB cache line, 64 bytes. 405 */ 406 407 stack->base = dmub_align(data->top, 256); 408 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 409 410 bios->base = dmub_align(stack->top, 256); 411 bios->top = bios->base + params->vbios_size; 412 413 mail->base = dmub_align(bios->top, 256); 414 mail->top = mail->base + DMUB_MAILBOX_SIZE; 415 416 fw_info = dmub_get_fw_meta_info(params); 417 418 if (fw_info) { 419 fw_state_size = fw_info->fw_region_size; 420 trace_buffer_size = fw_info->trace_buffer_size; 421 422 /** 423 * If DM didn't fill in a version, then fill it in based on 424 * the firmware meta now that we have it. 425 * 426 * TODO: Make it easier for driver to extract this out to 427 * pass during creation. 428 */ 429 if (dmub->fw_version == 0) 430 dmub->fw_version = fw_info->fw_version; 431 } 432 433 trace_buff->base = dmub_align(mail->top, 256); 434 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 435 436 fw_state->base = dmub_align(trace_buff->top, 256); 437 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 438 439 scratch_mem->base = dmub_align(fw_state->top, 256); 440 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 441 442 out->fb_size = dmub_align(scratch_mem->top, 4096); 443 444 return DMUB_STATUS_OK; 445 } 446 447 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 448 const struct dmub_srv_fb_params *params, 449 struct dmub_srv_fb_info *out) 450 { 451 uint8_t *cpu_base; 452 uint64_t gpu_base; 453 uint32_t i; 454 455 if (!dmub->sw_init) 456 return DMUB_STATUS_INVALID; 457 458 memset(out, 0, sizeof(*out)); 459 460 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 461 return DMUB_STATUS_INVALID; 462 463 cpu_base = (uint8_t *)params->cpu_addr; 464 gpu_base = params->gpu_addr; 465 466 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 467 const struct dmub_region *reg = 468 ¶ms->region_info->regions[i]; 469 470 out->fb[i].cpu_addr = cpu_base + reg->base; 471 out->fb[i].gpu_addr = gpu_base + reg->base; 472 out->fb[i].size = reg->top - reg->base; 473 } 474 475 out->num_fb = DMUB_NUM_WINDOWS; 476 477 return DMUB_STATUS_OK; 478 } 479 480 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 481 bool *is_supported) 482 { 483 *is_supported = false; 484 485 if (!dmub->sw_init) 486 return DMUB_STATUS_INVALID; 487 488 if (dmub->hw_funcs.is_supported) 489 *is_supported = dmub->hw_funcs.is_supported(dmub); 490 491 return DMUB_STATUS_OK; 492 } 493 494 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 495 { 496 *is_hw_init = false; 497 498 if (!dmub->sw_init) 499 return DMUB_STATUS_INVALID; 500 501 if (!dmub->hw_init) 502 return DMUB_STATUS_OK; 503 504 if (dmub->hw_funcs.is_hw_init) 505 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 506 507 return DMUB_STATUS_OK; 508 } 509 510 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 511 const struct dmub_srv_hw_params *params) 512 { 513 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 514 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 515 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 516 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 517 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 518 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 519 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 520 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 521 522 struct dmub_rb_init_params rb_params, outbox0_rb_params; 523 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 524 struct dmub_region inbox1, outbox1, outbox0; 525 526 if (!dmub->sw_init) 527 return DMUB_STATUS_INVALID; 528 529 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 530 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 531 ASSERT(0); 532 return DMUB_STATUS_INVALID; 533 } 534 535 dmub->fb_base = params->fb_base; 536 dmub->fb_offset = params->fb_offset; 537 dmub->psp_version = params->psp_version; 538 539 if (dmub->hw_funcs.reset) 540 dmub->hw_funcs.reset(dmub); 541 542 /* reset the cache of the last wptr as well now that hw is reset */ 543 dmub->inbox1_last_wptr = 0; 544 545 cw0.offset.quad_part = inst_fb->gpu_addr; 546 cw0.region.base = DMUB_CW0_BASE; 547 cw0.region.top = cw0.region.base + inst_fb->size - 1; 548 549 cw1.offset.quad_part = stack_fb->gpu_addr; 550 cw1.region.base = DMUB_CW1_BASE; 551 cw1.region.top = cw1.region.base + stack_fb->size - 1; 552 553 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 554 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 555 556 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 557 /** 558 * Read back all the instruction memory so we don't hang the 559 * DMCUB when backdoor loading if the write from x86 hasn't been 560 * flushed yet. This only occurs in backdoor loading. 561 */ 562 dmub_flush_buffer_mem(inst_fb); 563 564 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 565 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 566 else 567 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 568 } 569 570 cw2.offset.quad_part = data_fb->gpu_addr; 571 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 572 cw2.region.top = cw2.region.base + data_fb->size; 573 574 cw3.offset.quad_part = bios_fb->gpu_addr; 575 cw3.region.base = DMUB_CW3_BASE; 576 cw3.region.top = cw3.region.base + bios_fb->size; 577 578 cw4.offset.quad_part = mail_fb->gpu_addr; 579 cw4.region.base = DMUB_CW4_BASE; 580 cw4.region.top = cw4.region.base + mail_fb->size; 581 582 /** 583 * Doubled the mailbox region to accomodate inbox and outbox. 584 * Note: Currently, currently total mailbox size is 16KB. It is split 585 * equally into 8KB between inbox and outbox. If this config is 586 * changed, then uncached base address configuration of outbox1 587 * has to be updated in funcs->setup_out_mailbox. 588 */ 589 inbox1.base = cw4.region.base; 590 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 591 outbox1.base = inbox1.top; 592 outbox1.top = cw4.region.top; 593 594 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 595 cw5.region.base = DMUB_CW5_BASE; 596 cw5.region.top = cw5.region.base + tracebuff_fb->size; 597 598 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 599 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 600 601 cw6.offset.quad_part = fw_state_fb->gpu_addr; 602 cw6.region.base = DMUB_CW6_BASE; 603 cw6.region.top = cw6.region.base + fw_state_fb->size; 604 605 dmub->fw_state = fw_state_fb->cpu_addr; 606 607 dmub->scratch_mem_fb = *scratch_mem_fb; 608 609 if (dmub->hw_funcs.setup_windows) 610 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 611 612 if (dmub->hw_funcs.setup_outbox0) 613 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 614 615 if (dmub->hw_funcs.setup_mailbox) 616 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 617 if (dmub->hw_funcs.setup_out_mailbox) 618 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 619 620 dmub_memset(&rb_params, 0, sizeof(rb_params)); 621 rb_params.ctx = dmub; 622 rb_params.base_address = mail_fb->cpu_addr; 623 rb_params.capacity = DMUB_RB_SIZE; 624 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 625 626 // Initialize outbox1 ring buffer 627 rb_params.ctx = dmub; 628 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 629 rb_params.capacity = DMUB_RB_SIZE; 630 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 631 632 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 633 outbox0_rb_params.ctx = dmub; 634 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 635 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 636 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 637 638 /* Report to DMUB what features are supported by current driver */ 639 if (dmub->hw_funcs.enable_dmub_boot_options) 640 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 641 642 if (dmub->hw_funcs.skip_dmub_panel_power_sequence) 643 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 644 params->skip_panel_power_sequence); 645 646 if (dmub->hw_funcs.reset_release) 647 dmub->hw_funcs.reset_release(dmub); 648 649 dmub->hw_init = true; 650 651 return DMUB_STATUS_OK; 652 } 653 654 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 655 { 656 if (!dmub->sw_init) 657 return DMUB_STATUS_INVALID; 658 659 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 660 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 661 dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 662 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 663 } 664 665 return DMUB_STATUS_OK; 666 } 667 668 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 669 { 670 if (!dmub->sw_init) 671 return DMUB_STATUS_INVALID; 672 673 if (dmub->hw_funcs.reset) 674 dmub->hw_funcs.reset(dmub); 675 676 /* mailboxes have been reset in hw, so reset the sw state as well */ 677 dmub->inbox1_last_wptr = 0; 678 dmub->inbox1_rb.wrpt = 0; 679 dmub->inbox1_rb.rptr = 0; 680 dmub->outbox0_rb.wrpt = 0; 681 dmub->outbox0_rb.rptr = 0; 682 dmub->outbox1_rb.wrpt = 0; 683 dmub->outbox1_rb.rptr = 0; 684 685 dmub->hw_init = false; 686 687 return DMUB_STATUS_OK; 688 } 689 690 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 691 const union dmub_rb_cmd *cmd) 692 { 693 if (!dmub->hw_init) 694 return DMUB_STATUS_INVALID; 695 696 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 697 return DMUB_STATUS_OK; 698 699 return DMUB_STATUS_QUEUE_FULL; 700 } 701 702 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 703 { 704 struct dmub_rb flush_rb; 705 706 if (!dmub->hw_init) 707 return DMUB_STATUS_INVALID; 708 709 /** 710 * Read back all the queued commands to ensure that they've 711 * been flushed to framebuffer memory. Otherwise DMCUB might 712 * read back stale, fully invalid or partially invalid data. 713 */ 714 flush_rb = dmub->inbox1_rb; 715 flush_rb.rptr = dmub->inbox1_last_wptr; 716 dmub_rb_flush_pending(&flush_rb); 717 718 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 719 720 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 721 722 return DMUB_STATUS_OK; 723 } 724 725 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 726 uint32_t timeout_us) 727 { 728 uint32_t i; 729 730 if (!dmub->hw_init) 731 return DMUB_STATUS_INVALID; 732 733 for (i = 0; i <= timeout_us; i += 100) { 734 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 735 736 if (status.bits.dal_fw && status.bits.mailbox_rdy) 737 return DMUB_STATUS_OK; 738 739 udelay(100); 740 } 741 742 return DMUB_STATUS_TIMEOUT; 743 } 744 745 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 746 uint32_t timeout_us) 747 { 748 uint32_t i, rptr; 749 750 if (!dmub->hw_init) 751 return DMUB_STATUS_INVALID; 752 753 for (i = 0; i <= timeout_us; ++i) { 754 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 755 756 if (rptr > dmub->inbox1_rb.capacity) 757 return DMUB_STATUS_HW_FAILURE; 758 759 dmub->inbox1_rb.rptr = rptr; 760 761 if (dmub_rb_empty(&dmub->inbox1_rb)) 762 return DMUB_STATUS_OK; 763 764 udelay(1); 765 } 766 767 return DMUB_STATUS_TIMEOUT; 768 } 769 770 enum dmub_status 771 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 772 enum dmub_gpint_command command_code, 773 uint16_t param, uint32_t timeout_us) 774 { 775 union dmub_gpint_data_register reg; 776 uint32_t i; 777 778 if (!dmub->sw_init) 779 return DMUB_STATUS_INVALID; 780 781 if (!dmub->hw_funcs.set_gpint) 782 return DMUB_STATUS_INVALID; 783 784 if (!dmub->hw_funcs.is_gpint_acked) 785 return DMUB_STATUS_INVALID; 786 787 reg.bits.status = 1; 788 reg.bits.command_code = command_code; 789 reg.bits.param = param; 790 791 dmub->hw_funcs.set_gpint(dmub, reg); 792 793 for (i = 0; i < timeout_us; ++i) { 794 udelay(1); 795 796 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 797 return DMUB_STATUS_OK; 798 } 799 800 return DMUB_STATUS_TIMEOUT; 801 } 802 803 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 804 uint32_t *response) 805 { 806 *response = 0; 807 808 if (!dmub->sw_init) 809 return DMUB_STATUS_INVALID; 810 811 if (!dmub->hw_funcs.get_gpint_response) 812 return DMUB_STATUS_INVALID; 813 814 *response = dmub->hw_funcs.get_gpint_response(dmub); 815 816 return DMUB_STATUS_OK; 817 } 818 819 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 820 uint32_t *dataout) 821 { 822 *dataout = 0; 823 824 if (!dmub->sw_init) 825 return DMUB_STATUS_INVALID; 826 827 if (!dmub->hw_funcs.get_gpint_dataout) 828 return DMUB_STATUS_INVALID; 829 830 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 831 832 return DMUB_STATUS_OK; 833 } 834 835 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 836 union dmub_fw_boot_status *status) 837 { 838 status->all = 0; 839 840 if (!dmub->sw_init) 841 return DMUB_STATUS_INVALID; 842 843 if (dmub->hw_funcs.get_fw_status) 844 *status = dmub->hw_funcs.get_fw_status(dmub); 845 846 return DMUB_STATUS_OK; 847 } 848 849 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 850 union dmub_rb_cmd *cmd) 851 { 852 enum dmub_status status = DMUB_STATUS_OK; 853 854 // Queue command 855 status = dmub_srv_cmd_queue(dmub, cmd); 856 857 if (status != DMUB_STATUS_OK) 858 return status; 859 860 // Execute command 861 status = dmub_srv_cmd_execute(dmub); 862 863 if (status != DMUB_STATUS_OK) 864 return status; 865 866 // Wait for DMUB to process command 867 status = dmub_srv_wait_for_idle(dmub, 100000); 868 869 if (status != DMUB_STATUS_OK) 870 return status; 871 872 // Copy data back from ring buffer into command 873 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 874 875 return status; 876 } 877 878 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 879 void *entry) 880 { 881 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 882 uint64_t *dst = (uint64_t *)entry; 883 uint8_t i; 884 uint8_t loop_count; 885 886 if (rb->rptr == rb->wrpt) 887 return false; 888 889 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 890 // copying data 891 for (i = 0; i < loop_count; i++) 892 *dst++ = *src++; 893 894 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 895 896 rb->rptr %= rb->capacity; 897 898 return true; 899 } 900 901 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 902 { 903 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 904 905 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 906 } 907 908 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 909 { 910 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 911 return false; 912 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 913 return true; 914 } 915 916 bool dmub_srv_should_detect(struct dmub_srv *dmub) 917 { 918 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 919 return false; 920 921 return dmub->hw_funcs.should_detect(dmub); 922 } 923 924 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 925 { 926 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 927 return DMUB_STATUS_INVALID; 928 929 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 930 return DMUB_STATUS_OK; 931 } 932 933 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 934 { 935 uint32_t i = 0; 936 uint32_t ack = 0; 937 938 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 939 return DMUB_STATUS_INVALID; 940 941 for (i = 0; i <= timeout_us; i++) { 942 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 943 if (ack) 944 return DMUB_STATUS_OK; 945 } 946 return DMUB_STATUS_TIMEOUT; 947 } 948 949 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 950 union dmub_inbox0_data_register data) 951 { 952 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 953 return DMUB_STATUS_INVALID; 954 955 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 956 return DMUB_STATUS_OK; 957 } 958