1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "os_types.h" 36 /* 37 * Note: the DMUB service is standalone. No additional headers should be 38 * added below or above this line unless they reside within the DMUB 39 * folder. 40 */ 41 42 /* Alignment for framebuffer memory. */ 43 #define DMUB_FB_ALIGNMENT (1024 * 1024) 44 45 /* Stack size. */ 46 #define DMUB_STACK_SIZE (128 * 1024) 47 48 /* Context size. */ 49 #define DMUB_CONTEXT_SIZE (512 * 1024) 50 51 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 52 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 53 54 /* Default state size if meta is absent. */ 55 #define DMUB_FW_STATE_SIZE (64 * 1024) 56 57 /* Default tracebuffer size if meta is absent. */ 58 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 59 60 61 /* Default scratch mem size. */ 62 #define DMUB_SCRATCH_MEM_SIZE (256) 63 64 /* Number of windows in use. */ 65 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 66 /* Base addresses. */ 67 68 #define DMUB_CW0_BASE (0x60000000) 69 #define DMUB_CW1_BASE (0x61000000) 70 #define DMUB_CW3_BASE (0x63000000) 71 #define DMUB_CW4_BASE (0x64000000) 72 #define DMUB_CW5_BASE (0x65000000) 73 #define DMUB_CW6_BASE (0x66000000) 74 75 #define DMUB_REGION5_BASE (0xA0000000) 76 77 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 78 { 79 return (val + factor - 1) / factor * factor; 80 } 81 82 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 83 { 84 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 85 uint8_t buf[64]; 86 uint32_t pos, end; 87 88 /** 89 * Read 64-byte chunks since we don't want to store a 90 * large temporary buffer for this purpose. 91 */ 92 end = fb->size / sizeof(buf) * sizeof(buf); 93 94 for (pos = 0; pos < end; pos += sizeof(buf)) 95 dmub_memcpy(buf, base + pos, sizeof(buf)); 96 97 /* Read anything leftover into the buffer. */ 98 if (end < fb->size) 99 dmub_memcpy(buf, base + pos, fb->size - end); 100 } 101 102 static const struct dmub_fw_meta_info * 103 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 104 { 105 const union dmub_fw_meta *meta; 106 const uint8_t *blob = NULL; 107 uint32_t blob_size = 0; 108 uint32_t meta_offset = 0; 109 110 if (params->fw_bss_data && params->bss_data_size) { 111 /* Legacy metadata region. */ 112 blob = params->fw_bss_data; 113 blob_size = params->bss_data_size; 114 meta_offset = DMUB_FW_META_OFFSET; 115 } else if (params->fw_inst_const && params->inst_const_size) { 116 /* Combined metadata region. */ 117 blob = params->fw_inst_const; 118 blob_size = params->inst_const_size; 119 meta_offset = 0; 120 } 121 122 if (!blob || !blob_size) 123 return NULL; 124 125 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 126 return NULL; 127 128 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 129 sizeof(union dmub_fw_meta)); 130 131 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 132 return NULL; 133 134 return &meta->info; 135 } 136 137 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 138 { 139 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 140 141 switch (asic) { 142 case DMUB_ASIC_DCN20: 143 case DMUB_ASIC_DCN21: 144 case DMUB_ASIC_DCN30: 145 case DMUB_ASIC_DCN301: 146 case DMUB_ASIC_DCN302: 147 case DMUB_ASIC_DCN303: 148 dmub->regs = &dmub_srv_dcn20_regs; 149 150 funcs->reset = dmub_dcn20_reset; 151 funcs->reset_release = dmub_dcn20_reset_release; 152 funcs->backdoor_load = dmub_dcn20_backdoor_load; 153 funcs->setup_windows = dmub_dcn20_setup_windows; 154 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 155 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 156 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 157 funcs->is_supported = dmub_dcn20_is_supported; 158 funcs->is_hw_init = dmub_dcn20_is_hw_init; 159 funcs->set_gpint = dmub_dcn20_set_gpint; 160 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 161 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 162 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 163 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 164 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 165 funcs->get_current_time = dmub_dcn20_get_current_time; 166 167 // Out mailbox register access functions for RN and above 168 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 169 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 170 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 171 172 //outbox0 call stacks 173 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 174 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 175 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 176 177 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 178 179 if (asic == DMUB_ASIC_DCN21) { 180 dmub->regs = &dmub_srv_dcn21_regs; 181 182 funcs->is_phy_init = dmub_dcn21_is_phy_init; 183 } 184 if (asic == DMUB_ASIC_DCN30) { 185 dmub->regs = &dmub_srv_dcn30_regs; 186 187 funcs->backdoor_load = dmub_dcn30_backdoor_load; 188 funcs->setup_windows = dmub_dcn30_setup_windows; 189 } 190 if (asic == DMUB_ASIC_DCN301) { 191 dmub->regs = &dmub_srv_dcn301_regs; 192 193 funcs->backdoor_load = dmub_dcn30_backdoor_load; 194 funcs->setup_windows = dmub_dcn30_setup_windows; 195 } 196 if (asic == DMUB_ASIC_DCN302) { 197 dmub->regs = &dmub_srv_dcn302_regs; 198 199 funcs->backdoor_load = dmub_dcn30_backdoor_load; 200 funcs->setup_windows = dmub_dcn30_setup_windows; 201 } 202 if (asic == DMUB_ASIC_DCN303) { 203 dmub->regs = &dmub_srv_dcn303_regs; 204 205 funcs->backdoor_load = dmub_dcn30_backdoor_load; 206 funcs->setup_windows = dmub_dcn30_setup_windows; 207 } 208 break; 209 210 case DMUB_ASIC_DCN31: 211 case DMUB_ASIC_DCN31B: 212 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 213 funcs->reset = dmub_dcn31_reset; 214 funcs->reset_release = dmub_dcn31_reset_release; 215 funcs->backdoor_load = dmub_dcn31_backdoor_load; 216 funcs->setup_windows = dmub_dcn31_setup_windows; 217 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 218 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 219 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 220 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 221 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 222 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 223 funcs->is_supported = dmub_dcn31_is_supported; 224 funcs->is_hw_init = dmub_dcn31_is_hw_init; 225 funcs->set_gpint = dmub_dcn31_set_gpint; 226 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 227 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 228 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 229 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 230 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 231 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 232 //outbox0 call stacks 233 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 234 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 235 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 236 237 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 238 funcs->should_detect = dmub_dcn31_should_detect; 239 funcs->get_current_time = dmub_dcn31_get_current_time; 240 241 break; 242 243 default: 244 return false; 245 } 246 247 return true; 248 } 249 250 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 251 const struct dmub_srv_create_params *params) 252 { 253 enum dmub_status status = DMUB_STATUS_OK; 254 255 dmub_memset(dmub, 0, sizeof(*dmub)); 256 257 dmub->funcs = params->funcs; 258 dmub->user_ctx = params->user_ctx; 259 dmub->asic = params->asic; 260 dmub->fw_version = params->fw_version; 261 dmub->is_virtual = params->is_virtual; 262 263 /* Setup asic dependent hardware funcs. */ 264 if (!dmub_srv_hw_setup(dmub, params->asic)) { 265 status = DMUB_STATUS_INVALID; 266 goto cleanup; 267 } 268 269 /* Override (some) hardware funcs based on user params. */ 270 if (params->hw_funcs) { 271 if (params->hw_funcs->emul_get_inbox1_rptr) 272 dmub->hw_funcs.emul_get_inbox1_rptr = 273 params->hw_funcs->emul_get_inbox1_rptr; 274 275 if (params->hw_funcs->emul_set_inbox1_wptr) 276 dmub->hw_funcs.emul_set_inbox1_wptr = 277 params->hw_funcs->emul_set_inbox1_wptr; 278 279 if (params->hw_funcs->is_supported) 280 dmub->hw_funcs.is_supported = 281 params->hw_funcs->is_supported; 282 } 283 284 /* Sanity checks for required hw func pointers. */ 285 if (!dmub->hw_funcs.get_inbox1_rptr || 286 !dmub->hw_funcs.set_inbox1_wptr) { 287 status = DMUB_STATUS_INVALID; 288 goto cleanup; 289 } 290 291 cleanup: 292 if (status == DMUB_STATUS_OK) 293 dmub->sw_init = true; 294 else 295 dmub_srv_destroy(dmub); 296 297 return status; 298 } 299 300 void dmub_srv_destroy(struct dmub_srv *dmub) 301 { 302 dmub_memset(dmub, 0, sizeof(*dmub)); 303 } 304 305 enum dmub_status 306 dmub_srv_calc_region_info(struct dmub_srv *dmub, 307 const struct dmub_srv_region_params *params, 308 struct dmub_srv_region_info *out) 309 { 310 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 311 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 312 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 313 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 314 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 315 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 316 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 317 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 318 const struct dmub_fw_meta_info *fw_info; 319 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 320 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 321 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 322 323 if (!dmub->sw_init) 324 return DMUB_STATUS_INVALID; 325 326 memset(out, 0, sizeof(*out)); 327 328 out->num_regions = DMUB_NUM_WINDOWS; 329 330 inst->base = 0x0; 331 inst->top = inst->base + params->inst_const_size; 332 333 data->base = dmub_align(inst->top, 256); 334 data->top = data->base + params->bss_data_size; 335 336 /* 337 * All cache windows below should be aligned to the size 338 * of the DMCUB cache line, 64 bytes. 339 */ 340 341 stack->base = dmub_align(data->top, 256); 342 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 343 344 bios->base = dmub_align(stack->top, 256); 345 bios->top = bios->base + params->vbios_size; 346 347 mail->base = dmub_align(bios->top, 256); 348 mail->top = mail->base + DMUB_MAILBOX_SIZE; 349 350 fw_info = dmub_get_fw_meta_info(params); 351 352 if (fw_info) { 353 fw_state_size = fw_info->fw_region_size; 354 trace_buffer_size = fw_info->trace_buffer_size; 355 356 /** 357 * If DM didn't fill in a version, then fill it in based on 358 * the firmware meta now that we have it. 359 * 360 * TODO: Make it easier for driver to extract this out to 361 * pass during creation. 362 */ 363 if (dmub->fw_version == 0) 364 dmub->fw_version = fw_info->fw_version; 365 } 366 367 trace_buff->base = dmub_align(mail->top, 256); 368 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 369 370 fw_state->base = dmub_align(trace_buff->top, 256); 371 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 372 373 scratch_mem->base = dmub_align(fw_state->top, 256); 374 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 375 376 out->fb_size = dmub_align(scratch_mem->top, 4096); 377 378 return DMUB_STATUS_OK; 379 } 380 381 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 382 const struct dmub_srv_fb_params *params, 383 struct dmub_srv_fb_info *out) 384 { 385 uint8_t *cpu_base; 386 uint64_t gpu_base; 387 uint32_t i; 388 389 if (!dmub->sw_init) 390 return DMUB_STATUS_INVALID; 391 392 memset(out, 0, sizeof(*out)); 393 394 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 395 return DMUB_STATUS_INVALID; 396 397 cpu_base = (uint8_t *)params->cpu_addr; 398 gpu_base = params->gpu_addr; 399 400 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 401 const struct dmub_region *reg = 402 ¶ms->region_info->regions[i]; 403 404 out->fb[i].cpu_addr = cpu_base + reg->base; 405 out->fb[i].gpu_addr = gpu_base + reg->base; 406 out->fb[i].size = reg->top - reg->base; 407 } 408 409 out->num_fb = DMUB_NUM_WINDOWS; 410 411 return DMUB_STATUS_OK; 412 } 413 414 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 415 bool *is_supported) 416 { 417 *is_supported = false; 418 419 if (!dmub->sw_init) 420 return DMUB_STATUS_INVALID; 421 422 if (dmub->hw_funcs.is_supported) 423 *is_supported = dmub->hw_funcs.is_supported(dmub); 424 425 return DMUB_STATUS_OK; 426 } 427 428 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 429 { 430 *is_hw_init = false; 431 432 if (!dmub->sw_init) 433 return DMUB_STATUS_INVALID; 434 435 if (!dmub->hw_init) 436 return DMUB_STATUS_OK; 437 438 if (dmub->hw_funcs.is_hw_init) 439 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 440 441 return DMUB_STATUS_OK; 442 } 443 444 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 445 const struct dmub_srv_hw_params *params) 446 { 447 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 448 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 449 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 450 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 451 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 452 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 453 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 454 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 455 456 struct dmub_rb_init_params rb_params, outbox0_rb_params; 457 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 458 struct dmub_region inbox1, outbox1, outbox0; 459 460 if (!dmub->sw_init) 461 return DMUB_STATUS_INVALID; 462 463 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 464 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 465 ASSERT(0); 466 return DMUB_STATUS_INVALID; 467 } 468 469 dmub->fb_base = params->fb_base; 470 dmub->fb_offset = params->fb_offset; 471 dmub->psp_version = params->psp_version; 472 473 if (dmub->hw_funcs.reset) 474 dmub->hw_funcs.reset(dmub); 475 476 cw0.offset.quad_part = inst_fb->gpu_addr; 477 cw0.region.base = DMUB_CW0_BASE; 478 cw0.region.top = cw0.region.base + inst_fb->size - 1; 479 480 cw1.offset.quad_part = stack_fb->gpu_addr; 481 cw1.region.base = DMUB_CW1_BASE; 482 cw1.region.top = cw1.region.base + stack_fb->size - 1; 483 484 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 485 /** 486 * Read back all the instruction memory so we don't hang the 487 * DMCUB when backdoor loading if the write from x86 hasn't been 488 * flushed yet. This only occurs in backdoor loading. 489 */ 490 dmub_flush_buffer_mem(inst_fb); 491 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 492 } 493 494 cw2.offset.quad_part = data_fb->gpu_addr; 495 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 496 cw2.region.top = cw2.region.base + data_fb->size; 497 498 cw3.offset.quad_part = bios_fb->gpu_addr; 499 cw3.region.base = DMUB_CW3_BASE; 500 cw3.region.top = cw3.region.base + bios_fb->size; 501 502 cw4.offset.quad_part = mail_fb->gpu_addr; 503 cw4.region.base = DMUB_CW4_BASE; 504 cw4.region.top = cw4.region.base + mail_fb->size; 505 506 /** 507 * Doubled the mailbox region to accomodate inbox and outbox. 508 * Note: Currently, currently total mailbox size is 16KB. It is split 509 * equally into 8KB between inbox and outbox. If this config is 510 * changed, then uncached base address configuration of outbox1 511 * has to be updated in funcs->setup_out_mailbox. 512 */ 513 inbox1.base = cw4.region.base; 514 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 515 outbox1.base = inbox1.top; 516 outbox1.top = cw4.region.top; 517 518 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 519 cw5.region.base = DMUB_CW5_BASE; 520 cw5.region.top = cw5.region.base + tracebuff_fb->size; 521 522 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 523 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 524 525 cw6.offset.quad_part = fw_state_fb->gpu_addr; 526 cw6.region.base = DMUB_CW6_BASE; 527 cw6.region.top = cw6.region.base + fw_state_fb->size; 528 529 dmub->fw_state = fw_state_fb->cpu_addr; 530 531 dmub->scratch_mem_fb = *scratch_mem_fb; 532 533 if (dmub->hw_funcs.setup_windows) 534 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 535 536 if (dmub->hw_funcs.setup_outbox0) 537 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 538 539 if (dmub->hw_funcs.setup_mailbox) 540 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 541 if (dmub->hw_funcs.setup_out_mailbox) 542 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 543 544 dmub_memset(&rb_params, 0, sizeof(rb_params)); 545 rb_params.ctx = dmub; 546 rb_params.base_address = mail_fb->cpu_addr; 547 rb_params.capacity = DMUB_RB_SIZE; 548 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 549 550 // Initialize outbox1 ring buffer 551 rb_params.ctx = dmub; 552 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 553 rb_params.capacity = DMUB_RB_SIZE; 554 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 555 556 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 557 outbox0_rb_params.ctx = dmub; 558 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 559 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 560 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 561 562 /* Report to DMUB what features are supported by current driver */ 563 if (dmub->hw_funcs.enable_dmub_boot_options) 564 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 565 566 if (dmub->hw_funcs.reset_release) 567 dmub->hw_funcs.reset_release(dmub); 568 569 dmub->hw_init = true; 570 571 return DMUB_STATUS_OK; 572 } 573 574 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 575 { 576 if (!dmub->sw_init) 577 return DMUB_STATUS_INVALID; 578 579 if (dmub->hw_funcs.reset) 580 dmub->hw_funcs.reset(dmub); 581 582 dmub->hw_init = false; 583 584 return DMUB_STATUS_OK; 585 } 586 587 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 588 const union dmub_rb_cmd *cmd) 589 { 590 if (!dmub->hw_init) 591 return DMUB_STATUS_INVALID; 592 593 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 594 return DMUB_STATUS_OK; 595 596 return DMUB_STATUS_QUEUE_FULL; 597 } 598 599 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 600 { 601 if (!dmub->hw_init) 602 return DMUB_STATUS_INVALID; 603 604 /** 605 * Read back all the queued commands to ensure that they've 606 * been flushed to framebuffer memory. Otherwise DMCUB might 607 * read back stale, fully invalid or partially invalid data. 608 */ 609 dmub_rb_flush_pending(&dmub->inbox1_rb); 610 611 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 612 return DMUB_STATUS_OK; 613 } 614 615 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 616 uint32_t timeout_us) 617 { 618 uint32_t i; 619 620 if (!dmub->hw_init) 621 return DMUB_STATUS_INVALID; 622 623 for (i = 0; i <= timeout_us; i += 100) { 624 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 625 626 if (status.bits.dal_fw && status.bits.mailbox_rdy) 627 return DMUB_STATUS_OK; 628 629 udelay(100); 630 } 631 632 return DMUB_STATUS_TIMEOUT; 633 } 634 635 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 636 uint32_t timeout_us) 637 { 638 uint32_t i = 0; 639 640 if (!dmub->hw_init) 641 return DMUB_STATUS_INVALID; 642 643 if (!dmub->hw_funcs.is_phy_init) 644 return DMUB_STATUS_OK; 645 646 for (i = 0; i <= timeout_us; i += 10) { 647 if (dmub->hw_funcs.is_phy_init(dmub)) 648 return DMUB_STATUS_OK; 649 650 udelay(10); 651 } 652 653 return DMUB_STATUS_TIMEOUT; 654 } 655 656 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 657 uint32_t timeout_us) 658 { 659 uint32_t i, rptr; 660 661 if (!dmub->hw_init) 662 return DMUB_STATUS_INVALID; 663 664 for (i = 0; i <= timeout_us; ++i) { 665 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 666 667 if (rptr > dmub->inbox1_rb.capacity) 668 return DMUB_STATUS_HW_FAILURE; 669 670 dmub->inbox1_rb.rptr = rptr; 671 672 if (dmub_rb_empty(&dmub->inbox1_rb)) 673 return DMUB_STATUS_OK; 674 675 udelay(1); 676 } 677 678 return DMUB_STATUS_TIMEOUT; 679 } 680 681 enum dmub_status 682 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 683 enum dmub_gpint_command command_code, 684 uint16_t param, uint32_t timeout_us) 685 { 686 union dmub_gpint_data_register reg; 687 uint32_t i; 688 689 if (!dmub->sw_init) 690 return DMUB_STATUS_INVALID; 691 692 if (!dmub->hw_funcs.set_gpint) 693 return DMUB_STATUS_INVALID; 694 695 if (!dmub->hw_funcs.is_gpint_acked) 696 return DMUB_STATUS_INVALID; 697 698 reg.bits.status = 1; 699 reg.bits.command_code = command_code; 700 reg.bits.param = param; 701 702 dmub->hw_funcs.set_gpint(dmub, reg); 703 704 for (i = 0; i < timeout_us; ++i) { 705 udelay(1); 706 707 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 708 return DMUB_STATUS_OK; 709 } 710 711 return DMUB_STATUS_TIMEOUT; 712 } 713 714 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 715 uint32_t *response) 716 { 717 *response = 0; 718 719 if (!dmub->sw_init) 720 return DMUB_STATUS_INVALID; 721 722 if (!dmub->hw_funcs.get_gpint_response) 723 return DMUB_STATUS_INVALID; 724 725 *response = dmub->hw_funcs.get_gpint_response(dmub); 726 727 return DMUB_STATUS_OK; 728 } 729 730 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 731 uint32_t *dataout) 732 { 733 *dataout = 0; 734 735 if (!dmub->sw_init) 736 return DMUB_STATUS_INVALID; 737 738 if (!dmub->hw_funcs.get_gpint_dataout) 739 return DMUB_STATUS_INVALID; 740 741 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 742 743 return DMUB_STATUS_OK; 744 } 745 746 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 747 union dmub_fw_boot_status *status) 748 { 749 status->all = 0; 750 751 if (!dmub->sw_init) 752 return DMUB_STATUS_INVALID; 753 754 if (dmub->hw_funcs.get_fw_status) 755 *status = dmub->hw_funcs.get_fw_status(dmub); 756 757 return DMUB_STATUS_OK; 758 } 759 760 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 761 union dmub_rb_cmd *cmd) 762 { 763 enum dmub_status status = DMUB_STATUS_OK; 764 765 // Queue command 766 status = dmub_srv_cmd_queue(dmub, cmd); 767 768 if (status != DMUB_STATUS_OK) 769 return status; 770 771 // Execute command 772 status = dmub_srv_cmd_execute(dmub); 773 774 if (status != DMUB_STATUS_OK) 775 return status; 776 777 // Wait for DMUB to process command 778 status = dmub_srv_wait_for_idle(dmub, 100000); 779 780 if (status != DMUB_STATUS_OK) 781 return status; 782 783 // Copy data back from ring buffer into command 784 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 785 786 return status; 787 } 788 789 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 790 void *entry) 791 { 792 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 793 uint64_t *dst = (uint64_t *)entry; 794 uint8_t i; 795 uint8_t loop_count; 796 797 if (rb->rptr == rb->wrpt) 798 return false; 799 800 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 801 // copying data 802 for (i = 0; i < loop_count; i++) 803 *dst++ = *src++; 804 805 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 806 807 rb->rptr %= rb->capacity; 808 809 return true; 810 } 811 812 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 813 { 814 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 815 816 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 817 } 818 819 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 820 { 821 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 822 return false; 823 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 824 return true; 825 } 826 827 bool dmub_srv_should_detect(struct dmub_srv *dmub) 828 { 829 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 830 return false; 831 832 return dmub->hw_funcs.should_detect(dmub); 833 } 834