1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "os_types.h" 34 /* 35 * Note: the DMUB service is standalone. No additional headers should be 36 * added below or above this line unless they reside within the DMUB 37 * folder. 38 */ 39 40 /* Alignment for framebuffer memory. */ 41 #define DMUB_FB_ALIGNMENT (1024 * 1024) 42 43 /* Stack size. */ 44 #define DMUB_STACK_SIZE (128 * 1024) 45 46 /* Context size. */ 47 #define DMUB_CONTEXT_SIZE (512 * 1024) 48 49 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 50 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 51 52 /* Default state size if meta is absent. */ 53 #define DMUB_FW_STATE_SIZE (64 * 1024) 54 55 /* Default tracebuffer size if meta is absent. */ 56 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 57 58 59 /* Default scratch mem size. */ 60 #define DMUB_SCRATCH_MEM_SIZE (256) 61 62 /* Number of windows in use. */ 63 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 64 /* Base addresses. */ 65 66 #define DMUB_CW0_BASE (0x60000000) 67 #define DMUB_CW1_BASE (0x61000000) 68 #define DMUB_CW3_BASE (0x63000000) 69 #define DMUB_CW4_BASE (0x64000000) 70 #define DMUB_CW5_BASE (0x65000000) 71 #define DMUB_CW6_BASE (0x66000000) 72 73 #define DMUB_REGION5_BASE (0xA0000000) 74 75 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 76 { 77 return (val + factor - 1) / factor * factor; 78 } 79 80 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 81 { 82 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 83 uint8_t buf[64]; 84 uint32_t pos, end; 85 86 /** 87 * Read 64-byte chunks since we don't want to store a 88 * large temporary buffer for this purpose. 89 */ 90 end = fb->size / sizeof(buf) * sizeof(buf); 91 92 for (pos = 0; pos < end; pos += sizeof(buf)) 93 dmub_memcpy(buf, base + pos, sizeof(buf)); 94 95 /* Read anything leftover into the buffer. */ 96 if (end < fb->size) 97 dmub_memcpy(buf, base + pos, fb->size - end); 98 } 99 100 static const struct dmub_fw_meta_info * 101 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 102 { 103 const union dmub_fw_meta *meta; 104 const uint8_t *blob = NULL; 105 uint32_t blob_size = 0; 106 uint32_t meta_offset = 0; 107 108 if (params->fw_bss_data && params->bss_data_size) { 109 /* Legacy metadata region. */ 110 blob = params->fw_bss_data; 111 blob_size = params->bss_data_size; 112 meta_offset = DMUB_FW_META_OFFSET; 113 } else if (params->fw_inst_const && params->inst_const_size) { 114 /* Combined metadata region. */ 115 blob = params->fw_inst_const; 116 blob_size = params->inst_const_size; 117 meta_offset = 0; 118 } 119 120 if (!blob || !blob_size) 121 return NULL; 122 123 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 124 return NULL; 125 126 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 127 sizeof(union dmub_fw_meta)); 128 129 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 130 return NULL; 131 132 return &meta->info; 133 } 134 135 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 136 { 137 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 138 139 switch (asic) { 140 case DMUB_ASIC_DCN20: 141 case DMUB_ASIC_DCN21: 142 case DMUB_ASIC_DCN30: 143 case DMUB_ASIC_DCN301: 144 case DMUB_ASIC_DCN302: 145 dmub->regs = &dmub_srv_dcn20_regs; 146 147 funcs->reset = dmub_dcn20_reset; 148 funcs->reset_release = dmub_dcn20_reset_release; 149 funcs->backdoor_load = dmub_dcn20_backdoor_load; 150 funcs->setup_windows = dmub_dcn20_setup_windows; 151 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 152 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 153 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 154 funcs->is_supported = dmub_dcn20_is_supported; 155 funcs->is_hw_init = dmub_dcn20_is_hw_init; 156 funcs->set_gpint = dmub_dcn20_set_gpint; 157 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 158 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 159 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 160 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 161 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 162 163 // Out mailbox register access functions for RN and above 164 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 165 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 166 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 167 168 //outbox0 call stacks 169 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 170 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 171 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 172 173 if (asic == DMUB_ASIC_DCN21) { 174 dmub->regs = &dmub_srv_dcn21_regs; 175 176 funcs->is_phy_init = dmub_dcn21_is_phy_init; 177 } 178 if (asic == DMUB_ASIC_DCN30) { 179 dmub->regs = &dmub_srv_dcn30_regs; 180 181 funcs->backdoor_load = dmub_dcn30_backdoor_load; 182 funcs->setup_windows = dmub_dcn30_setup_windows; 183 } 184 if (asic == DMUB_ASIC_DCN301) { 185 dmub->regs = &dmub_srv_dcn301_regs; 186 187 funcs->backdoor_load = dmub_dcn30_backdoor_load; 188 funcs->setup_windows = dmub_dcn30_setup_windows; 189 } 190 if (asic == DMUB_ASIC_DCN302) { 191 dmub->regs = &dmub_srv_dcn302_regs; 192 193 funcs->backdoor_load = dmub_dcn30_backdoor_load; 194 funcs->setup_windows = dmub_dcn30_setup_windows; 195 } 196 break; 197 198 default: 199 return false; 200 } 201 202 return true; 203 } 204 205 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 206 const struct dmub_srv_create_params *params) 207 { 208 enum dmub_status status = DMUB_STATUS_OK; 209 210 dmub_memset(dmub, 0, sizeof(*dmub)); 211 212 dmub->funcs = params->funcs; 213 dmub->user_ctx = params->user_ctx; 214 dmub->asic = params->asic; 215 dmub->fw_version = params->fw_version; 216 dmub->is_virtual = params->is_virtual; 217 218 /* Setup asic dependent hardware funcs. */ 219 if (!dmub_srv_hw_setup(dmub, params->asic)) { 220 status = DMUB_STATUS_INVALID; 221 goto cleanup; 222 } 223 224 /* Override (some) hardware funcs based on user params. */ 225 if (params->hw_funcs) { 226 if (params->hw_funcs->emul_get_inbox1_rptr) 227 dmub->hw_funcs.emul_get_inbox1_rptr = 228 params->hw_funcs->emul_get_inbox1_rptr; 229 230 if (params->hw_funcs->emul_set_inbox1_wptr) 231 dmub->hw_funcs.emul_set_inbox1_wptr = 232 params->hw_funcs->emul_set_inbox1_wptr; 233 234 if (params->hw_funcs->is_supported) 235 dmub->hw_funcs.is_supported = 236 params->hw_funcs->is_supported; 237 } 238 239 /* Sanity checks for required hw func pointers. */ 240 if (!dmub->hw_funcs.get_inbox1_rptr || 241 !dmub->hw_funcs.set_inbox1_wptr) { 242 status = DMUB_STATUS_INVALID; 243 goto cleanup; 244 } 245 246 cleanup: 247 if (status == DMUB_STATUS_OK) 248 dmub->sw_init = true; 249 else 250 dmub_srv_destroy(dmub); 251 252 return status; 253 } 254 255 void dmub_srv_destroy(struct dmub_srv *dmub) 256 { 257 dmub_memset(dmub, 0, sizeof(*dmub)); 258 } 259 260 enum dmub_status 261 dmub_srv_calc_region_info(struct dmub_srv *dmub, 262 const struct dmub_srv_region_params *params, 263 struct dmub_srv_region_info *out) 264 { 265 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 266 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 267 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 268 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 269 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 270 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 271 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 272 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 273 const struct dmub_fw_meta_info *fw_info; 274 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 275 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 276 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 277 278 if (!dmub->sw_init) 279 return DMUB_STATUS_INVALID; 280 281 memset(out, 0, sizeof(*out)); 282 283 out->num_regions = DMUB_NUM_WINDOWS; 284 285 inst->base = 0x0; 286 inst->top = inst->base + params->inst_const_size; 287 288 data->base = dmub_align(inst->top, 256); 289 data->top = data->base + params->bss_data_size; 290 291 /* 292 * All cache windows below should be aligned to the size 293 * of the DMCUB cache line, 64 bytes. 294 */ 295 296 stack->base = dmub_align(data->top, 256); 297 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 298 299 bios->base = dmub_align(stack->top, 256); 300 bios->top = bios->base + params->vbios_size; 301 302 mail->base = dmub_align(bios->top, 256); 303 mail->top = mail->base + DMUB_MAILBOX_SIZE; 304 305 fw_info = dmub_get_fw_meta_info(params); 306 307 if (fw_info) { 308 fw_state_size = fw_info->fw_region_size; 309 trace_buffer_size = fw_info->trace_buffer_size; 310 311 /** 312 * If DM didn't fill in a version, then fill it in based on 313 * the firmware meta now that we have it. 314 * 315 * TODO: Make it easier for driver to extract this out to 316 * pass during creation. 317 */ 318 if (dmub->fw_version == 0) 319 dmub->fw_version = fw_info->fw_version; 320 } 321 322 trace_buff->base = dmub_align(mail->top, 256); 323 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 324 325 fw_state->base = dmub_align(trace_buff->top, 256); 326 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 327 328 scratch_mem->base = dmub_align(fw_state->top, 256); 329 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 330 331 out->fb_size = dmub_align(scratch_mem->top, 4096); 332 333 return DMUB_STATUS_OK; 334 } 335 336 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 337 const struct dmub_srv_fb_params *params, 338 struct dmub_srv_fb_info *out) 339 { 340 uint8_t *cpu_base; 341 uint64_t gpu_base; 342 uint32_t i; 343 344 if (!dmub->sw_init) 345 return DMUB_STATUS_INVALID; 346 347 memset(out, 0, sizeof(*out)); 348 349 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 350 return DMUB_STATUS_INVALID; 351 352 cpu_base = (uint8_t *)params->cpu_addr; 353 gpu_base = params->gpu_addr; 354 355 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 356 const struct dmub_region *reg = 357 ¶ms->region_info->regions[i]; 358 359 out->fb[i].cpu_addr = cpu_base + reg->base; 360 out->fb[i].gpu_addr = gpu_base + reg->base; 361 out->fb[i].size = reg->top - reg->base; 362 } 363 364 out->num_fb = DMUB_NUM_WINDOWS; 365 366 return DMUB_STATUS_OK; 367 } 368 369 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 370 bool *is_supported) 371 { 372 *is_supported = false; 373 374 if (!dmub->sw_init) 375 return DMUB_STATUS_INVALID; 376 377 if (dmub->hw_funcs.is_supported) 378 *is_supported = dmub->hw_funcs.is_supported(dmub); 379 380 return DMUB_STATUS_OK; 381 } 382 383 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 384 { 385 *is_hw_init = false; 386 387 if (!dmub->sw_init) 388 return DMUB_STATUS_INVALID; 389 390 if (!dmub->hw_init) 391 return DMUB_STATUS_OK; 392 393 if (dmub->hw_funcs.is_hw_init) 394 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 395 396 return DMUB_STATUS_OK; 397 } 398 399 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 400 const struct dmub_srv_hw_params *params) 401 { 402 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 403 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 404 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 405 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 406 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 407 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 408 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 409 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 410 411 struct dmub_rb_init_params rb_params, outbox0_rb_params; 412 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 413 struct dmub_region inbox1, outbox1, outbox0; 414 415 if (!dmub->sw_init) 416 return DMUB_STATUS_INVALID; 417 418 dmub->fb_base = params->fb_base; 419 dmub->fb_offset = params->fb_offset; 420 dmub->psp_version = params->psp_version; 421 422 if (dmub->hw_funcs.reset) 423 dmub->hw_funcs.reset(dmub); 424 425 if (inst_fb && data_fb) { 426 cw0.offset.quad_part = inst_fb->gpu_addr; 427 cw0.region.base = DMUB_CW0_BASE; 428 cw0.region.top = cw0.region.base + inst_fb->size - 1; 429 430 cw1.offset.quad_part = stack_fb->gpu_addr; 431 cw1.region.base = DMUB_CW1_BASE; 432 cw1.region.top = cw1.region.base + stack_fb->size - 1; 433 434 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 435 /** 436 * Read back all the instruction memory so we don't hang the 437 * DMCUB when backdoor loading if the write from x86 hasn't been 438 * flushed yet. This only occurs in backdoor loading. 439 */ 440 dmub_flush_buffer_mem(inst_fb); 441 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 442 } 443 444 } 445 446 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 447 fw_state_fb && scratch_mem_fb) { 448 cw2.offset.quad_part = data_fb->gpu_addr; 449 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 450 cw2.region.top = cw2.region.base + data_fb->size; 451 452 cw3.offset.quad_part = bios_fb->gpu_addr; 453 cw3.region.base = DMUB_CW3_BASE; 454 cw3.region.top = cw3.region.base + bios_fb->size; 455 456 cw4.offset.quad_part = mail_fb->gpu_addr; 457 cw4.region.base = DMUB_CW4_BASE; 458 cw4.region.top = cw4.region.base + mail_fb->size; 459 460 /** 461 * Doubled the mailbox region to accomodate inbox and outbox. 462 * Note: Currently, currently total mailbox size is 16KB. It is split 463 * equally into 8KB between inbox and outbox. If this config is 464 * changed, then uncached base address configuration of outbox1 465 * has to be updated in funcs->setup_out_mailbox. 466 */ 467 inbox1.base = cw4.region.base; 468 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 469 outbox1.base = inbox1.top; 470 outbox1.top = cw4.region.top; 471 472 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 473 cw5.region.base = DMUB_CW5_BASE; 474 cw5.region.top = cw5.region.base + tracebuff_fb->size; 475 476 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 477 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 478 479 480 cw6.offset.quad_part = fw_state_fb->gpu_addr; 481 cw6.region.base = DMUB_CW6_BASE; 482 cw6.region.top = cw6.region.base + fw_state_fb->size; 483 484 dmub->fw_state = fw_state_fb->cpu_addr; 485 486 dmub->scratch_mem_fb = *scratch_mem_fb; 487 488 if (dmub->hw_funcs.setup_windows) 489 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 490 &cw5, &cw6); 491 492 if (dmub->hw_funcs.setup_outbox0) 493 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 494 495 if (dmub->hw_funcs.setup_mailbox) 496 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 497 if (dmub->hw_funcs.setup_out_mailbox) 498 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 499 } 500 501 if (mail_fb) { 502 dmub_memset(&rb_params, 0, sizeof(rb_params)); 503 rb_params.ctx = dmub; 504 rb_params.base_address = mail_fb->cpu_addr; 505 rb_params.capacity = DMUB_RB_SIZE; 506 507 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 508 509 // Initialize outbox1 ring buffer 510 rb_params.ctx = dmub; 511 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 512 rb_params.capacity = DMUB_RB_SIZE; 513 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 514 515 } 516 517 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 518 outbox0_rb_params.ctx = dmub; 519 outbox0_rb_params.base_address = (void *)((uint64_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 520 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 521 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 522 523 if (dmub->hw_funcs.reset_release) 524 dmub->hw_funcs.reset_release(dmub); 525 526 dmub->hw_init = true; 527 528 return DMUB_STATUS_OK; 529 } 530 531 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 532 { 533 if (!dmub->sw_init) 534 return DMUB_STATUS_INVALID; 535 536 if (dmub->hw_funcs.reset) 537 dmub->hw_funcs.reset(dmub); 538 539 dmub->hw_init = false; 540 541 return DMUB_STATUS_OK; 542 } 543 544 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 545 const union dmub_rb_cmd *cmd) 546 { 547 if (!dmub->hw_init) 548 return DMUB_STATUS_INVALID; 549 550 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 551 return DMUB_STATUS_OK; 552 553 return DMUB_STATUS_QUEUE_FULL; 554 } 555 556 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 557 { 558 if (!dmub->hw_init) 559 return DMUB_STATUS_INVALID; 560 561 /** 562 * Read back all the queued commands to ensure that they've 563 * been flushed to framebuffer memory. Otherwise DMCUB might 564 * read back stale, fully invalid or partially invalid data. 565 */ 566 dmub_rb_flush_pending(&dmub->inbox1_rb); 567 568 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 569 return DMUB_STATUS_OK; 570 } 571 572 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 573 uint32_t timeout_us) 574 { 575 uint32_t i; 576 577 if (!dmub->hw_init) 578 return DMUB_STATUS_INVALID; 579 580 for (i = 0; i <= timeout_us; i += 100) { 581 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 582 583 if (status.bits.dal_fw && status.bits.mailbox_rdy) 584 return DMUB_STATUS_OK; 585 586 udelay(100); 587 } 588 589 return DMUB_STATUS_TIMEOUT; 590 } 591 592 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 593 uint32_t timeout_us) 594 { 595 uint32_t i = 0; 596 597 if (!dmub->hw_init) 598 return DMUB_STATUS_INVALID; 599 600 if (!dmub->hw_funcs.is_phy_init) 601 return DMUB_STATUS_OK; 602 603 for (i = 0; i <= timeout_us; i += 10) { 604 if (dmub->hw_funcs.is_phy_init(dmub)) 605 return DMUB_STATUS_OK; 606 607 udelay(10); 608 } 609 610 return DMUB_STATUS_TIMEOUT; 611 } 612 613 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 614 uint32_t timeout_us) 615 { 616 uint32_t i; 617 618 if (!dmub->hw_init) 619 return DMUB_STATUS_INVALID; 620 621 for (i = 0; i <= timeout_us; ++i) { 622 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 623 if (dmub_rb_empty(&dmub->inbox1_rb)) 624 return DMUB_STATUS_OK; 625 626 udelay(1); 627 } 628 629 return DMUB_STATUS_TIMEOUT; 630 } 631 632 enum dmub_status 633 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 634 enum dmub_gpint_command command_code, 635 uint16_t param, uint32_t timeout_us) 636 { 637 union dmub_gpint_data_register reg; 638 uint32_t i; 639 640 if (!dmub->sw_init) 641 return DMUB_STATUS_INVALID; 642 643 if (!dmub->hw_funcs.set_gpint) 644 return DMUB_STATUS_INVALID; 645 646 if (!dmub->hw_funcs.is_gpint_acked) 647 return DMUB_STATUS_INVALID; 648 649 reg.bits.status = 1; 650 reg.bits.command_code = command_code; 651 reg.bits.param = param; 652 653 dmub->hw_funcs.set_gpint(dmub, reg); 654 655 for (i = 0; i < timeout_us; ++i) { 656 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 657 return DMUB_STATUS_OK; 658 } 659 660 return DMUB_STATUS_TIMEOUT; 661 } 662 663 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 664 uint32_t *response) 665 { 666 *response = 0; 667 668 if (!dmub->sw_init) 669 return DMUB_STATUS_INVALID; 670 671 if (!dmub->hw_funcs.get_gpint_response) 672 return DMUB_STATUS_INVALID; 673 674 *response = dmub->hw_funcs.get_gpint_response(dmub); 675 676 return DMUB_STATUS_OK; 677 } 678 679 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 680 union dmub_fw_boot_status *status) 681 { 682 status->all = 0; 683 684 if (!dmub->sw_init) 685 return DMUB_STATUS_INVALID; 686 687 if (dmub->hw_funcs.get_fw_status) 688 *status = dmub->hw_funcs.get_fw_status(dmub); 689 690 return DMUB_STATUS_OK; 691 } 692 693 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 694 union dmub_rb_cmd *cmd) 695 { 696 enum dmub_status status = DMUB_STATUS_OK; 697 698 // Queue command 699 status = dmub_srv_cmd_queue(dmub, cmd); 700 701 if (status != DMUB_STATUS_OK) 702 return status; 703 704 // Execute command 705 status = dmub_srv_cmd_execute(dmub); 706 707 if (status != DMUB_STATUS_OK) 708 return status; 709 710 // Wait for DMUB to process command 711 status = dmub_srv_wait_for_idle(dmub, 100000); 712 713 if (status != DMUB_STATUS_OK) 714 return status; 715 716 // Copy data back from ring buffer into command 717 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 718 719 return status; 720 } 721 722 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 723 void *entry) 724 { 725 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 726 uint64_t *dst = (uint64_t *)entry; 727 uint8_t i; 728 uint8_t loop_count; 729 730 if (rb->rptr == rb->wrpt) 731 return false; 732 733 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 734 // copying data 735 for (i = 0; i < loop_count; i++) 736 *dst++ = *src++; 737 738 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 739 740 rb->rptr %= rb->capacity; 741 742 return true; 743 } 744 745 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 746 { 747 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 748 749 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 750 } 751