1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../inc/dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_fw_meta.h" 30 #include "os_types.h" 31 /* 32 * Note: the DMUB service is standalone. No additional headers should be 33 * added below or above this line unless they reside within the DMUB 34 * folder. 35 */ 36 37 /* Alignment for framebuffer memory. */ 38 #define DMUB_FB_ALIGNMENT (1024 * 1024) 39 40 /* Stack size. */ 41 #define DMUB_STACK_SIZE (128 * 1024) 42 43 /* Context size. */ 44 #define DMUB_CONTEXT_SIZE (512 * 1024) 45 46 /* Mailbox size */ 47 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 48 49 /* Default state size if meta is absent. */ 50 #define DMUB_FW_STATE_SIZE (1024) 51 52 /* Default tracebuffer size if meta is absent. */ 53 #define DMUB_TRACE_BUFFER_SIZE (1024) 54 55 /* Default scratch mem size. */ 56 #define DMUB_SCRATCH_MEM_SIZE (256) 57 58 /* Number of windows in use. */ 59 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 60 /* Base addresses. */ 61 62 #define DMUB_CW0_BASE (0x60000000) 63 #define DMUB_CW1_BASE (0x61000000) 64 #define DMUB_CW3_BASE (0x63000000) 65 #define DMUB_CW5_BASE (0x65000000) 66 #define DMUB_CW6_BASE (0x66000000) 67 68 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 69 { 70 return (val + factor - 1) / factor * factor; 71 } 72 73 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 74 { 75 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 76 uint8_t buf[64]; 77 uint32_t pos, end; 78 79 /** 80 * Read 64-byte chunks since we don't want to store a 81 * large temporary buffer for this purpose. 82 */ 83 end = fb->size / sizeof(buf) * sizeof(buf); 84 85 for (pos = 0; pos < end; pos += sizeof(buf)) 86 dmub_memcpy(buf, base + pos, sizeof(buf)); 87 88 /* Read anything leftover into the buffer. */ 89 if (end < fb->size) 90 dmub_memcpy(buf, base + pos, fb->size - end); 91 } 92 93 static const struct dmub_fw_meta_info * 94 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 95 { 96 const union dmub_fw_meta *meta; 97 const uint8_t *blob = NULL; 98 uint32_t blob_size = 0; 99 100 if (params->fw_bss_data) { 101 /* Legacy metadata region. */ 102 blob = params->fw_bss_data; 103 blob_size = params->bss_data_size; 104 } else if (params->fw_inst_const) { 105 /* Combined metadata region. */ 106 blob = params->fw_inst_const; 107 blob_size = params->inst_const_size; 108 } 109 110 if (!blob || !blob_size) 111 return NULL; 112 113 if (blob_size < sizeof(union dmub_fw_meta) + DMUB_FW_META_OFFSET) 114 return NULL; 115 116 meta = (const union dmub_fw_meta *)(blob + blob_size - 117 DMUB_FW_META_OFFSET - 118 sizeof(union dmub_fw_meta)); 119 120 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 121 return NULL; 122 123 return &meta->info; 124 } 125 126 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 127 { 128 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 129 130 switch (asic) { 131 case DMUB_ASIC_DCN20: 132 case DMUB_ASIC_DCN21: 133 dmub->regs = &dmub_srv_dcn20_regs; 134 135 funcs->reset = dmub_dcn20_reset; 136 funcs->reset_release = dmub_dcn20_reset_release; 137 funcs->backdoor_load = dmub_dcn20_backdoor_load; 138 funcs->setup_windows = dmub_dcn20_setup_windows; 139 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 140 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 141 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 142 funcs->is_supported = dmub_dcn20_is_supported; 143 funcs->is_hw_init = dmub_dcn20_is_hw_init; 144 funcs->set_gpint = dmub_dcn20_set_gpint; 145 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 146 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 147 148 if (asic == DMUB_ASIC_DCN21) { 149 dmub->regs = &dmub_srv_dcn21_regs; 150 151 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 152 funcs->is_phy_init = dmub_dcn21_is_phy_init; 153 } 154 break; 155 156 default: 157 return false; 158 } 159 160 return true; 161 } 162 163 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 164 const struct dmub_srv_create_params *params) 165 { 166 enum dmub_status status = DMUB_STATUS_OK; 167 168 dmub_memset(dmub, 0, sizeof(*dmub)); 169 170 dmub->funcs = params->funcs; 171 dmub->user_ctx = params->user_ctx; 172 dmub->asic = params->asic; 173 dmub->is_virtual = params->is_virtual; 174 175 /* Setup asic dependent hardware funcs. */ 176 if (!dmub_srv_hw_setup(dmub, params->asic)) { 177 status = DMUB_STATUS_INVALID; 178 goto cleanup; 179 } 180 181 /* Override (some) hardware funcs based on user params. */ 182 if (params->hw_funcs) { 183 if (params->hw_funcs->get_inbox1_rptr) 184 dmub->hw_funcs.get_inbox1_rptr = 185 params->hw_funcs->get_inbox1_rptr; 186 187 if (params->hw_funcs->set_inbox1_wptr) 188 dmub->hw_funcs.set_inbox1_wptr = 189 params->hw_funcs->set_inbox1_wptr; 190 191 if (params->hw_funcs->is_supported) 192 dmub->hw_funcs.is_supported = 193 params->hw_funcs->is_supported; 194 } 195 196 /* Sanity checks for required hw func pointers. */ 197 if (!dmub->hw_funcs.get_inbox1_rptr || 198 !dmub->hw_funcs.set_inbox1_wptr) { 199 status = DMUB_STATUS_INVALID; 200 goto cleanup; 201 } 202 203 cleanup: 204 if (status == DMUB_STATUS_OK) 205 dmub->sw_init = true; 206 else 207 dmub_srv_destroy(dmub); 208 209 return status; 210 } 211 212 void dmub_srv_destroy(struct dmub_srv *dmub) 213 { 214 dmub_memset(dmub, 0, sizeof(*dmub)); 215 } 216 217 enum dmub_status 218 dmub_srv_calc_region_info(struct dmub_srv *dmub, 219 const struct dmub_srv_region_params *params, 220 struct dmub_srv_region_info *out) 221 { 222 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 223 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 224 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 225 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 226 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 227 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 228 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 229 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 230 const struct dmub_fw_meta_info *fw_info; 231 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 232 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 233 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 234 235 if (!dmub->sw_init) 236 return DMUB_STATUS_INVALID; 237 238 memset(out, 0, sizeof(*out)); 239 240 out->num_regions = DMUB_NUM_WINDOWS; 241 242 inst->base = 0x0; 243 inst->top = inst->base + params->inst_const_size; 244 245 data->base = dmub_align(inst->top, 256); 246 data->top = data->base + params->bss_data_size; 247 248 /* 249 * All cache windows below should be aligned to the size 250 * of the DMCUB cache line, 64 bytes. 251 */ 252 253 stack->base = dmub_align(data->top, 256); 254 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 255 256 bios->base = dmub_align(stack->top, 256); 257 bios->top = bios->base + params->vbios_size; 258 259 mail->base = dmub_align(bios->top, 256); 260 mail->top = mail->base + DMUB_MAILBOX_SIZE; 261 262 fw_info = dmub_get_fw_meta_info(params); 263 264 if (fw_info) { 265 fw_state_size = fw_info->fw_region_size; 266 trace_buffer_size = fw_info->trace_buffer_size; 267 } 268 269 trace_buff->base = dmub_align(mail->top, 256); 270 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 271 272 fw_state->base = dmub_align(trace_buff->top, 256); 273 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 274 275 scratch_mem->base = dmub_align(fw_state->top, 256); 276 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 277 278 out->fb_size = dmub_align(scratch_mem->top, 4096); 279 280 return DMUB_STATUS_OK; 281 } 282 283 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 284 const struct dmub_srv_fb_params *params, 285 struct dmub_srv_fb_info *out) 286 { 287 uint8_t *cpu_base; 288 uint64_t gpu_base; 289 uint32_t i; 290 291 if (!dmub->sw_init) 292 return DMUB_STATUS_INVALID; 293 294 memset(out, 0, sizeof(*out)); 295 296 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 297 return DMUB_STATUS_INVALID; 298 299 cpu_base = (uint8_t *)params->cpu_addr; 300 gpu_base = params->gpu_addr; 301 302 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 303 const struct dmub_region *reg = 304 ¶ms->region_info->regions[i]; 305 306 out->fb[i].cpu_addr = cpu_base + reg->base; 307 out->fb[i].gpu_addr = gpu_base + reg->base; 308 out->fb[i].size = reg->top - reg->base; 309 } 310 311 out->num_fb = DMUB_NUM_WINDOWS; 312 313 return DMUB_STATUS_OK; 314 } 315 316 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 317 bool *is_supported) 318 { 319 *is_supported = false; 320 321 if (!dmub->sw_init) 322 return DMUB_STATUS_INVALID; 323 324 if (dmub->hw_funcs.is_supported) 325 *is_supported = dmub->hw_funcs.is_supported(dmub); 326 327 return DMUB_STATUS_OK; 328 } 329 330 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 331 { 332 *is_hw_init = false; 333 334 if (!dmub->sw_init) 335 return DMUB_STATUS_INVALID; 336 337 if (!dmub->hw_init) 338 return DMUB_STATUS_OK; 339 340 if (dmub->hw_funcs.is_hw_init) 341 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 342 343 return DMUB_STATUS_OK; 344 } 345 346 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 347 const struct dmub_srv_hw_params *params) 348 { 349 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 350 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 351 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 352 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 353 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 354 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 355 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 356 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 357 358 struct dmub_rb_init_params rb_params; 359 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 360 struct dmub_region inbox1; 361 362 if (!dmub->sw_init) 363 return DMUB_STATUS_INVALID; 364 365 dmub->fb_base = params->fb_base; 366 dmub->fb_offset = params->fb_offset; 367 dmub->psp_version = params->psp_version; 368 369 if (inst_fb && data_fb) { 370 cw0.offset.quad_part = inst_fb->gpu_addr; 371 cw0.region.base = DMUB_CW0_BASE; 372 cw0.region.top = cw0.region.base + inst_fb->size - 1; 373 374 cw1.offset.quad_part = stack_fb->gpu_addr; 375 cw1.region.base = DMUB_CW1_BASE; 376 cw1.region.top = cw1.region.base + stack_fb->size - 1; 377 378 /** 379 * Read back all the instruction memory so we don't hang the 380 * DMCUB when backdoor loading if the write from x86 hasn't been 381 * flushed yet. This only occurs in backdoor loading. 382 */ 383 dmub_flush_buffer_mem(inst_fb); 384 385 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) 386 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 387 } 388 389 if (dmub->hw_funcs.reset) 390 dmub->hw_funcs.reset(dmub); 391 392 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 393 fw_state_fb && scratch_mem_fb) { 394 cw2.offset.quad_part = data_fb->gpu_addr; 395 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 396 cw2.region.top = cw2.region.base + data_fb->size; 397 398 cw3.offset.quad_part = bios_fb->gpu_addr; 399 cw3.region.base = DMUB_CW3_BASE; 400 cw3.region.top = cw3.region.base + bios_fb->size; 401 402 cw4.offset.quad_part = mail_fb->gpu_addr; 403 cw4.region.base = cw3.region.top + 1; 404 cw4.region.top = cw4.region.base + mail_fb->size; 405 406 inbox1.base = cw4.region.base; 407 inbox1.top = cw4.region.top; 408 409 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 410 cw5.region.base = DMUB_CW5_BASE; 411 cw5.region.top = cw5.region.base + tracebuff_fb->size; 412 413 cw6.offset.quad_part = fw_state_fb->gpu_addr; 414 cw6.region.base = DMUB_CW6_BASE; 415 cw6.region.top = cw6.region.base + fw_state_fb->size; 416 417 dmub->fw_state = fw_state_fb->cpu_addr; 418 419 dmub->scratch_mem_fb = *scratch_mem_fb; 420 421 if (dmub->hw_funcs.setup_windows) 422 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 423 &cw5, &cw6); 424 425 if (dmub->hw_funcs.setup_mailbox) 426 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 427 } 428 429 if (mail_fb) { 430 dmub_memset(&rb_params, 0, sizeof(rb_params)); 431 rb_params.ctx = dmub; 432 rb_params.base_address = mail_fb->cpu_addr; 433 rb_params.capacity = DMUB_RB_SIZE; 434 435 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 436 } 437 438 if (dmub->hw_funcs.reset_release) 439 dmub->hw_funcs.reset_release(dmub); 440 441 dmub->hw_init = true; 442 443 return DMUB_STATUS_OK; 444 } 445 446 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 447 { 448 if (!dmub->sw_init) 449 return DMUB_STATUS_INVALID; 450 451 if (dmub->hw_init == false) 452 return DMUB_STATUS_OK; 453 454 if (dmub->hw_funcs.reset) 455 dmub->hw_funcs.reset(dmub); 456 457 dmub->hw_init = false; 458 459 return DMUB_STATUS_OK; 460 } 461 462 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 463 const struct dmub_cmd_header *cmd) 464 { 465 if (!dmub->hw_init) 466 return DMUB_STATUS_INVALID; 467 468 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 469 return DMUB_STATUS_OK; 470 471 return DMUB_STATUS_QUEUE_FULL; 472 } 473 474 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 475 { 476 if (!dmub->hw_init) 477 return DMUB_STATUS_INVALID; 478 479 /** 480 * Read back all the queued commands to ensure that they've 481 * been flushed to framebuffer memory. Otherwise DMCUB might 482 * read back stale, fully invalid or partially invalid data. 483 */ 484 dmub_rb_flush_pending(&dmub->inbox1_rb); 485 486 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 487 return DMUB_STATUS_OK; 488 } 489 490 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 491 uint32_t timeout_us) 492 { 493 uint32_t i; 494 495 if (!dmub->hw_init) 496 return DMUB_STATUS_INVALID; 497 498 if (!dmub->hw_funcs.is_auto_load_done) 499 return DMUB_STATUS_OK; 500 501 for (i = 0; i <= timeout_us; i += 100) { 502 if (dmub->hw_funcs.is_auto_load_done(dmub)) 503 return DMUB_STATUS_OK; 504 505 udelay(100); 506 } 507 508 return DMUB_STATUS_TIMEOUT; 509 } 510 511 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 512 uint32_t timeout_us) 513 { 514 uint32_t i = 0; 515 516 if (!dmub->hw_init) 517 return DMUB_STATUS_INVALID; 518 519 if (!dmub->hw_funcs.is_phy_init) 520 return DMUB_STATUS_OK; 521 522 for (i = 0; i <= timeout_us; i += 10) { 523 if (dmub->hw_funcs.is_phy_init(dmub)) 524 return DMUB_STATUS_OK; 525 526 udelay(10); 527 } 528 529 return DMUB_STATUS_TIMEOUT; 530 } 531 532 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 533 uint32_t timeout_us) 534 { 535 uint32_t i; 536 537 if (!dmub->hw_init) 538 return DMUB_STATUS_INVALID; 539 540 for (i = 0; i <= timeout_us; ++i) { 541 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 542 if (dmub_rb_empty(&dmub->inbox1_rb)) 543 return DMUB_STATUS_OK; 544 545 udelay(1); 546 } 547 548 return DMUB_STATUS_TIMEOUT; 549 } 550 551 enum dmub_status 552 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 553 enum dmub_gpint_command command_code, 554 uint16_t param, uint32_t timeout_us) 555 { 556 union dmub_gpint_data_register reg; 557 uint32_t i; 558 559 if (!dmub->sw_init) 560 return DMUB_STATUS_INVALID; 561 562 if (!dmub->hw_funcs.set_gpint) 563 return DMUB_STATUS_INVALID; 564 565 if (!dmub->hw_funcs.is_gpint_acked) 566 return DMUB_STATUS_INVALID; 567 568 reg.bits.status = 1; 569 reg.bits.command_code = command_code; 570 reg.bits.param = param; 571 572 dmub->hw_funcs.set_gpint(dmub, reg); 573 574 for (i = 0; i < timeout_us; ++i) { 575 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 576 return DMUB_STATUS_OK; 577 } 578 579 return DMUB_STATUS_TIMEOUT; 580 } 581 582 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 583 uint32_t *response) 584 { 585 *response = 0; 586 587 if (!dmub->sw_init) 588 return DMUB_STATUS_INVALID; 589 590 if (!dmub->hw_funcs.get_gpint_response) 591 return DMUB_STATUS_INVALID; 592 593 *response = dmub->hw_funcs.get_gpint_response(dmub); 594 595 return DMUB_STATUS_OK; 596 } 597