1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "os_types.h" 34 /* 35 * Note: the DMUB service is standalone. No additional headers should be 36 * added below or above this line unless they reside within the DMUB 37 * folder. 38 */ 39 40 /* Alignment for framebuffer memory. */ 41 #define DMUB_FB_ALIGNMENT (1024 * 1024) 42 43 /* Stack size. */ 44 #define DMUB_STACK_SIZE (128 * 1024) 45 46 /* Context size. */ 47 #define DMUB_CONTEXT_SIZE (512 * 1024) 48 49 /* Mailbox size */ 50 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 51 52 /* Default state size if meta is absent. */ 53 #define DMUB_FW_STATE_SIZE (64 * 1024) 54 55 /* Default tracebuffer size if meta is absent. */ 56 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 57 58 /* Default scratch mem size. */ 59 #define DMUB_SCRATCH_MEM_SIZE (256) 60 61 /* Number of windows in use. */ 62 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 63 /* Base addresses. */ 64 65 #define DMUB_CW0_BASE (0x60000000) 66 #define DMUB_CW1_BASE (0x61000000) 67 #define DMUB_CW3_BASE (0x63000000) 68 #define DMUB_CW4_BASE (0x64000000) 69 #define DMUB_CW5_BASE (0x65000000) 70 #define DMUB_CW6_BASE (0x66000000) 71 72 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 73 { 74 return (val + factor - 1) / factor * factor; 75 } 76 77 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 78 { 79 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 80 uint8_t buf[64]; 81 uint32_t pos, end; 82 83 /** 84 * Read 64-byte chunks since we don't want to store a 85 * large temporary buffer for this purpose. 86 */ 87 end = fb->size / sizeof(buf) * sizeof(buf); 88 89 for (pos = 0; pos < end; pos += sizeof(buf)) 90 dmub_memcpy(buf, base + pos, sizeof(buf)); 91 92 /* Read anything leftover into the buffer. */ 93 if (end < fb->size) 94 dmub_memcpy(buf, base + pos, fb->size - end); 95 } 96 97 static const struct dmub_fw_meta_info * 98 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 99 { 100 const union dmub_fw_meta *meta; 101 const uint8_t *blob = NULL; 102 uint32_t blob_size = 0; 103 uint32_t meta_offset = 0; 104 105 if (params->fw_bss_data && params->bss_data_size) { 106 /* Legacy metadata region. */ 107 blob = params->fw_bss_data; 108 blob_size = params->bss_data_size; 109 meta_offset = DMUB_FW_META_OFFSET; 110 } else if (params->fw_inst_const && params->inst_const_size) { 111 /* Combined metadata region. */ 112 blob = params->fw_inst_const; 113 blob_size = params->inst_const_size; 114 meta_offset = 0; 115 } 116 117 if (!blob || !blob_size) 118 return NULL; 119 120 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 121 return NULL; 122 123 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 124 sizeof(union dmub_fw_meta)); 125 126 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 127 return NULL; 128 129 return &meta->info; 130 } 131 132 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 133 { 134 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 135 136 switch (asic) { 137 case DMUB_ASIC_DCN20: 138 case DMUB_ASIC_DCN21: 139 case DMUB_ASIC_DCN30: 140 case DMUB_ASIC_DCN301: 141 case DMUB_ASIC_DCN302: 142 dmub->regs = &dmub_srv_dcn20_regs; 143 144 funcs->reset = dmub_dcn20_reset; 145 funcs->reset_release = dmub_dcn20_reset_release; 146 funcs->backdoor_load = dmub_dcn20_backdoor_load; 147 funcs->setup_windows = dmub_dcn20_setup_windows; 148 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 149 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 150 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 151 funcs->is_supported = dmub_dcn20_is_supported; 152 funcs->is_hw_init = dmub_dcn20_is_hw_init; 153 funcs->set_gpint = dmub_dcn20_set_gpint; 154 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 155 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 156 157 if (asic == DMUB_ASIC_DCN21) { 158 dmub->regs = &dmub_srv_dcn21_regs; 159 160 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 161 funcs->is_phy_init = dmub_dcn21_is_phy_init; 162 } 163 if (asic == DMUB_ASIC_DCN30) { 164 dmub->regs = &dmub_srv_dcn30_regs; 165 166 funcs->is_auto_load_done = dmub_dcn30_is_auto_load_done; 167 funcs->backdoor_load = dmub_dcn30_backdoor_load; 168 funcs->setup_windows = dmub_dcn30_setup_windows; 169 } 170 if (asic == DMUB_ASIC_DCN301) { 171 dmub->regs = &dmub_srv_dcn301_regs; 172 173 funcs->backdoor_load = dmub_dcn30_backdoor_load; 174 funcs->setup_windows = dmub_dcn30_setup_windows; 175 } 176 if (asic == DMUB_ASIC_DCN302) { 177 dmub->regs = &dmub_srv_dcn302_regs; 178 179 funcs->backdoor_load = dmub_dcn30_backdoor_load; 180 funcs->setup_windows = dmub_dcn30_setup_windows; 181 } 182 break; 183 184 default: 185 return false; 186 } 187 188 return true; 189 } 190 191 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 192 const struct dmub_srv_create_params *params) 193 { 194 enum dmub_status status = DMUB_STATUS_OK; 195 196 dmub_memset(dmub, 0, sizeof(*dmub)); 197 198 dmub->funcs = params->funcs; 199 dmub->user_ctx = params->user_ctx; 200 dmub->asic = params->asic; 201 dmub->fw_version = params->fw_version; 202 dmub->is_virtual = params->is_virtual; 203 204 /* Setup asic dependent hardware funcs. */ 205 if (!dmub_srv_hw_setup(dmub, params->asic)) { 206 status = DMUB_STATUS_INVALID; 207 goto cleanup; 208 } 209 210 /* Override (some) hardware funcs based on user params. */ 211 if (params->hw_funcs) { 212 if (params->hw_funcs->emul_get_inbox1_rptr) 213 dmub->hw_funcs.emul_get_inbox1_rptr = 214 params->hw_funcs->emul_get_inbox1_rptr; 215 216 if (params->hw_funcs->emul_set_inbox1_wptr) 217 dmub->hw_funcs.emul_set_inbox1_wptr = 218 params->hw_funcs->emul_set_inbox1_wptr; 219 220 if (params->hw_funcs->is_supported) 221 dmub->hw_funcs.is_supported = 222 params->hw_funcs->is_supported; 223 } 224 225 /* Sanity checks for required hw func pointers. */ 226 if (!dmub->hw_funcs.get_inbox1_rptr || 227 !dmub->hw_funcs.set_inbox1_wptr) { 228 status = DMUB_STATUS_INVALID; 229 goto cleanup; 230 } 231 232 cleanup: 233 if (status == DMUB_STATUS_OK) 234 dmub->sw_init = true; 235 else 236 dmub_srv_destroy(dmub); 237 238 return status; 239 } 240 241 void dmub_srv_destroy(struct dmub_srv *dmub) 242 { 243 dmub_memset(dmub, 0, sizeof(*dmub)); 244 } 245 246 enum dmub_status 247 dmub_srv_calc_region_info(struct dmub_srv *dmub, 248 const struct dmub_srv_region_params *params, 249 struct dmub_srv_region_info *out) 250 { 251 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 252 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 253 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 254 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 255 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 256 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 257 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 258 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 259 const struct dmub_fw_meta_info *fw_info; 260 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 261 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 262 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 263 264 if (!dmub->sw_init) 265 return DMUB_STATUS_INVALID; 266 267 memset(out, 0, sizeof(*out)); 268 269 out->num_regions = DMUB_NUM_WINDOWS; 270 271 inst->base = 0x0; 272 inst->top = inst->base + params->inst_const_size; 273 274 data->base = dmub_align(inst->top, 256); 275 data->top = data->base + params->bss_data_size; 276 277 /* 278 * All cache windows below should be aligned to the size 279 * of the DMCUB cache line, 64 bytes. 280 */ 281 282 stack->base = dmub_align(data->top, 256); 283 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 284 285 bios->base = dmub_align(stack->top, 256); 286 bios->top = bios->base + params->vbios_size; 287 288 mail->base = dmub_align(bios->top, 256); 289 mail->top = mail->base + DMUB_MAILBOX_SIZE; 290 291 fw_info = dmub_get_fw_meta_info(params); 292 293 if (fw_info) { 294 fw_state_size = fw_info->fw_region_size; 295 trace_buffer_size = fw_info->trace_buffer_size; 296 297 /** 298 * If DM didn't fill in a version, then fill it in based on 299 * the firmware meta now that we have it. 300 * 301 * TODO: Make it easier for driver to extract this out to 302 * pass during creation. 303 */ 304 if (dmub->fw_version == 0) 305 dmub->fw_version = fw_info->fw_version; 306 } 307 308 trace_buff->base = dmub_align(mail->top, 256); 309 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 310 311 fw_state->base = dmub_align(trace_buff->top, 256); 312 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 313 314 scratch_mem->base = dmub_align(fw_state->top, 256); 315 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 316 317 out->fb_size = dmub_align(scratch_mem->top, 4096); 318 319 return DMUB_STATUS_OK; 320 } 321 322 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 323 const struct dmub_srv_fb_params *params, 324 struct dmub_srv_fb_info *out) 325 { 326 uint8_t *cpu_base; 327 uint64_t gpu_base; 328 uint32_t i; 329 330 if (!dmub->sw_init) 331 return DMUB_STATUS_INVALID; 332 333 memset(out, 0, sizeof(*out)); 334 335 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 336 return DMUB_STATUS_INVALID; 337 338 cpu_base = (uint8_t *)params->cpu_addr; 339 gpu_base = params->gpu_addr; 340 341 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 342 const struct dmub_region *reg = 343 ¶ms->region_info->regions[i]; 344 345 out->fb[i].cpu_addr = cpu_base + reg->base; 346 out->fb[i].gpu_addr = gpu_base + reg->base; 347 out->fb[i].size = reg->top - reg->base; 348 } 349 350 out->num_fb = DMUB_NUM_WINDOWS; 351 352 return DMUB_STATUS_OK; 353 } 354 355 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 356 bool *is_supported) 357 { 358 *is_supported = false; 359 360 if (!dmub->sw_init) 361 return DMUB_STATUS_INVALID; 362 363 if (dmub->hw_funcs.is_supported) 364 *is_supported = dmub->hw_funcs.is_supported(dmub); 365 366 return DMUB_STATUS_OK; 367 } 368 369 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 370 { 371 *is_hw_init = false; 372 373 if (!dmub->sw_init) 374 return DMUB_STATUS_INVALID; 375 376 if (!dmub->hw_init) 377 return DMUB_STATUS_OK; 378 379 if (dmub->hw_funcs.is_hw_init) 380 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 381 382 return DMUB_STATUS_OK; 383 } 384 385 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 386 const struct dmub_srv_hw_params *params) 387 { 388 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 389 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 390 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 391 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 392 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 393 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 394 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 395 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 396 397 struct dmub_rb_init_params rb_params; 398 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 399 struct dmub_region inbox1; 400 401 if (!dmub->sw_init) 402 return DMUB_STATUS_INVALID; 403 404 dmub->fb_base = params->fb_base; 405 dmub->fb_offset = params->fb_offset; 406 dmub->psp_version = params->psp_version; 407 408 if (inst_fb && data_fb) { 409 cw0.offset.quad_part = inst_fb->gpu_addr; 410 cw0.region.base = DMUB_CW0_BASE; 411 cw0.region.top = cw0.region.base + inst_fb->size - 1; 412 413 cw1.offset.quad_part = stack_fb->gpu_addr; 414 cw1.region.base = DMUB_CW1_BASE; 415 cw1.region.top = cw1.region.base + stack_fb->size - 1; 416 417 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 418 /** 419 * Read back all the instruction memory so we don't hang the 420 * DMCUB when backdoor loading if the write from x86 hasn't been 421 * flushed yet. This only occurs in backdoor loading. 422 */ 423 dmub_flush_buffer_mem(inst_fb); 424 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 425 } 426 427 } 428 429 if (dmub->hw_funcs.reset) 430 dmub->hw_funcs.reset(dmub); 431 432 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 433 fw_state_fb && scratch_mem_fb) { 434 cw2.offset.quad_part = data_fb->gpu_addr; 435 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 436 cw2.region.top = cw2.region.base + data_fb->size; 437 438 cw3.offset.quad_part = bios_fb->gpu_addr; 439 cw3.region.base = DMUB_CW3_BASE; 440 cw3.region.top = cw3.region.base + bios_fb->size; 441 442 cw4.offset.quad_part = mail_fb->gpu_addr; 443 cw4.region.base = DMUB_CW4_BASE; 444 cw4.region.top = cw4.region.base + mail_fb->size; 445 446 inbox1.base = cw4.region.base; 447 inbox1.top = cw4.region.top; 448 449 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 450 cw5.region.base = DMUB_CW5_BASE; 451 cw5.region.top = cw5.region.base + tracebuff_fb->size; 452 453 cw6.offset.quad_part = fw_state_fb->gpu_addr; 454 cw6.region.base = DMUB_CW6_BASE; 455 cw6.region.top = cw6.region.base + fw_state_fb->size; 456 457 dmub->fw_state = fw_state_fb->cpu_addr; 458 459 dmub->scratch_mem_fb = *scratch_mem_fb; 460 461 if (dmub->hw_funcs.setup_windows) 462 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 463 &cw5, &cw6); 464 465 if (dmub->hw_funcs.setup_mailbox) 466 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 467 } 468 469 if (mail_fb) { 470 dmub_memset(&rb_params, 0, sizeof(rb_params)); 471 rb_params.ctx = dmub; 472 rb_params.base_address = mail_fb->cpu_addr; 473 rb_params.capacity = DMUB_RB_SIZE; 474 475 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 476 } 477 478 if (dmub->hw_funcs.reset_release) 479 dmub->hw_funcs.reset_release(dmub); 480 481 dmub->hw_init = true; 482 483 return DMUB_STATUS_OK; 484 } 485 486 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 487 { 488 if (!dmub->sw_init) 489 return DMUB_STATUS_INVALID; 490 491 if (dmub->hw_init == false) 492 return DMUB_STATUS_OK; 493 494 if (dmub->hw_funcs.reset) 495 dmub->hw_funcs.reset(dmub); 496 497 dmub->hw_init = false; 498 499 return DMUB_STATUS_OK; 500 } 501 502 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 503 const union dmub_rb_cmd *cmd) 504 { 505 if (!dmub->hw_init) 506 return DMUB_STATUS_INVALID; 507 508 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 509 return DMUB_STATUS_OK; 510 511 return DMUB_STATUS_QUEUE_FULL; 512 } 513 514 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 515 { 516 if (!dmub->hw_init) 517 return DMUB_STATUS_INVALID; 518 519 /** 520 * Read back all the queued commands to ensure that they've 521 * been flushed to framebuffer memory. Otherwise DMCUB might 522 * read back stale, fully invalid or partially invalid data. 523 */ 524 dmub_rb_flush_pending(&dmub->inbox1_rb); 525 526 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 527 return DMUB_STATUS_OK; 528 } 529 530 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 531 uint32_t timeout_us) 532 { 533 uint32_t i; 534 535 if (!dmub->hw_init) 536 return DMUB_STATUS_INVALID; 537 538 if (!dmub->hw_funcs.is_auto_load_done) 539 return DMUB_STATUS_OK; 540 541 for (i = 0; i <= timeout_us; i += 100) { 542 if (dmub->hw_funcs.is_auto_load_done(dmub)) 543 return DMUB_STATUS_OK; 544 545 udelay(100); 546 } 547 548 return DMUB_STATUS_TIMEOUT; 549 } 550 551 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 552 uint32_t timeout_us) 553 { 554 uint32_t i = 0; 555 556 if (!dmub->hw_init) 557 return DMUB_STATUS_INVALID; 558 559 if (!dmub->hw_funcs.is_phy_init) 560 return DMUB_STATUS_OK; 561 562 for (i = 0; i <= timeout_us; i += 10) { 563 if (dmub->hw_funcs.is_phy_init(dmub)) 564 return DMUB_STATUS_OK; 565 566 udelay(10); 567 } 568 569 return DMUB_STATUS_TIMEOUT; 570 } 571 572 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 573 uint32_t timeout_us) 574 { 575 uint32_t i; 576 577 if (!dmub->hw_init) 578 return DMUB_STATUS_INVALID; 579 580 for (i = 0; i <= timeout_us; ++i) { 581 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 582 if (dmub_rb_empty(&dmub->inbox1_rb)) 583 return DMUB_STATUS_OK; 584 585 udelay(1); 586 } 587 588 return DMUB_STATUS_TIMEOUT; 589 } 590 591 enum dmub_status 592 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 593 enum dmub_gpint_command command_code, 594 uint16_t param, uint32_t timeout_us) 595 { 596 union dmub_gpint_data_register reg; 597 uint32_t i; 598 599 if (!dmub->sw_init) 600 return DMUB_STATUS_INVALID; 601 602 if (!dmub->hw_funcs.set_gpint) 603 return DMUB_STATUS_INVALID; 604 605 if (!dmub->hw_funcs.is_gpint_acked) 606 return DMUB_STATUS_INVALID; 607 608 reg.bits.status = 1; 609 reg.bits.command_code = command_code; 610 reg.bits.param = param; 611 612 dmub->hw_funcs.set_gpint(dmub, reg); 613 614 for (i = 0; i < timeout_us; ++i) { 615 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 616 return DMUB_STATUS_OK; 617 } 618 619 return DMUB_STATUS_TIMEOUT; 620 } 621 622 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 623 uint32_t *response) 624 { 625 *response = 0; 626 627 if (!dmub->sw_init) 628 return DMUB_STATUS_INVALID; 629 630 if (!dmub->hw_funcs.get_gpint_response) 631 return DMUB_STATUS_INVALID; 632 633 *response = dmub->hw_funcs.get_gpint_response(dmub); 634 635 return DMUB_STATUS_OK; 636 } 637