1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "os_types.h" 40 /* 41 * Note: the DMUB service is standalone. No additional headers should be 42 * added below or above this line unless they reside within the DMUB 43 * folder. 44 */ 45 46 /* Alignment for framebuffer memory. */ 47 #define DMUB_FB_ALIGNMENT (1024 * 1024) 48 49 /* Stack size. */ 50 #define DMUB_STACK_SIZE (128 * 1024) 51 52 /* Context size. */ 53 #define DMUB_CONTEXT_SIZE (512 * 1024) 54 55 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 57 58 /* Default state size if meta is absent. */ 59 #define DMUB_FW_STATE_SIZE (64 * 1024) 60 61 /* Default tracebuffer size if meta is absent. */ 62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 63 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (256) 67 68 /* Number of windows in use. */ 69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 70 /* Base addresses. */ 71 72 #define DMUB_CW0_BASE (0x60000000) 73 #define DMUB_CW1_BASE (0x61000000) 74 #define DMUB_CW3_BASE (0x63000000) 75 #define DMUB_CW4_BASE (0x64000000) 76 #define DMUB_CW5_BASE (0x65000000) 77 #define DMUB_CW6_BASE (0x66000000) 78 79 #define DMUB_REGION5_BASE (0xA0000000) 80 81 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 82 { 83 return (val + factor - 1) / factor * factor; 84 } 85 86 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 87 { 88 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 89 uint8_t buf[64]; 90 uint32_t pos, end; 91 92 /** 93 * Read 64-byte chunks since we don't want to store a 94 * large temporary buffer for this purpose. 95 */ 96 end = fb->size / sizeof(buf) * sizeof(buf); 97 98 for (pos = 0; pos < end; pos += sizeof(buf)) 99 dmub_memcpy(buf, base + pos, sizeof(buf)); 100 101 /* Read anything leftover into the buffer. */ 102 if (end < fb->size) 103 dmub_memcpy(buf, base + pos, fb->size - end); 104 } 105 106 static const struct dmub_fw_meta_info * 107 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 108 { 109 const union dmub_fw_meta *meta; 110 111 if (!blob || !blob_size) 112 return NULL; 113 114 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 115 return NULL; 116 117 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 118 sizeof(union dmub_fw_meta)); 119 120 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 121 return NULL; 122 123 return &meta->info; 124 } 125 126 static const struct dmub_fw_meta_info * 127 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 128 { 129 const struct dmub_fw_meta_info *info = NULL; 130 131 if (params->fw_bss_data && params->bss_data_size) { 132 /* Legacy metadata region. */ 133 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 134 params->bss_data_size, 135 DMUB_FW_META_OFFSET); 136 } else if (params->fw_inst_const && params->inst_const_size) { 137 /* Combined metadata region - can be aligned to 16-bytes. */ 138 uint32_t i; 139 140 for (i = 0; i < 16; ++i) { 141 info = dmub_get_fw_meta_info_from_blob( 142 params->fw_inst_const, params->inst_const_size, i); 143 144 if (info) 145 break; 146 } 147 } 148 149 return info; 150 } 151 152 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 153 { 154 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 155 156 switch (asic) { 157 case DMUB_ASIC_DCN20: 158 case DMUB_ASIC_DCN21: 159 case DMUB_ASIC_DCN30: 160 case DMUB_ASIC_DCN301: 161 case DMUB_ASIC_DCN302: 162 case DMUB_ASIC_DCN303: 163 dmub->regs = &dmub_srv_dcn20_regs; 164 165 funcs->reset = dmub_dcn20_reset; 166 funcs->reset_release = dmub_dcn20_reset_release; 167 funcs->backdoor_load = dmub_dcn20_backdoor_load; 168 funcs->setup_windows = dmub_dcn20_setup_windows; 169 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 170 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 171 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 172 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 173 funcs->is_supported = dmub_dcn20_is_supported; 174 funcs->is_hw_init = dmub_dcn20_is_hw_init; 175 funcs->set_gpint = dmub_dcn20_set_gpint; 176 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 177 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 178 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 179 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 180 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 181 funcs->get_current_time = dmub_dcn20_get_current_time; 182 183 // Out mailbox register access functions for RN and above 184 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 185 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 186 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 187 188 //outbox0 call stacks 189 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 190 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 191 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 192 193 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 194 195 if (asic == DMUB_ASIC_DCN21) 196 dmub->regs = &dmub_srv_dcn21_regs; 197 198 if (asic == DMUB_ASIC_DCN30) { 199 dmub->regs = &dmub_srv_dcn30_regs; 200 201 funcs->backdoor_load = dmub_dcn30_backdoor_load; 202 funcs->setup_windows = dmub_dcn30_setup_windows; 203 } 204 if (asic == DMUB_ASIC_DCN301) { 205 dmub->regs = &dmub_srv_dcn301_regs; 206 207 funcs->backdoor_load = dmub_dcn30_backdoor_load; 208 funcs->setup_windows = dmub_dcn30_setup_windows; 209 } 210 if (asic == DMUB_ASIC_DCN302) { 211 dmub->regs = &dmub_srv_dcn302_regs; 212 213 funcs->backdoor_load = dmub_dcn30_backdoor_load; 214 funcs->setup_windows = dmub_dcn30_setup_windows; 215 } 216 if (asic == DMUB_ASIC_DCN303) { 217 dmub->regs = &dmub_srv_dcn303_regs; 218 219 funcs->backdoor_load = dmub_dcn30_backdoor_load; 220 funcs->setup_windows = dmub_dcn30_setup_windows; 221 } 222 break; 223 224 case DMUB_ASIC_DCN31: 225 case DMUB_ASIC_DCN31B: 226 case DMUB_ASIC_DCN314: 227 case DMUB_ASIC_DCN315: 228 case DMUB_ASIC_DCN316: 229 if (asic == DMUB_ASIC_DCN314) { 230 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 231 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 232 } else if (asic == DMUB_ASIC_DCN315) { 233 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 234 } else if (asic == DMUB_ASIC_DCN316) { 235 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 236 } else { 237 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 238 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 239 } 240 funcs->reset = dmub_dcn31_reset; 241 funcs->reset_release = dmub_dcn31_reset_release; 242 funcs->backdoor_load = dmub_dcn31_backdoor_load; 243 funcs->setup_windows = dmub_dcn31_setup_windows; 244 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 245 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 246 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 247 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 248 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 249 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 250 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 251 funcs->is_supported = dmub_dcn31_is_supported; 252 funcs->is_hw_init = dmub_dcn31_is_hw_init; 253 funcs->set_gpint = dmub_dcn31_set_gpint; 254 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 255 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 256 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 257 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 258 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 259 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 260 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 261 //outbox0 call stacks 262 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 263 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 264 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 265 266 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 267 funcs->should_detect = dmub_dcn31_should_detect; 268 funcs->get_current_time = dmub_dcn31_get_current_time; 269 270 break; 271 272 case DMUB_ASIC_DCN32: 273 case DMUB_ASIC_DCN321: 274 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 275 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 276 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 277 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 278 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 279 funcs->reset = dmub_dcn32_reset; 280 funcs->reset_release = dmub_dcn32_reset_release; 281 funcs->backdoor_load = dmub_dcn32_backdoor_load; 282 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 283 funcs->setup_windows = dmub_dcn32_setup_windows; 284 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 285 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 286 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 287 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 288 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 289 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 290 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 291 funcs->is_supported = dmub_dcn32_is_supported; 292 funcs->is_hw_init = dmub_dcn32_is_hw_init; 293 funcs->set_gpint = dmub_dcn32_set_gpint; 294 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 295 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 296 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 297 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 298 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 299 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 300 301 /* outbox0 call stacks */ 302 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 303 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 304 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 305 funcs->get_current_time = dmub_dcn32_get_current_time; 306 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 307 308 break; 309 310 default: 311 return false; 312 } 313 314 return true; 315 } 316 317 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 318 const struct dmub_srv_create_params *params) 319 { 320 enum dmub_status status = DMUB_STATUS_OK; 321 322 dmub_memset(dmub, 0, sizeof(*dmub)); 323 324 dmub->funcs = params->funcs; 325 dmub->user_ctx = params->user_ctx; 326 dmub->asic = params->asic; 327 dmub->fw_version = params->fw_version; 328 dmub->is_virtual = params->is_virtual; 329 330 /* Setup asic dependent hardware funcs. */ 331 if (!dmub_srv_hw_setup(dmub, params->asic)) { 332 status = DMUB_STATUS_INVALID; 333 goto cleanup; 334 } 335 336 /* Override (some) hardware funcs based on user params. */ 337 if (params->hw_funcs) { 338 if (params->hw_funcs->emul_get_inbox1_rptr) 339 dmub->hw_funcs.emul_get_inbox1_rptr = 340 params->hw_funcs->emul_get_inbox1_rptr; 341 342 if (params->hw_funcs->emul_set_inbox1_wptr) 343 dmub->hw_funcs.emul_set_inbox1_wptr = 344 params->hw_funcs->emul_set_inbox1_wptr; 345 346 if (params->hw_funcs->is_supported) 347 dmub->hw_funcs.is_supported = 348 params->hw_funcs->is_supported; 349 } 350 351 /* Sanity checks for required hw func pointers. */ 352 if (!dmub->hw_funcs.get_inbox1_rptr || 353 !dmub->hw_funcs.set_inbox1_wptr) { 354 status = DMUB_STATUS_INVALID; 355 goto cleanup; 356 } 357 358 cleanup: 359 if (status == DMUB_STATUS_OK) 360 dmub->sw_init = true; 361 else 362 dmub_srv_destroy(dmub); 363 364 return status; 365 } 366 367 void dmub_srv_destroy(struct dmub_srv *dmub) 368 { 369 dmub_memset(dmub, 0, sizeof(*dmub)); 370 } 371 372 enum dmub_status 373 dmub_srv_calc_region_info(struct dmub_srv *dmub, 374 const struct dmub_srv_region_params *params, 375 struct dmub_srv_region_info *out) 376 { 377 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 378 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 379 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 380 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 381 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 382 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 383 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 384 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 385 const struct dmub_fw_meta_info *fw_info; 386 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 387 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 388 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 389 390 if (!dmub->sw_init) 391 return DMUB_STATUS_INVALID; 392 393 memset(out, 0, sizeof(*out)); 394 395 out->num_regions = DMUB_NUM_WINDOWS; 396 397 inst->base = 0x0; 398 inst->top = inst->base + params->inst_const_size; 399 400 data->base = dmub_align(inst->top, 256); 401 data->top = data->base + params->bss_data_size; 402 403 /* 404 * All cache windows below should be aligned to the size 405 * of the DMCUB cache line, 64 bytes. 406 */ 407 408 stack->base = dmub_align(data->top, 256); 409 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 410 411 bios->base = dmub_align(stack->top, 256); 412 bios->top = bios->base + params->vbios_size; 413 414 mail->base = dmub_align(bios->top, 256); 415 mail->top = mail->base + DMUB_MAILBOX_SIZE; 416 417 fw_info = dmub_get_fw_meta_info(params); 418 419 if (fw_info) { 420 fw_state_size = fw_info->fw_region_size; 421 trace_buffer_size = fw_info->trace_buffer_size; 422 423 /** 424 * If DM didn't fill in a version, then fill it in based on 425 * the firmware meta now that we have it. 426 * 427 * TODO: Make it easier for driver to extract this out to 428 * pass during creation. 429 */ 430 if (dmub->fw_version == 0) 431 dmub->fw_version = fw_info->fw_version; 432 } 433 434 trace_buff->base = dmub_align(mail->top, 256); 435 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 436 437 fw_state->base = dmub_align(trace_buff->top, 256); 438 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 439 440 scratch_mem->base = dmub_align(fw_state->top, 256); 441 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 442 443 out->fb_size = dmub_align(scratch_mem->top, 4096); 444 445 return DMUB_STATUS_OK; 446 } 447 448 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 449 const struct dmub_srv_fb_params *params, 450 struct dmub_srv_fb_info *out) 451 { 452 uint8_t *cpu_base; 453 uint64_t gpu_base; 454 uint32_t i; 455 456 if (!dmub->sw_init) 457 return DMUB_STATUS_INVALID; 458 459 memset(out, 0, sizeof(*out)); 460 461 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 462 return DMUB_STATUS_INVALID; 463 464 cpu_base = (uint8_t *)params->cpu_addr; 465 gpu_base = params->gpu_addr; 466 467 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 468 const struct dmub_region *reg = 469 ¶ms->region_info->regions[i]; 470 471 out->fb[i].cpu_addr = cpu_base + reg->base; 472 out->fb[i].gpu_addr = gpu_base + reg->base; 473 out->fb[i].size = reg->top - reg->base; 474 } 475 476 out->num_fb = DMUB_NUM_WINDOWS; 477 478 return DMUB_STATUS_OK; 479 } 480 481 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 482 bool *is_supported) 483 { 484 *is_supported = false; 485 486 if (!dmub->sw_init) 487 return DMUB_STATUS_INVALID; 488 489 if (dmub->hw_funcs.is_supported) 490 *is_supported = dmub->hw_funcs.is_supported(dmub); 491 492 return DMUB_STATUS_OK; 493 } 494 495 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 496 { 497 *is_hw_init = false; 498 499 if (!dmub->sw_init) 500 return DMUB_STATUS_INVALID; 501 502 if (!dmub->hw_init) 503 return DMUB_STATUS_OK; 504 505 if (dmub->hw_funcs.is_hw_init) 506 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 507 508 return DMUB_STATUS_OK; 509 } 510 511 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 512 const struct dmub_srv_hw_params *params) 513 { 514 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 515 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 516 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 517 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 518 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 519 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 520 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 521 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 522 523 struct dmub_rb_init_params rb_params, outbox0_rb_params; 524 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 525 struct dmub_region inbox1, outbox1, outbox0; 526 527 if (!dmub->sw_init) 528 return DMUB_STATUS_INVALID; 529 530 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 531 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 532 ASSERT(0); 533 return DMUB_STATUS_INVALID; 534 } 535 536 dmub->fb_base = params->fb_base; 537 dmub->fb_offset = params->fb_offset; 538 dmub->psp_version = params->psp_version; 539 540 if (dmub->hw_funcs.reset) 541 dmub->hw_funcs.reset(dmub); 542 543 /* reset the cache of the last wptr as well now that hw is reset */ 544 dmub->inbox1_last_wptr = 0; 545 546 cw0.offset.quad_part = inst_fb->gpu_addr; 547 cw0.region.base = DMUB_CW0_BASE; 548 cw0.region.top = cw0.region.base + inst_fb->size - 1; 549 550 cw1.offset.quad_part = stack_fb->gpu_addr; 551 cw1.region.base = DMUB_CW1_BASE; 552 cw1.region.top = cw1.region.base + stack_fb->size - 1; 553 554 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 555 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 556 557 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 558 /** 559 * Read back all the instruction memory so we don't hang the 560 * DMCUB when backdoor loading if the write from x86 hasn't been 561 * flushed yet. This only occurs in backdoor loading. 562 */ 563 dmub_flush_buffer_mem(inst_fb); 564 565 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 566 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 567 else 568 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 569 } 570 571 cw2.offset.quad_part = data_fb->gpu_addr; 572 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 573 cw2.region.top = cw2.region.base + data_fb->size; 574 575 cw3.offset.quad_part = bios_fb->gpu_addr; 576 cw3.region.base = DMUB_CW3_BASE; 577 cw3.region.top = cw3.region.base + bios_fb->size; 578 579 cw4.offset.quad_part = mail_fb->gpu_addr; 580 cw4.region.base = DMUB_CW4_BASE; 581 cw4.region.top = cw4.region.base + mail_fb->size; 582 583 /** 584 * Doubled the mailbox region to accomodate inbox and outbox. 585 * Note: Currently, currently total mailbox size is 16KB. It is split 586 * equally into 8KB between inbox and outbox. If this config is 587 * changed, then uncached base address configuration of outbox1 588 * has to be updated in funcs->setup_out_mailbox. 589 */ 590 inbox1.base = cw4.region.base; 591 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 592 outbox1.base = inbox1.top; 593 outbox1.top = cw4.region.top; 594 595 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 596 cw5.region.base = DMUB_CW5_BASE; 597 cw5.region.top = cw5.region.base + tracebuff_fb->size; 598 599 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 600 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 601 602 cw6.offset.quad_part = fw_state_fb->gpu_addr; 603 cw6.region.base = DMUB_CW6_BASE; 604 cw6.region.top = cw6.region.base + fw_state_fb->size; 605 606 dmub->fw_state = fw_state_fb->cpu_addr; 607 608 dmub->scratch_mem_fb = *scratch_mem_fb; 609 610 if (dmub->hw_funcs.setup_windows) 611 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 612 613 if (dmub->hw_funcs.setup_outbox0) 614 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 615 616 if (dmub->hw_funcs.setup_mailbox) 617 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 618 if (dmub->hw_funcs.setup_out_mailbox) 619 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 620 621 dmub_memset(&rb_params, 0, sizeof(rb_params)); 622 rb_params.ctx = dmub; 623 rb_params.base_address = mail_fb->cpu_addr; 624 rb_params.capacity = DMUB_RB_SIZE; 625 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 626 627 // Initialize outbox1 ring buffer 628 rb_params.ctx = dmub; 629 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 630 rb_params.capacity = DMUB_RB_SIZE; 631 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 632 633 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 634 outbox0_rb_params.ctx = dmub; 635 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 636 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 637 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 638 639 /* Report to DMUB what features are supported by current driver */ 640 if (dmub->hw_funcs.enable_dmub_boot_options) 641 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 642 643 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 644 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 645 params->skip_panel_power_sequence); 646 647 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 648 dmub->hw_funcs.reset_release(dmub); 649 650 dmub->hw_init = true; 651 652 return DMUB_STATUS_OK; 653 } 654 655 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 656 { 657 if (!dmub->sw_init) 658 return DMUB_STATUS_INVALID; 659 660 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 661 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 662 dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 663 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 664 } 665 666 return DMUB_STATUS_OK; 667 } 668 669 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 670 { 671 if (!dmub->sw_init) 672 return DMUB_STATUS_INVALID; 673 674 if (dmub->hw_funcs.reset) 675 dmub->hw_funcs.reset(dmub); 676 677 /* mailboxes have been reset in hw, so reset the sw state as well */ 678 dmub->inbox1_last_wptr = 0; 679 dmub->inbox1_rb.wrpt = 0; 680 dmub->inbox1_rb.rptr = 0; 681 dmub->outbox0_rb.wrpt = 0; 682 dmub->outbox0_rb.rptr = 0; 683 dmub->outbox1_rb.wrpt = 0; 684 dmub->outbox1_rb.rptr = 0; 685 686 dmub->hw_init = false; 687 688 return DMUB_STATUS_OK; 689 } 690 691 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 692 const union dmub_rb_cmd *cmd) 693 { 694 if (!dmub->hw_init) 695 return DMUB_STATUS_INVALID; 696 697 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 698 return DMUB_STATUS_OK; 699 700 return DMUB_STATUS_QUEUE_FULL; 701 } 702 703 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 704 { 705 struct dmub_rb flush_rb; 706 707 if (!dmub->hw_init) 708 return DMUB_STATUS_INVALID; 709 710 /** 711 * Read back all the queued commands to ensure that they've 712 * been flushed to framebuffer memory. Otherwise DMCUB might 713 * read back stale, fully invalid or partially invalid data. 714 */ 715 flush_rb = dmub->inbox1_rb; 716 flush_rb.rptr = dmub->inbox1_last_wptr; 717 dmub_rb_flush_pending(&flush_rb); 718 719 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 720 721 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 722 723 return DMUB_STATUS_OK; 724 } 725 726 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 727 uint32_t timeout_us) 728 { 729 uint32_t i; 730 731 if (!dmub->hw_init) 732 return DMUB_STATUS_INVALID; 733 734 for (i = 0; i <= timeout_us; i += 100) { 735 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 736 737 if (status.bits.dal_fw && status.bits.mailbox_rdy) 738 return DMUB_STATUS_OK; 739 740 udelay(100); 741 } 742 743 return DMUB_STATUS_TIMEOUT; 744 } 745 746 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 747 uint32_t timeout_us) 748 { 749 uint32_t i, rptr; 750 751 if (!dmub->hw_init) 752 return DMUB_STATUS_INVALID; 753 754 for (i = 0; i <= timeout_us; ++i) { 755 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 756 757 if (rptr > dmub->inbox1_rb.capacity) 758 return DMUB_STATUS_HW_FAILURE; 759 760 dmub->inbox1_rb.rptr = rptr; 761 762 if (dmub_rb_empty(&dmub->inbox1_rb)) 763 return DMUB_STATUS_OK; 764 765 udelay(1); 766 } 767 768 return DMUB_STATUS_TIMEOUT; 769 } 770 771 enum dmub_status 772 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 773 enum dmub_gpint_command command_code, 774 uint16_t param, uint32_t timeout_us) 775 { 776 union dmub_gpint_data_register reg; 777 uint32_t i; 778 779 if (!dmub->sw_init) 780 return DMUB_STATUS_INVALID; 781 782 if (!dmub->hw_funcs.set_gpint) 783 return DMUB_STATUS_INVALID; 784 785 if (!dmub->hw_funcs.is_gpint_acked) 786 return DMUB_STATUS_INVALID; 787 788 reg.bits.status = 1; 789 reg.bits.command_code = command_code; 790 reg.bits.param = param; 791 792 dmub->hw_funcs.set_gpint(dmub, reg); 793 794 for (i = 0; i < timeout_us; ++i) { 795 udelay(1); 796 797 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 798 return DMUB_STATUS_OK; 799 } 800 801 return DMUB_STATUS_TIMEOUT; 802 } 803 804 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 805 uint32_t *response) 806 { 807 *response = 0; 808 809 if (!dmub->sw_init) 810 return DMUB_STATUS_INVALID; 811 812 if (!dmub->hw_funcs.get_gpint_response) 813 return DMUB_STATUS_INVALID; 814 815 *response = dmub->hw_funcs.get_gpint_response(dmub); 816 817 return DMUB_STATUS_OK; 818 } 819 820 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 821 uint32_t *dataout) 822 { 823 *dataout = 0; 824 825 if (!dmub->sw_init) 826 return DMUB_STATUS_INVALID; 827 828 if (!dmub->hw_funcs.get_gpint_dataout) 829 return DMUB_STATUS_INVALID; 830 831 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 832 833 return DMUB_STATUS_OK; 834 } 835 836 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 837 union dmub_fw_boot_status *status) 838 { 839 status->all = 0; 840 841 if (!dmub->sw_init) 842 return DMUB_STATUS_INVALID; 843 844 if (dmub->hw_funcs.get_fw_status) 845 *status = dmub->hw_funcs.get_fw_status(dmub); 846 847 return DMUB_STATUS_OK; 848 } 849 850 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 851 union dmub_fw_boot_options *option) 852 { 853 option->all = 0; 854 855 if (!dmub->sw_init) 856 return DMUB_STATUS_INVALID; 857 858 if (dmub->hw_funcs.get_fw_boot_option) 859 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 860 861 return DMUB_STATUS_OK; 862 } 863 864 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 865 bool skip) 866 { 867 if (!dmub->sw_init) 868 return DMUB_STATUS_INVALID; 869 870 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 871 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 872 873 return DMUB_STATUS_OK; 874 } 875 876 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 877 union dmub_rb_cmd *cmd) 878 { 879 enum dmub_status status = DMUB_STATUS_OK; 880 881 // Queue command 882 status = dmub_srv_cmd_queue(dmub, cmd); 883 884 if (status != DMUB_STATUS_OK) 885 return status; 886 887 // Execute command 888 status = dmub_srv_cmd_execute(dmub); 889 890 if (status != DMUB_STATUS_OK) 891 return status; 892 893 // Wait for DMUB to process command 894 status = dmub_srv_wait_for_idle(dmub, 100000); 895 896 if (status != DMUB_STATUS_OK) 897 return status; 898 899 // Copy data back from ring buffer into command 900 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 901 902 return status; 903 } 904 905 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 906 void *entry) 907 { 908 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 909 uint64_t *dst = (uint64_t *)entry; 910 uint8_t i; 911 uint8_t loop_count; 912 913 if (rb->rptr == rb->wrpt) 914 return false; 915 916 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 917 // copying data 918 for (i = 0; i < loop_count; i++) 919 *dst++ = *src++; 920 921 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 922 923 rb->rptr %= rb->capacity; 924 925 return true; 926 } 927 928 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 929 { 930 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 931 932 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 933 } 934 935 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 936 { 937 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 938 return false; 939 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 940 return true; 941 } 942 943 bool dmub_srv_should_detect(struct dmub_srv *dmub) 944 { 945 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 946 return false; 947 948 return dmub->hw_funcs.should_detect(dmub); 949 } 950 951 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 952 { 953 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 954 return DMUB_STATUS_INVALID; 955 956 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 957 return DMUB_STATUS_OK; 958 } 959 960 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 961 { 962 uint32_t i = 0; 963 uint32_t ack = 0; 964 965 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 966 return DMUB_STATUS_INVALID; 967 968 for (i = 0; i <= timeout_us; i++) { 969 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 970 if (ack) 971 return DMUB_STATUS_OK; 972 } 973 return DMUB_STATUS_TIMEOUT; 974 } 975 976 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 977 union dmub_inbox0_data_register data) 978 { 979 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 980 return DMUB_STATUS_INVALID; 981 982 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 983 return DMUB_STATUS_OK; 984 } 985