1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 31 #include "dmub_dcn30.h" 32 #endif 33 #ifdef CONFIG_DRM_AMD_DC_DCN3_01 34 #include "dmub_dcn301.h" 35 #endif 36 #include "os_types.h" 37 /* 38 * Note: the DMUB service is standalone. No additional headers should be 39 * added below or above this line unless they reside within the DMUB 40 * folder. 41 */ 42 43 /* Alignment for framebuffer memory. */ 44 #define DMUB_FB_ALIGNMENT (1024 * 1024) 45 46 /* Stack size. */ 47 #define DMUB_STACK_SIZE (128 * 1024) 48 49 /* Context size. */ 50 #define DMUB_CONTEXT_SIZE (512 * 1024) 51 52 /* Mailbox size */ 53 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 54 55 /* Default state size if meta is absent. */ 56 #define DMUB_FW_STATE_SIZE (64 * 1024) 57 58 /* Default tracebuffer size if meta is absent. */ 59 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 60 61 /* Default scratch mem size. */ 62 #define DMUB_SCRATCH_MEM_SIZE (256) 63 64 /* Number of windows in use. */ 65 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 66 /* Base addresses. */ 67 68 #define DMUB_CW0_BASE (0x60000000) 69 #define DMUB_CW1_BASE (0x61000000) 70 #define DMUB_CW3_BASE (0x63000000) 71 #define DMUB_CW4_BASE (0x64000000) 72 #define DMUB_CW5_BASE (0x65000000) 73 #define DMUB_CW6_BASE (0x66000000) 74 75 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 76 { 77 return (val + factor - 1) / factor * factor; 78 } 79 80 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 81 { 82 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 83 uint8_t buf[64]; 84 uint32_t pos, end; 85 86 /** 87 * Read 64-byte chunks since we don't want to store a 88 * large temporary buffer for this purpose. 89 */ 90 end = fb->size / sizeof(buf) * sizeof(buf); 91 92 for (pos = 0; pos < end; pos += sizeof(buf)) 93 dmub_memcpy(buf, base + pos, sizeof(buf)); 94 95 /* Read anything leftover into the buffer. */ 96 if (end < fb->size) 97 dmub_memcpy(buf, base + pos, fb->size - end); 98 } 99 100 static const struct dmub_fw_meta_info * 101 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 102 { 103 const union dmub_fw_meta *meta; 104 const uint8_t *blob = NULL; 105 uint32_t blob_size = 0; 106 uint32_t meta_offset = 0; 107 108 if (params->fw_bss_data && params->bss_data_size) { 109 /* Legacy metadata region. */ 110 blob = params->fw_bss_data; 111 blob_size = params->bss_data_size; 112 meta_offset = DMUB_FW_META_OFFSET; 113 } else if (params->fw_inst_const && params->inst_const_size) { 114 /* Combined metadata region. */ 115 blob = params->fw_inst_const; 116 blob_size = params->inst_const_size; 117 meta_offset = 0; 118 } 119 120 if (!blob || !blob_size) 121 return NULL; 122 123 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 124 return NULL; 125 126 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 127 sizeof(union dmub_fw_meta)); 128 129 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 130 return NULL; 131 132 return &meta->info; 133 } 134 135 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 136 { 137 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 138 139 switch (asic) { 140 case DMUB_ASIC_DCN20: 141 case DMUB_ASIC_DCN21: 142 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 143 case DMUB_ASIC_DCN30: 144 #endif 145 #ifdef CONFIG_DRM_AMD_DC_DCN3_01 146 case DMUB_ASIC_DCN301: 147 #endif 148 dmub->regs = &dmub_srv_dcn20_regs; 149 150 funcs->reset = dmub_dcn20_reset; 151 funcs->reset_release = dmub_dcn20_reset_release; 152 funcs->backdoor_load = dmub_dcn20_backdoor_load; 153 funcs->setup_windows = dmub_dcn20_setup_windows; 154 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 155 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 156 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 157 funcs->is_supported = dmub_dcn20_is_supported; 158 funcs->is_hw_init = dmub_dcn20_is_hw_init; 159 funcs->set_gpint = dmub_dcn20_set_gpint; 160 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 161 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 162 163 if (asic == DMUB_ASIC_DCN21) { 164 dmub->regs = &dmub_srv_dcn21_regs; 165 166 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 167 funcs->is_phy_init = dmub_dcn21_is_phy_init; 168 } 169 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 170 if (asic == DMUB_ASIC_DCN30) { 171 dmub->regs = &dmub_srv_dcn30_regs; 172 173 funcs->is_auto_load_done = dmub_dcn30_is_auto_load_done; 174 funcs->backdoor_load = dmub_dcn30_backdoor_load; 175 funcs->setup_windows = dmub_dcn30_setup_windows; 176 } 177 #endif 178 #ifdef CONFIG_DRM_AMD_DC_DCN3_01 179 if (asic == DMUB_ASIC_DCN301) { 180 dmub->regs = &dmub_srv_dcn301_regs; 181 182 funcs->backdoor_load = dmub_dcn30_backdoor_load; 183 funcs->setup_windows = dmub_dcn30_setup_windows; 184 } 185 #endif 186 break; 187 188 default: 189 return false; 190 } 191 192 return true; 193 } 194 195 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 196 const struct dmub_srv_create_params *params) 197 { 198 enum dmub_status status = DMUB_STATUS_OK; 199 200 dmub_memset(dmub, 0, sizeof(*dmub)); 201 202 dmub->funcs = params->funcs; 203 dmub->user_ctx = params->user_ctx; 204 dmub->asic = params->asic; 205 dmub->fw_version = params->fw_version; 206 dmub->is_virtual = params->is_virtual; 207 208 /* Setup asic dependent hardware funcs. */ 209 if (!dmub_srv_hw_setup(dmub, params->asic)) { 210 status = DMUB_STATUS_INVALID; 211 goto cleanup; 212 } 213 214 /* Override (some) hardware funcs based on user params. */ 215 if (params->hw_funcs) { 216 if (params->hw_funcs->emul_get_inbox1_rptr) 217 dmub->hw_funcs.emul_get_inbox1_rptr = 218 params->hw_funcs->emul_get_inbox1_rptr; 219 220 if (params->hw_funcs->emul_set_inbox1_wptr) 221 dmub->hw_funcs.emul_set_inbox1_wptr = 222 params->hw_funcs->emul_set_inbox1_wptr; 223 224 if (params->hw_funcs->is_supported) 225 dmub->hw_funcs.is_supported = 226 params->hw_funcs->is_supported; 227 } 228 229 /* Sanity checks for required hw func pointers. */ 230 if (!dmub->hw_funcs.get_inbox1_rptr || 231 !dmub->hw_funcs.set_inbox1_wptr) { 232 status = DMUB_STATUS_INVALID; 233 goto cleanup; 234 } 235 236 cleanup: 237 if (status == DMUB_STATUS_OK) 238 dmub->sw_init = true; 239 else 240 dmub_srv_destroy(dmub); 241 242 return status; 243 } 244 245 void dmub_srv_destroy(struct dmub_srv *dmub) 246 { 247 dmub_memset(dmub, 0, sizeof(*dmub)); 248 } 249 250 enum dmub_status 251 dmub_srv_calc_region_info(struct dmub_srv *dmub, 252 const struct dmub_srv_region_params *params, 253 struct dmub_srv_region_info *out) 254 { 255 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 256 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 257 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 258 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 259 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 260 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 261 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 262 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 263 const struct dmub_fw_meta_info *fw_info; 264 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 265 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 266 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 267 268 if (!dmub->sw_init) 269 return DMUB_STATUS_INVALID; 270 271 memset(out, 0, sizeof(*out)); 272 273 out->num_regions = DMUB_NUM_WINDOWS; 274 275 inst->base = 0x0; 276 inst->top = inst->base + params->inst_const_size; 277 278 data->base = dmub_align(inst->top, 256); 279 data->top = data->base + params->bss_data_size; 280 281 /* 282 * All cache windows below should be aligned to the size 283 * of the DMCUB cache line, 64 bytes. 284 */ 285 286 stack->base = dmub_align(data->top, 256); 287 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 288 289 bios->base = dmub_align(stack->top, 256); 290 bios->top = bios->base + params->vbios_size; 291 292 mail->base = dmub_align(bios->top, 256); 293 mail->top = mail->base + DMUB_MAILBOX_SIZE; 294 295 fw_info = dmub_get_fw_meta_info(params); 296 297 if (fw_info) { 298 fw_state_size = fw_info->fw_region_size; 299 trace_buffer_size = fw_info->trace_buffer_size; 300 301 /** 302 * If DM didn't fill in a version, then fill it in based on 303 * the firmware meta now that we have it. 304 * 305 * TODO: Make it easier for driver to extract this out to 306 * pass during creation. 307 */ 308 if (dmub->fw_version == 0) 309 dmub->fw_version = fw_info->fw_version; 310 } 311 312 trace_buff->base = dmub_align(mail->top, 256); 313 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 314 315 fw_state->base = dmub_align(trace_buff->top, 256); 316 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 317 318 scratch_mem->base = dmub_align(fw_state->top, 256); 319 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 320 321 out->fb_size = dmub_align(scratch_mem->top, 4096); 322 323 return DMUB_STATUS_OK; 324 } 325 326 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 327 const struct dmub_srv_fb_params *params, 328 struct dmub_srv_fb_info *out) 329 { 330 uint8_t *cpu_base; 331 uint64_t gpu_base; 332 uint32_t i; 333 334 if (!dmub->sw_init) 335 return DMUB_STATUS_INVALID; 336 337 memset(out, 0, sizeof(*out)); 338 339 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 340 return DMUB_STATUS_INVALID; 341 342 cpu_base = (uint8_t *)params->cpu_addr; 343 gpu_base = params->gpu_addr; 344 345 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 346 const struct dmub_region *reg = 347 ¶ms->region_info->regions[i]; 348 349 out->fb[i].cpu_addr = cpu_base + reg->base; 350 out->fb[i].gpu_addr = gpu_base + reg->base; 351 out->fb[i].size = reg->top - reg->base; 352 } 353 354 out->num_fb = DMUB_NUM_WINDOWS; 355 356 return DMUB_STATUS_OK; 357 } 358 359 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 360 bool *is_supported) 361 { 362 *is_supported = false; 363 364 if (!dmub->sw_init) 365 return DMUB_STATUS_INVALID; 366 367 if (dmub->hw_funcs.is_supported) 368 *is_supported = dmub->hw_funcs.is_supported(dmub); 369 370 return DMUB_STATUS_OK; 371 } 372 373 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 374 { 375 *is_hw_init = false; 376 377 if (!dmub->sw_init) 378 return DMUB_STATUS_INVALID; 379 380 if (!dmub->hw_init) 381 return DMUB_STATUS_OK; 382 383 if (dmub->hw_funcs.is_hw_init) 384 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 385 386 return DMUB_STATUS_OK; 387 } 388 389 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 390 const struct dmub_srv_hw_params *params) 391 { 392 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 393 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 394 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 395 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 396 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 397 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 398 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 399 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 400 401 struct dmub_rb_init_params rb_params; 402 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 403 struct dmub_region inbox1; 404 405 if (!dmub->sw_init) 406 return DMUB_STATUS_INVALID; 407 408 dmub->fb_base = params->fb_base; 409 dmub->fb_offset = params->fb_offset; 410 dmub->psp_version = params->psp_version; 411 412 if (inst_fb && data_fb) { 413 cw0.offset.quad_part = inst_fb->gpu_addr; 414 cw0.region.base = DMUB_CW0_BASE; 415 cw0.region.top = cw0.region.base + inst_fb->size - 1; 416 417 cw1.offset.quad_part = stack_fb->gpu_addr; 418 cw1.region.base = DMUB_CW1_BASE; 419 cw1.region.top = cw1.region.base + stack_fb->size - 1; 420 421 /** 422 * Read back all the instruction memory so we don't hang the 423 * DMCUB when backdoor loading if the write from x86 hasn't been 424 * flushed yet. This only occurs in backdoor loading. 425 */ 426 dmub_flush_buffer_mem(inst_fb); 427 428 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) 429 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 430 } 431 432 if (dmub->hw_funcs.reset) 433 dmub->hw_funcs.reset(dmub); 434 435 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 436 fw_state_fb && scratch_mem_fb) { 437 cw2.offset.quad_part = data_fb->gpu_addr; 438 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 439 cw2.region.top = cw2.region.base + data_fb->size; 440 441 cw3.offset.quad_part = bios_fb->gpu_addr; 442 cw3.region.base = DMUB_CW3_BASE; 443 cw3.region.top = cw3.region.base + bios_fb->size; 444 445 cw4.offset.quad_part = mail_fb->gpu_addr; 446 cw4.region.base = DMUB_CW4_BASE; 447 cw4.region.top = cw4.region.base + mail_fb->size; 448 449 inbox1.base = cw4.region.base; 450 inbox1.top = cw4.region.top; 451 452 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 453 cw5.region.base = DMUB_CW5_BASE; 454 cw5.region.top = cw5.region.base + tracebuff_fb->size; 455 456 cw6.offset.quad_part = fw_state_fb->gpu_addr; 457 cw6.region.base = DMUB_CW6_BASE; 458 cw6.region.top = cw6.region.base + fw_state_fb->size; 459 460 dmub->fw_state = fw_state_fb->cpu_addr; 461 462 dmub->scratch_mem_fb = *scratch_mem_fb; 463 464 if (dmub->hw_funcs.setup_windows) 465 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 466 &cw5, &cw6); 467 468 if (dmub->hw_funcs.setup_mailbox) 469 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 470 } 471 472 if (mail_fb) { 473 dmub_memset(&rb_params, 0, sizeof(rb_params)); 474 rb_params.ctx = dmub; 475 rb_params.base_address = mail_fb->cpu_addr; 476 rb_params.capacity = DMUB_RB_SIZE; 477 478 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 479 } 480 481 if (dmub->hw_funcs.reset_release) 482 dmub->hw_funcs.reset_release(dmub); 483 484 dmub->hw_init = true; 485 486 return DMUB_STATUS_OK; 487 } 488 489 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 490 { 491 if (!dmub->sw_init) 492 return DMUB_STATUS_INVALID; 493 494 if (dmub->hw_init == false) 495 return DMUB_STATUS_OK; 496 497 if (dmub->hw_funcs.reset) 498 dmub->hw_funcs.reset(dmub); 499 500 dmub->hw_init = false; 501 502 return DMUB_STATUS_OK; 503 } 504 505 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 506 const union dmub_rb_cmd *cmd) 507 { 508 if (!dmub->hw_init) 509 return DMUB_STATUS_INVALID; 510 511 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 512 return DMUB_STATUS_OK; 513 514 return DMUB_STATUS_QUEUE_FULL; 515 } 516 517 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 518 { 519 if (!dmub->hw_init) 520 return DMUB_STATUS_INVALID; 521 522 /** 523 * Read back all the queued commands to ensure that they've 524 * been flushed to framebuffer memory. Otherwise DMCUB might 525 * read back stale, fully invalid or partially invalid data. 526 */ 527 dmub_rb_flush_pending(&dmub->inbox1_rb); 528 529 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 530 return DMUB_STATUS_OK; 531 } 532 533 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 534 uint32_t timeout_us) 535 { 536 uint32_t i; 537 538 if (!dmub->hw_init) 539 return DMUB_STATUS_INVALID; 540 541 if (!dmub->hw_funcs.is_auto_load_done) 542 return DMUB_STATUS_OK; 543 544 for (i = 0; i <= timeout_us; i += 100) { 545 if (dmub->hw_funcs.is_auto_load_done(dmub)) 546 return DMUB_STATUS_OK; 547 548 udelay(100); 549 } 550 551 return DMUB_STATUS_TIMEOUT; 552 } 553 554 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 555 uint32_t timeout_us) 556 { 557 uint32_t i = 0; 558 559 if (!dmub->hw_init) 560 return DMUB_STATUS_INVALID; 561 562 if (!dmub->hw_funcs.is_phy_init) 563 return DMUB_STATUS_OK; 564 565 for (i = 0; i <= timeout_us; i += 10) { 566 if (dmub->hw_funcs.is_phy_init(dmub)) 567 return DMUB_STATUS_OK; 568 569 udelay(10); 570 } 571 572 return DMUB_STATUS_TIMEOUT; 573 } 574 575 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 576 uint32_t timeout_us) 577 { 578 uint32_t i; 579 580 if (!dmub->hw_init) 581 return DMUB_STATUS_INVALID; 582 583 for (i = 0; i <= timeout_us; ++i) { 584 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 585 if (dmub_rb_empty(&dmub->inbox1_rb)) 586 return DMUB_STATUS_OK; 587 588 udelay(1); 589 } 590 591 return DMUB_STATUS_TIMEOUT; 592 } 593 594 enum dmub_status 595 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 596 enum dmub_gpint_command command_code, 597 uint16_t param, uint32_t timeout_us) 598 { 599 union dmub_gpint_data_register reg; 600 uint32_t i; 601 602 if (!dmub->sw_init) 603 return DMUB_STATUS_INVALID; 604 605 if (!dmub->hw_funcs.set_gpint) 606 return DMUB_STATUS_INVALID; 607 608 if (!dmub->hw_funcs.is_gpint_acked) 609 return DMUB_STATUS_INVALID; 610 611 reg.bits.status = 1; 612 reg.bits.command_code = command_code; 613 reg.bits.param = param; 614 615 dmub->hw_funcs.set_gpint(dmub, reg); 616 617 for (i = 0; i < timeout_us; ++i) { 618 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 619 return DMUB_STATUS_OK; 620 } 621 622 return DMUB_STATUS_TIMEOUT; 623 } 624 625 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 626 uint32_t *response) 627 { 628 *response = 0; 629 630 if (!dmub->sw_init) 631 return DMUB_STATUS_INVALID; 632 633 if (!dmub->hw_funcs.get_gpint_response) 634 return DMUB_STATUS_INVALID; 635 636 *response = dmub->hw_funcs.get_gpint_response(dmub); 637 638 return DMUB_STATUS_OK; 639 } 640