1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "os_types.h" 34 /* 35 * Note: the DMUB service is standalone. No additional headers should be 36 * added below or above this line unless they reside within the DMUB 37 * folder. 38 */ 39 40 /* Alignment for framebuffer memory. */ 41 #define DMUB_FB_ALIGNMENT (1024 * 1024) 42 43 /* Stack size. */ 44 #define DMUB_STACK_SIZE (128 * 1024) 45 46 /* Context size. */ 47 #define DMUB_CONTEXT_SIZE (512 * 1024) 48 49 /* Mailbox size */ 50 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 51 52 /* Default state size if meta is absent. */ 53 #define DMUB_FW_STATE_SIZE (64 * 1024) 54 55 /* Default tracebuffer size if meta is absent. */ 56 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 57 58 /* Default scratch mem size. */ 59 #define DMUB_SCRATCH_MEM_SIZE (256) 60 61 /* Number of windows in use. */ 62 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 63 /* Base addresses. */ 64 65 #define DMUB_CW0_BASE (0x60000000) 66 #define DMUB_CW1_BASE (0x61000000) 67 #define DMUB_CW3_BASE (0x63000000) 68 #define DMUB_CW4_BASE (0x64000000) 69 #define DMUB_CW5_BASE (0x65000000) 70 #define DMUB_CW6_BASE (0x66000000) 71 72 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 73 { 74 return (val + factor - 1) / factor * factor; 75 } 76 77 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 78 { 79 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 80 uint8_t buf[64]; 81 uint32_t pos, end; 82 83 /** 84 * Read 64-byte chunks since we don't want to store a 85 * large temporary buffer for this purpose. 86 */ 87 end = fb->size / sizeof(buf) * sizeof(buf); 88 89 for (pos = 0; pos < end; pos += sizeof(buf)) 90 dmub_memcpy(buf, base + pos, sizeof(buf)); 91 92 /* Read anything leftover into the buffer. */ 93 if (end < fb->size) 94 dmub_memcpy(buf, base + pos, fb->size - end); 95 } 96 97 static const struct dmub_fw_meta_info * 98 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 99 { 100 const union dmub_fw_meta *meta; 101 const uint8_t *blob = NULL; 102 uint32_t blob_size = 0; 103 uint32_t meta_offset = 0; 104 105 if (params->fw_bss_data && params->bss_data_size) { 106 /* Legacy metadata region. */ 107 blob = params->fw_bss_data; 108 blob_size = params->bss_data_size; 109 meta_offset = DMUB_FW_META_OFFSET; 110 } else if (params->fw_inst_const && params->inst_const_size) { 111 /* Combined metadata region. */ 112 blob = params->fw_inst_const; 113 blob_size = params->inst_const_size; 114 meta_offset = 0; 115 } 116 117 if (!blob || !blob_size) 118 return NULL; 119 120 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 121 return NULL; 122 123 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 124 sizeof(union dmub_fw_meta)); 125 126 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 127 return NULL; 128 129 return &meta->info; 130 } 131 132 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 133 { 134 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 135 136 switch (asic) { 137 case DMUB_ASIC_DCN20: 138 case DMUB_ASIC_DCN21: 139 case DMUB_ASIC_DCN30: 140 case DMUB_ASIC_DCN301: 141 case DMUB_ASIC_DCN302: 142 dmub->regs = &dmub_srv_dcn20_regs; 143 144 funcs->reset = dmub_dcn20_reset; 145 funcs->reset_release = dmub_dcn20_reset_release; 146 funcs->backdoor_load = dmub_dcn20_backdoor_load; 147 funcs->setup_windows = dmub_dcn20_setup_windows; 148 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 149 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 150 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 151 funcs->is_supported = dmub_dcn20_is_supported; 152 funcs->is_hw_init = dmub_dcn20_is_hw_init; 153 funcs->set_gpint = dmub_dcn20_set_gpint; 154 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 155 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 156 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 157 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 158 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 159 160 if (asic == DMUB_ASIC_DCN21) { 161 dmub->regs = &dmub_srv_dcn21_regs; 162 163 funcs->is_phy_init = dmub_dcn21_is_phy_init; 164 } 165 if (asic == DMUB_ASIC_DCN30) { 166 dmub->regs = &dmub_srv_dcn30_regs; 167 168 funcs->backdoor_load = dmub_dcn30_backdoor_load; 169 funcs->setup_windows = dmub_dcn30_setup_windows; 170 } 171 if (asic == DMUB_ASIC_DCN301) { 172 dmub->regs = &dmub_srv_dcn301_regs; 173 174 funcs->backdoor_load = dmub_dcn30_backdoor_load; 175 funcs->setup_windows = dmub_dcn30_setup_windows; 176 } 177 if (asic == DMUB_ASIC_DCN302) { 178 dmub->regs = &dmub_srv_dcn302_regs; 179 180 funcs->backdoor_load = dmub_dcn30_backdoor_load; 181 funcs->setup_windows = dmub_dcn30_setup_windows; 182 } 183 break; 184 185 default: 186 return false; 187 } 188 189 return true; 190 } 191 192 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 193 const struct dmub_srv_create_params *params) 194 { 195 enum dmub_status status = DMUB_STATUS_OK; 196 197 dmub_memset(dmub, 0, sizeof(*dmub)); 198 199 dmub->funcs = params->funcs; 200 dmub->user_ctx = params->user_ctx; 201 dmub->asic = params->asic; 202 dmub->fw_version = params->fw_version; 203 dmub->is_virtual = params->is_virtual; 204 205 /* Setup asic dependent hardware funcs. */ 206 if (!dmub_srv_hw_setup(dmub, params->asic)) { 207 status = DMUB_STATUS_INVALID; 208 goto cleanup; 209 } 210 211 /* Override (some) hardware funcs based on user params. */ 212 if (params->hw_funcs) { 213 if (params->hw_funcs->emul_get_inbox1_rptr) 214 dmub->hw_funcs.emul_get_inbox1_rptr = 215 params->hw_funcs->emul_get_inbox1_rptr; 216 217 if (params->hw_funcs->emul_set_inbox1_wptr) 218 dmub->hw_funcs.emul_set_inbox1_wptr = 219 params->hw_funcs->emul_set_inbox1_wptr; 220 221 if (params->hw_funcs->is_supported) 222 dmub->hw_funcs.is_supported = 223 params->hw_funcs->is_supported; 224 } 225 226 /* Sanity checks for required hw func pointers. */ 227 if (!dmub->hw_funcs.get_inbox1_rptr || 228 !dmub->hw_funcs.set_inbox1_wptr) { 229 status = DMUB_STATUS_INVALID; 230 goto cleanup; 231 } 232 233 cleanup: 234 if (status == DMUB_STATUS_OK) 235 dmub->sw_init = true; 236 else 237 dmub_srv_destroy(dmub); 238 239 return status; 240 } 241 242 void dmub_srv_destroy(struct dmub_srv *dmub) 243 { 244 dmub_memset(dmub, 0, sizeof(*dmub)); 245 } 246 247 enum dmub_status 248 dmub_srv_calc_region_info(struct dmub_srv *dmub, 249 const struct dmub_srv_region_params *params, 250 struct dmub_srv_region_info *out) 251 { 252 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 253 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 254 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 255 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 256 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 257 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 258 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 259 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 260 const struct dmub_fw_meta_info *fw_info; 261 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 262 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 263 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 264 265 if (!dmub->sw_init) 266 return DMUB_STATUS_INVALID; 267 268 memset(out, 0, sizeof(*out)); 269 270 out->num_regions = DMUB_NUM_WINDOWS; 271 272 inst->base = 0x0; 273 inst->top = inst->base + params->inst_const_size; 274 275 data->base = dmub_align(inst->top, 256); 276 data->top = data->base + params->bss_data_size; 277 278 /* 279 * All cache windows below should be aligned to the size 280 * of the DMCUB cache line, 64 bytes. 281 */ 282 283 stack->base = dmub_align(data->top, 256); 284 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 285 286 bios->base = dmub_align(stack->top, 256); 287 bios->top = bios->base + params->vbios_size; 288 289 mail->base = dmub_align(bios->top, 256); 290 mail->top = mail->base + DMUB_MAILBOX_SIZE; 291 292 fw_info = dmub_get_fw_meta_info(params); 293 294 if (fw_info) { 295 fw_state_size = fw_info->fw_region_size; 296 trace_buffer_size = fw_info->trace_buffer_size; 297 298 /** 299 * If DM didn't fill in a version, then fill it in based on 300 * the firmware meta now that we have it. 301 * 302 * TODO: Make it easier for driver to extract this out to 303 * pass during creation. 304 */ 305 if (dmub->fw_version == 0) 306 dmub->fw_version = fw_info->fw_version; 307 } 308 309 trace_buff->base = dmub_align(mail->top, 256); 310 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 311 312 fw_state->base = dmub_align(trace_buff->top, 256); 313 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 314 315 scratch_mem->base = dmub_align(fw_state->top, 256); 316 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 317 318 out->fb_size = dmub_align(scratch_mem->top, 4096); 319 320 return DMUB_STATUS_OK; 321 } 322 323 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 324 const struct dmub_srv_fb_params *params, 325 struct dmub_srv_fb_info *out) 326 { 327 uint8_t *cpu_base; 328 uint64_t gpu_base; 329 uint32_t i; 330 331 if (!dmub->sw_init) 332 return DMUB_STATUS_INVALID; 333 334 memset(out, 0, sizeof(*out)); 335 336 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 337 return DMUB_STATUS_INVALID; 338 339 cpu_base = (uint8_t *)params->cpu_addr; 340 gpu_base = params->gpu_addr; 341 342 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 343 const struct dmub_region *reg = 344 ¶ms->region_info->regions[i]; 345 346 out->fb[i].cpu_addr = cpu_base + reg->base; 347 out->fb[i].gpu_addr = gpu_base + reg->base; 348 out->fb[i].size = reg->top - reg->base; 349 } 350 351 out->num_fb = DMUB_NUM_WINDOWS; 352 353 return DMUB_STATUS_OK; 354 } 355 356 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 357 bool *is_supported) 358 { 359 *is_supported = false; 360 361 if (!dmub->sw_init) 362 return DMUB_STATUS_INVALID; 363 364 if (dmub->hw_funcs.is_supported) 365 *is_supported = dmub->hw_funcs.is_supported(dmub); 366 367 return DMUB_STATUS_OK; 368 } 369 370 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 371 { 372 *is_hw_init = false; 373 374 if (!dmub->sw_init) 375 return DMUB_STATUS_INVALID; 376 377 if (!dmub->hw_init) 378 return DMUB_STATUS_OK; 379 380 if (dmub->hw_funcs.is_hw_init) 381 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 382 383 return DMUB_STATUS_OK; 384 } 385 386 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 387 const struct dmub_srv_hw_params *params) 388 { 389 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 390 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 391 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 392 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 393 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 394 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 395 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 396 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 397 398 struct dmub_rb_init_params rb_params; 399 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 400 struct dmub_region inbox1; 401 402 if (!dmub->sw_init) 403 return DMUB_STATUS_INVALID; 404 405 dmub->fb_base = params->fb_base; 406 dmub->fb_offset = params->fb_offset; 407 dmub->psp_version = params->psp_version; 408 409 if (dmub->hw_funcs.reset) 410 dmub->hw_funcs.reset(dmub); 411 412 if (inst_fb && data_fb) { 413 cw0.offset.quad_part = inst_fb->gpu_addr; 414 cw0.region.base = DMUB_CW0_BASE; 415 cw0.region.top = cw0.region.base + inst_fb->size - 1; 416 417 cw1.offset.quad_part = stack_fb->gpu_addr; 418 cw1.region.base = DMUB_CW1_BASE; 419 cw1.region.top = cw1.region.base + stack_fb->size - 1; 420 421 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 422 /** 423 * Read back all the instruction memory so we don't hang the 424 * DMCUB when backdoor loading if the write from x86 hasn't been 425 * flushed yet. This only occurs in backdoor loading. 426 */ 427 dmub_flush_buffer_mem(inst_fb); 428 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 429 } 430 431 } 432 433 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 434 fw_state_fb && scratch_mem_fb) { 435 cw2.offset.quad_part = data_fb->gpu_addr; 436 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 437 cw2.region.top = cw2.region.base + data_fb->size; 438 439 cw3.offset.quad_part = bios_fb->gpu_addr; 440 cw3.region.base = DMUB_CW3_BASE; 441 cw3.region.top = cw3.region.base + bios_fb->size; 442 443 cw4.offset.quad_part = mail_fb->gpu_addr; 444 cw4.region.base = DMUB_CW4_BASE; 445 cw4.region.top = cw4.region.base + mail_fb->size; 446 447 inbox1.base = cw4.region.base; 448 inbox1.top = cw4.region.top; 449 450 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 451 cw5.region.base = DMUB_CW5_BASE; 452 cw5.region.top = cw5.region.base + tracebuff_fb->size; 453 454 cw6.offset.quad_part = fw_state_fb->gpu_addr; 455 cw6.region.base = DMUB_CW6_BASE; 456 cw6.region.top = cw6.region.base + fw_state_fb->size; 457 458 dmub->fw_state = fw_state_fb->cpu_addr; 459 460 dmub->scratch_mem_fb = *scratch_mem_fb; 461 462 if (dmub->hw_funcs.setup_windows) 463 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 464 &cw5, &cw6); 465 466 if (dmub->hw_funcs.setup_mailbox) 467 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 468 } 469 470 if (mail_fb) { 471 dmub_memset(&rb_params, 0, sizeof(rb_params)); 472 rb_params.ctx = dmub; 473 rb_params.base_address = mail_fb->cpu_addr; 474 rb_params.capacity = DMUB_RB_SIZE; 475 476 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 477 } 478 479 if (dmub->hw_funcs.reset_release) 480 dmub->hw_funcs.reset_release(dmub); 481 482 dmub->hw_init = true; 483 484 return DMUB_STATUS_OK; 485 } 486 487 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 488 { 489 if (!dmub->sw_init) 490 return DMUB_STATUS_INVALID; 491 492 if (dmub->hw_funcs.reset) 493 dmub->hw_funcs.reset(dmub); 494 495 dmub->hw_init = false; 496 497 return DMUB_STATUS_OK; 498 } 499 500 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 501 const union dmub_rb_cmd *cmd) 502 { 503 if (!dmub->hw_init) 504 return DMUB_STATUS_INVALID; 505 506 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 507 return DMUB_STATUS_OK; 508 509 return DMUB_STATUS_QUEUE_FULL; 510 } 511 512 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 513 { 514 if (!dmub->hw_init) 515 return DMUB_STATUS_INVALID; 516 517 /** 518 * Read back all the queued commands to ensure that they've 519 * been flushed to framebuffer memory. Otherwise DMCUB might 520 * read back stale, fully invalid or partially invalid data. 521 */ 522 dmub_rb_flush_pending(&dmub->inbox1_rb); 523 524 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 525 return DMUB_STATUS_OK; 526 } 527 528 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 529 uint32_t timeout_us) 530 { 531 uint32_t i; 532 533 if (!dmub->hw_init) 534 return DMUB_STATUS_INVALID; 535 536 for (i = 0; i <= timeout_us; i += 100) { 537 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 538 539 if (status.bits.dal_fw && status.bits.mailbox_rdy) 540 return DMUB_STATUS_OK; 541 542 udelay(100); 543 } 544 545 return DMUB_STATUS_TIMEOUT; 546 } 547 548 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 549 uint32_t timeout_us) 550 { 551 uint32_t i = 0; 552 553 if (!dmub->hw_init) 554 return DMUB_STATUS_INVALID; 555 556 if (!dmub->hw_funcs.is_phy_init) 557 return DMUB_STATUS_OK; 558 559 for (i = 0; i <= timeout_us; i += 10) { 560 if (dmub->hw_funcs.is_phy_init(dmub)) 561 return DMUB_STATUS_OK; 562 563 udelay(10); 564 } 565 566 return DMUB_STATUS_TIMEOUT; 567 } 568 569 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 570 uint32_t timeout_us) 571 { 572 uint32_t i; 573 574 if (!dmub->hw_init) 575 return DMUB_STATUS_INVALID; 576 577 for (i = 0; i <= timeout_us; ++i) { 578 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 579 if (dmub_rb_empty(&dmub->inbox1_rb)) 580 return DMUB_STATUS_OK; 581 582 udelay(1); 583 } 584 585 return DMUB_STATUS_TIMEOUT; 586 } 587 588 enum dmub_status 589 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 590 enum dmub_gpint_command command_code, 591 uint16_t param, uint32_t timeout_us) 592 { 593 union dmub_gpint_data_register reg; 594 uint32_t i; 595 596 if (!dmub->sw_init) 597 return DMUB_STATUS_INVALID; 598 599 if (!dmub->hw_funcs.set_gpint) 600 return DMUB_STATUS_INVALID; 601 602 if (!dmub->hw_funcs.is_gpint_acked) 603 return DMUB_STATUS_INVALID; 604 605 reg.bits.status = 1; 606 reg.bits.command_code = command_code; 607 reg.bits.param = param; 608 609 dmub->hw_funcs.set_gpint(dmub, reg); 610 611 for (i = 0; i < timeout_us; ++i) { 612 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 613 return DMUB_STATUS_OK; 614 } 615 616 return DMUB_STATUS_TIMEOUT; 617 } 618 619 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 620 uint32_t *response) 621 { 622 *response = 0; 623 624 if (!dmub->sw_init) 625 return DMUB_STATUS_INVALID; 626 627 if (!dmub->hw_funcs.get_gpint_response) 628 return DMUB_STATUS_INVALID; 629 630 *response = dmub->hw_funcs.get_gpint_response(dmub); 631 632 return DMUB_STATUS_OK; 633 } 634 635 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 636 union dmub_fw_boot_status *status) 637 { 638 status->all = 0; 639 640 if (!dmub->sw_init) 641 return DMUB_STATUS_INVALID; 642 643 if (dmub->hw_funcs.get_fw_status) 644 *status = dmub->hw_funcs.get_fw_status(dmub); 645 646 return DMUB_STATUS_OK; 647 } 648 649 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 650 union dmub_rb_cmd *cmd) 651 { 652 enum dmub_status status = DMUB_STATUS_OK; 653 654 // Queue command 655 status = dmub_srv_cmd_queue(dmub, cmd); 656 657 if (status != DMUB_STATUS_OK) 658 return status; 659 660 // Execute command 661 status = dmub_srv_cmd_execute(dmub); 662 663 if (status != DMUB_STATUS_OK) 664 return status; 665 666 // Wait for DMUB to process command 667 status = dmub_srv_wait_for_idle(dmub, 100000); 668 669 if (status != DMUB_STATUS_OK) 670 return status; 671 672 // Copy data back from ring buffer into command 673 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 674 675 return status; 676 } 677