1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn315.h" 36 #include "dmub_dcn316.h" 37 #include "dmub_dcn32.h" 38 #include "os_types.h" 39 /* 40 * Note: the DMUB service is standalone. No additional headers should be 41 * added below or above this line unless they reside within the DMUB 42 * folder. 43 */ 44 45 /* Alignment for framebuffer memory. */ 46 #define DMUB_FB_ALIGNMENT (1024 * 1024) 47 48 /* Stack size. */ 49 #define DMUB_STACK_SIZE (128 * 1024) 50 51 /* Context size. */ 52 #define DMUB_CONTEXT_SIZE (512 * 1024) 53 54 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 55 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 56 57 /* Default state size if meta is absent. */ 58 #define DMUB_FW_STATE_SIZE (64 * 1024) 59 60 /* Default tracebuffer size if meta is absent. */ 61 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 62 63 64 /* Default scratch mem size. */ 65 #define DMUB_SCRATCH_MEM_SIZE (256) 66 67 /* Number of windows in use. */ 68 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 69 /* Base addresses. */ 70 71 #define DMUB_CW0_BASE (0x60000000) 72 #define DMUB_CW1_BASE (0x61000000) 73 #define DMUB_CW3_BASE (0x63000000) 74 #define DMUB_CW4_BASE (0x64000000) 75 #define DMUB_CW5_BASE (0x65000000) 76 #define DMUB_CW6_BASE (0x66000000) 77 78 #define DMUB_REGION5_BASE (0xA0000000) 79 80 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 81 { 82 return (val + factor - 1) / factor * factor; 83 } 84 85 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 86 { 87 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 88 uint8_t buf[64]; 89 uint32_t pos, end; 90 91 /** 92 * Read 64-byte chunks since we don't want to store a 93 * large temporary buffer for this purpose. 94 */ 95 end = fb->size / sizeof(buf) * sizeof(buf); 96 97 for (pos = 0; pos < end; pos += sizeof(buf)) 98 dmub_memcpy(buf, base + pos, sizeof(buf)); 99 100 /* Read anything leftover into the buffer. */ 101 if (end < fb->size) 102 dmub_memcpy(buf, base + pos, fb->size - end); 103 } 104 105 static const struct dmub_fw_meta_info * 106 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 107 { 108 const union dmub_fw_meta *meta; 109 110 if (!blob || !blob_size) 111 return NULL; 112 113 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 114 return NULL; 115 116 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 117 sizeof(union dmub_fw_meta)); 118 119 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 120 return NULL; 121 122 return &meta->info; 123 } 124 125 static const struct dmub_fw_meta_info * 126 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 127 { 128 const struct dmub_fw_meta_info *info = NULL; 129 130 if (params->fw_bss_data && params->bss_data_size) { 131 /* Legacy metadata region. */ 132 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 133 params->bss_data_size, 134 DMUB_FW_META_OFFSET); 135 } else if (params->fw_inst_const && params->inst_const_size) { 136 /* Combined metadata region - can be aligned to 16-bytes. */ 137 uint32_t i; 138 139 for (i = 0; i < 16; ++i) { 140 info = dmub_get_fw_meta_info_from_blob( 141 params->fw_inst_const, params->inst_const_size, i); 142 143 if (info) 144 break; 145 } 146 } 147 148 return info; 149 } 150 151 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 152 { 153 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 154 155 switch (asic) { 156 case DMUB_ASIC_DCN20: 157 case DMUB_ASIC_DCN21: 158 case DMUB_ASIC_DCN30: 159 case DMUB_ASIC_DCN301: 160 case DMUB_ASIC_DCN302: 161 case DMUB_ASIC_DCN303: 162 dmub->regs = &dmub_srv_dcn20_regs; 163 164 funcs->reset = dmub_dcn20_reset; 165 funcs->reset_release = dmub_dcn20_reset_release; 166 funcs->backdoor_load = dmub_dcn20_backdoor_load; 167 funcs->setup_windows = dmub_dcn20_setup_windows; 168 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 169 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 170 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 171 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 172 funcs->is_supported = dmub_dcn20_is_supported; 173 funcs->is_hw_init = dmub_dcn20_is_hw_init; 174 funcs->set_gpint = dmub_dcn20_set_gpint; 175 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 176 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 177 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 178 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 179 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 180 funcs->get_current_time = dmub_dcn20_get_current_time; 181 182 // Out mailbox register access functions for RN and above 183 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 184 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 185 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 186 187 //outbox0 call stacks 188 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 189 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 190 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 191 192 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 193 194 if (asic == DMUB_ASIC_DCN21) 195 dmub->regs = &dmub_srv_dcn21_regs; 196 197 if (asic == DMUB_ASIC_DCN30) { 198 dmub->regs = &dmub_srv_dcn30_regs; 199 200 funcs->backdoor_load = dmub_dcn30_backdoor_load; 201 funcs->setup_windows = dmub_dcn30_setup_windows; 202 } 203 if (asic == DMUB_ASIC_DCN301) { 204 dmub->regs = &dmub_srv_dcn301_regs; 205 206 funcs->backdoor_load = dmub_dcn30_backdoor_load; 207 funcs->setup_windows = dmub_dcn30_setup_windows; 208 } 209 if (asic == DMUB_ASIC_DCN302) { 210 dmub->regs = &dmub_srv_dcn302_regs; 211 212 funcs->backdoor_load = dmub_dcn30_backdoor_load; 213 funcs->setup_windows = dmub_dcn30_setup_windows; 214 } 215 if (asic == DMUB_ASIC_DCN303) { 216 dmub->regs = &dmub_srv_dcn303_regs; 217 218 funcs->backdoor_load = dmub_dcn30_backdoor_load; 219 funcs->setup_windows = dmub_dcn30_setup_windows; 220 } 221 break; 222 223 case DMUB_ASIC_DCN31: 224 case DMUB_ASIC_DCN31B: 225 case DMUB_ASIC_DCN314: 226 case DMUB_ASIC_DCN315: 227 case DMUB_ASIC_DCN316: 228 if (asic == DMUB_ASIC_DCN315) 229 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 230 else if (asic == DMUB_ASIC_DCN316) 231 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 232 else 233 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 234 funcs->reset = dmub_dcn31_reset; 235 funcs->reset_release = dmub_dcn31_reset_release; 236 funcs->backdoor_load = dmub_dcn31_backdoor_load; 237 funcs->setup_windows = dmub_dcn31_setup_windows; 238 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 239 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 240 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 241 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 242 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 243 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 244 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 245 funcs->is_supported = dmub_dcn31_is_supported; 246 funcs->is_hw_init = dmub_dcn31_is_hw_init; 247 funcs->set_gpint = dmub_dcn31_set_gpint; 248 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 249 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 250 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 251 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 252 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 253 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 254 //outbox0 call stacks 255 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 256 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 257 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 258 259 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 260 funcs->should_detect = dmub_dcn31_should_detect; 261 funcs->get_current_time = dmub_dcn31_get_current_time; 262 263 break; 264 265 case DMUB_ASIC_DCN32: 266 case DMUB_ASIC_DCN321: 267 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 268 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 269 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 270 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 271 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 272 funcs->reset = dmub_dcn32_reset; 273 funcs->reset_release = dmub_dcn32_reset_release; 274 funcs->backdoor_load = dmub_dcn32_backdoor_load; 275 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 276 funcs->setup_windows = dmub_dcn32_setup_windows; 277 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 278 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 279 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 280 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 281 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 282 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 283 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 284 funcs->is_supported = dmub_dcn32_is_supported; 285 funcs->is_hw_init = dmub_dcn32_is_hw_init; 286 funcs->set_gpint = dmub_dcn32_set_gpint; 287 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 288 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 289 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 290 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 291 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 292 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 293 294 /* outbox0 call stacks */ 295 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 296 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 297 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 298 funcs->get_current_time = dmub_dcn32_get_current_time; 299 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 300 301 break; 302 303 default: 304 return false; 305 } 306 307 return true; 308 } 309 310 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 311 const struct dmub_srv_create_params *params) 312 { 313 enum dmub_status status = DMUB_STATUS_OK; 314 315 dmub_memset(dmub, 0, sizeof(*dmub)); 316 317 dmub->funcs = params->funcs; 318 dmub->user_ctx = params->user_ctx; 319 dmub->asic = params->asic; 320 dmub->fw_version = params->fw_version; 321 dmub->is_virtual = params->is_virtual; 322 323 /* Setup asic dependent hardware funcs. */ 324 if (!dmub_srv_hw_setup(dmub, params->asic)) { 325 status = DMUB_STATUS_INVALID; 326 goto cleanup; 327 } 328 329 /* Override (some) hardware funcs based on user params. */ 330 if (params->hw_funcs) { 331 if (params->hw_funcs->emul_get_inbox1_rptr) 332 dmub->hw_funcs.emul_get_inbox1_rptr = 333 params->hw_funcs->emul_get_inbox1_rptr; 334 335 if (params->hw_funcs->emul_set_inbox1_wptr) 336 dmub->hw_funcs.emul_set_inbox1_wptr = 337 params->hw_funcs->emul_set_inbox1_wptr; 338 339 if (params->hw_funcs->is_supported) 340 dmub->hw_funcs.is_supported = 341 params->hw_funcs->is_supported; 342 } 343 344 /* Sanity checks for required hw func pointers. */ 345 if (!dmub->hw_funcs.get_inbox1_rptr || 346 !dmub->hw_funcs.set_inbox1_wptr) { 347 status = DMUB_STATUS_INVALID; 348 goto cleanup; 349 } 350 351 cleanup: 352 if (status == DMUB_STATUS_OK) 353 dmub->sw_init = true; 354 else 355 dmub_srv_destroy(dmub); 356 357 return status; 358 } 359 360 void dmub_srv_destroy(struct dmub_srv *dmub) 361 { 362 dmub_memset(dmub, 0, sizeof(*dmub)); 363 } 364 365 enum dmub_status 366 dmub_srv_calc_region_info(struct dmub_srv *dmub, 367 const struct dmub_srv_region_params *params, 368 struct dmub_srv_region_info *out) 369 { 370 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 371 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 372 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 373 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 374 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 375 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 376 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 377 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 378 const struct dmub_fw_meta_info *fw_info; 379 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 380 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 381 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 382 383 if (!dmub->sw_init) 384 return DMUB_STATUS_INVALID; 385 386 memset(out, 0, sizeof(*out)); 387 388 out->num_regions = DMUB_NUM_WINDOWS; 389 390 inst->base = 0x0; 391 inst->top = inst->base + params->inst_const_size; 392 393 data->base = dmub_align(inst->top, 256); 394 data->top = data->base + params->bss_data_size; 395 396 /* 397 * All cache windows below should be aligned to the size 398 * of the DMCUB cache line, 64 bytes. 399 */ 400 401 stack->base = dmub_align(data->top, 256); 402 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 403 404 bios->base = dmub_align(stack->top, 256); 405 bios->top = bios->base + params->vbios_size; 406 407 mail->base = dmub_align(bios->top, 256); 408 mail->top = mail->base + DMUB_MAILBOX_SIZE; 409 410 fw_info = dmub_get_fw_meta_info(params); 411 412 if (fw_info) { 413 fw_state_size = fw_info->fw_region_size; 414 trace_buffer_size = fw_info->trace_buffer_size; 415 416 /** 417 * If DM didn't fill in a version, then fill it in based on 418 * the firmware meta now that we have it. 419 * 420 * TODO: Make it easier for driver to extract this out to 421 * pass during creation. 422 */ 423 if (dmub->fw_version == 0) 424 dmub->fw_version = fw_info->fw_version; 425 } 426 427 trace_buff->base = dmub_align(mail->top, 256); 428 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 429 430 fw_state->base = dmub_align(trace_buff->top, 256); 431 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 432 433 scratch_mem->base = dmub_align(fw_state->top, 256); 434 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 435 436 out->fb_size = dmub_align(scratch_mem->top, 4096); 437 438 return DMUB_STATUS_OK; 439 } 440 441 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 442 const struct dmub_srv_fb_params *params, 443 struct dmub_srv_fb_info *out) 444 { 445 uint8_t *cpu_base; 446 uint64_t gpu_base; 447 uint32_t i; 448 449 if (!dmub->sw_init) 450 return DMUB_STATUS_INVALID; 451 452 memset(out, 0, sizeof(*out)); 453 454 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 455 return DMUB_STATUS_INVALID; 456 457 cpu_base = (uint8_t *)params->cpu_addr; 458 gpu_base = params->gpu_addr; 459 460 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 461 const struct dmub_region *reg = 462 ¶ms->region_info->regions[i]; 463 464 out->fb[i].cpu_addr = cpu_base + reg->base; 465 out->fb[i].gpu_addr = gpu_base + reg->base; 466 out->fb[i].size = reg->top - reg->base; 467 } 468 469 out->num_fb = DMUB_NUM_WINDOWS; 470 471 return DMUB_STATUS_OK; 472 } 473 474 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 475 bool *is_supported) 476 { 477 *is_supported = false; 478 479 if (!dmub->sw_init) 480 return DMUB_STATUS_INVALID; 481 482 if (dmub->hw_funcs.is_supported) 483 *is_supported = dmub->hw_funcs.is_supported(dmub); 484 485 return DMUB_STATUS_OK; 486 } 487 488 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 489 { 490 *is_hw_init = false; 491 492 if (!dmub->sw_init) 493 return DMUB_STATUS_INVALID; 494 495 if (!dmub->hw_init) 496 return DMUB_STATUS_OK; 497 498 if (dmub->hw_funcs.is_hw_init) 499 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 500 501 return DMUB_STATUS_OK; 502 } 503 504 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 505 const struct dmub_srv_hw_params *params) 506 { 507 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 508 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 509 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 510 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 511 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 512 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 513 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 514 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 515 516 struct dmub_rb_init_params rb_params, outbox0_rb_params; 517 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 518 struct dmub_region inbox1, outbox1, outbox0; 519 520 if (!dmub->sw_init) 521 return DMUB_STATUS_INVALID; 522 523 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 524 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 525 ASSERT(0); 526 return DMUB_STATUS_INVALID; 527 } 528 529 dmub->fb_base = params->fb_base; 530 dmub->fb_offset = params->fb_offset; 531 dmub->psp_version = params->psp_version; 532 533 if (dmub->hw_funcs.reset) 534 dmub->hw_funcs.reset(dmub); 535 536 /* reset the cache of the last wptr as well now that hw is reset */ 537 dmub->inbox1_last_wptr = 0; 538 539 cw0.offset.quad_part = inst_fb->gpu_addr; 540 cw0.region.base = DMUB_CW0_BASE; 541 cw0.region.top = cw0.region.base + inst_fb->size - 1; 542 543 cw1.offset.quad_part = stack_fb->gpu_addr; 544 cw1.region.base = DMUB_CW1_BASE; 545 cw1.region.top = cw1.region.base + stack_fb->size - 1; 546 547 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 548 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 549 550 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 551 /** 552 * Read back all the instruction memory so we don't hang the 553 * DMCUB when backdoor loading if the write from x86 hasn't been 554 * flushed yet. This only occurs in backdoor loading. 555 */ 556 dmub_flush_buffer_mem(inst_fb); 557 558 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 559 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 560 else 561 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 562 } 563 564 cw2.offset.quad_part = data_fb->gpu_addr; 565 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 566 cw2.region.top = cw2.region.base + data_fb->size; 567 568 cw3.offset.quad_part = bios_fb->gpu_addr; 569 cw3.region.base = DMUB_CW3_BASE; 570 cw3.region.top = cw3.region.base + bios_fb->size; 571 572 cw4.offset.quad_part = mail_fb->gpu_addr; 573 cw4.region.base = DMUB_CW4_BASE; 574 cw4.region.top = cw4.region.base + mail_fb->size; 575 576 /** 577 * Doubled the mailbox region to accomodate inbox and outbox. 578 * Note: Currently, currently total mailbox size is 16KB. It is split 579 * equally into 8KB between inbox and outbox. If this config is 580 * changed, then uncached base address configuration of outbox1 581 * has to be updated in funcs->setup_out_mailbox. 582 */ 583 inbox1.base = cw4.region.base; 584 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 585 outbox1.base = inbox1.top; 586 outbox1.top = cw4.region.top; 587 588 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 589 cw5.region.base = DMUB_CW5_BASE; 590 cw5.region.top = cw5.region.base + tracebuff_fb->size; 591 592 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 593 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 594 595 cw6.offset.quad_part = fw_state_fb->gpu_addr; 596 cw6.region.base = DMUB_CW6_BASE; 597 cw6.region.top = cw6.region.base + fw_state_fb->size; 598 599 dmub->fw_state = fw_state_fb->cpu_addr; 600 601 dmub->scratch_mem_fb = *scratch_mem_fb; 602 603 if (dmub->hw_funcs.setup_windows) 604 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 605 606 if (dmub->hw_funcs.setup_outbox0) 607 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 608 609 if (dmub->hw_funcs.setup_mailbox) 610 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 611 if (dmub->hw_funcs.setup_out_mailbox) 612 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 613 614 dmub_memset(&rb_params, 0, sizeof(rb_params)); 615 rb_params.ctx = dmub; 616 rb_params.base_address = mail_fb->cpu_addr; 617 rb_params.capacity = DMUB_RB_SIZE; 618 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 619 620 // Initialize outbox1 ring buffer 621 rb_params.ctx = dmub; 622 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 623 rb_params.capacity = DMUB_RB_SIZE; 624 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 625 626 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 627 outbox0_rb_params.ctx = dmub; 628 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 629 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 630 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 631 632 /* Report to DMUB what features are supported by current driver */ 633 if (dmub->hw_funcs.enable_dmub_boot_options) 634 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 635 636 if (dmub->hw_funcs.skip_dmub_panel_power_sequence) 637 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 638 params->skip_panel_power_sequence); 639 640 if (dmub->hw_funcs.reset_release) 641 dmub->hw_funcs.reset_release(dmub); 642 643 dmub->hw_init = true; 644 645 return DMUB_STATUS_OK; 646 } 647 648 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 649 { 650 if (!dmub->sw_init) 651 return DMUB_STATUS_INVALID; 652 653 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 654 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 655 dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 656 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 657 } 658 659 return DMUB_STATUS_OK; 660 } 661 662 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 663 { 664 if (!dmub->sw_init) 665 return DMUB_STATUS_INVALID; 666 667 if (dmub->hw_funcs.reset) 668 dmub->hw_funcs.reset(dmub); 669 670 /* mailboxes have been reset in hw, so reset the sw state as well */ 671 dmub->inbox1_last_wptr = 0; 672 dmub->inbox1_rb.wrpt = 0; 673 dmub->inbox1_rb.rptr = 0; 674 dmub->outbox0_rb.wrpt = 0; 675 dmub->outbox0_rb.rptr = 0; 676 dmub->outbox1_rb.wrpt = 0; 677 dmub->outbox1_rb.rptr = 0; 678 679 dmub->hw_init = false; 680 681 return DMUB_STATUS_OK; 682 } 683 684 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 685 const union dmub_rb_cmd *cmd) 686 { 687 if (!dmub->hw_init) 688 return DMUB_STATUS_INVALID; 689 690 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 691 return DMUB_STATUS_OK; 692 693 return DMUB_STATUS_QUEUE_FULL; 694 } 695 696 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 697 { 698 struct dmub_rb flush_rb; 699 700 if (!dmub->hw_init) 701 return DMUB_STATUS_INVALID; 702 703 /** 704 * Read back all the queued commands to ensure that they've 705 * been flushed to framebuffer memory. Otherwise DMCUB might 706 * read back stale, fully invalid or partially invalid data. 707 */ 708 flush_rb = dmub->inbox1_rb; 709 flush_rb.rptr = dmub->inbox1_last_wptr; 710 dmub_rb_flush_pending(&flush_rb); 711 712 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 713 714 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 715 716 return DMUB_STATUS_OK; 717 } 718 719 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 720 uint32_t timeout_us) 721 { 722 uint32_t i; 723 724 if (!dmub->hw_init) 725 return DMUB_STATUS_INVALID; 726 727 for (i = 0; i <= timeout_us; i += 100) { 728 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 729 730 if (status.bits.dal_fw && status.bits.mailbox_rdy) 731 return DMUB_STATUS_OK; 732 733 udelay(100); 734 } 735 736 return DMUB_STATUS_TIMEOUT; 737 } 738 739 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 740 uint32_t timeout_us) 741 { 742 uint32_t i, rptr; 743 744 if (!dmub->hw_init) 745 return DMUB_STATUS_INVALID; 746 747 for (i = 0; i <= timeout_us; ++i) { 748 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 749 750 if (rptr > dmub->inbox1_rb.capacity) 751 return DMUB_STATUS_HW_FAILURE; 752 753 dmub->inbox1_rb.rptr = rptr; 754 755 if (dmub_rb_empty(&dmub->inbox1_rb)) 756 return DMUB_STATUS_OK; 757 758 udelay(1); 759 } 760 761 return DMUB_STATUS_TIMEOUT; 762 } 763 764 enum dmub_status 765 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 766 enum dmub_gpint_command command_code, 767 uint16_t param, uint32_t timeout_us) 768 { 769 union dmub_gpint_data_register reg; 770 uint32_t i; 771 772 if (!dmub->sw_init) 773 return DMUB_STATUS_INVALID; 774 775 if (!dmub->hw_funcs.set_gpint) 776 return DMUB_STATUS_INVALID; 777 778 if (!dmub->hw_funcs.is_gpint_acked) 779 return DMUB_STATUS_INVALID; 780 781 reg.bits.status = 1; 782 reg.bits.command_code = command_code; 783 reg.bits.param = param; 784 785 dmub->hw_funcs.set_gpint(dmub, reg); 786 787 for (i = 0; i < timeout_us; ++i) { 788 udelay(1); 789 790 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 791 return DMUB_STATUS_OK; 792 } 793 794 return DMUB_STATUS_TIMEOUT; 795 } 796 797 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 798 uint32_t *response) 799 { 800 *response = 0; 801 802 if (!dmub->sw_init) 803 return DMUB_STATUS_INVALID; 804 805 if (!dmub->hw_funcs.get_gpint_response) 806 return DMUB_STATUS_INVALID; 807 808 *response = dmub->hw_funcs.get_gpint_response(dmub); 809 810 return DMUB_STATUS_OK; 811 } 812 813 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 814 uint32_t *dataout) 815 { 816 *dataout = 0; 817 818 if (!dmub->sw_init) 819 return DMUB_STATUS_INVALID; 820 821 if (!dmub->hw_funcs.get_gpint_dataout) 822 return DMUB_STATUS_INVALID; 823 824 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 825 826 return DMUB_STATUS_OK; 827 } 828 829 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 830 union dmub_fw_boot_status *status) 831 { 832 status->all = 0; 833 834 if (!dmub->sw_init) 835 return DMUB_STATUS_INVALID; 836 837 if (dmub->hw_funcs.get_fw_status) 838 *status = dmub->hw_funcs.get_fw_status(dmub); 839 840 return DMUB_STATUS_OK; 841 } 842 843 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 844 union dmub_rb_cmd *cmd) 845 { 846 enum dmub_status status = DMUB_STATUS_OK; 847 848 // Queue command 849 status = dmub_srv_cmd_queue(dmub, cmd); 850 851 if (status != DMUB_STATUS_OK) 852 return status; 853 854 // Execute command 855 status = dmub_srv_cmd_execute(dmub); 856 857 if (status != DMUB_STATUS_OK) 858 return status; 859 860 // Wait for DMUB to process command 861 status = dmub_srv_wait_for_idle(dmub, 100000); 862 863 if (status != DMUB_STATUS_OK) 864 return status; 865 866 // Copy data back from ring buffer into command 867 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 868 869 return status; 870 } 871 872 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 873 void *entry) 874 { 875 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 876 uint64_t *dst = (uint64_t *)entry; 877 uint8_t i; 878 uint8_t loop_count; 879 880 if (rb->rptr == rb->wrpt) 881 return false; 882 883 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 884 // copying data 885 for (i = 0; i < loop_count; i++) 886 *dst++ = *src++; 887 888 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 889 890 rb->rptr %= rb->capacity; 891 892 return true; 893 } 894 895 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 896 { 897 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 898 899 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 900 } 901 902 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 903 { 904 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 905 return false; 906 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 907 return true; 908 } 909 910 bool dmub_srv_should_detect(struct dmub_srv *dmub) 911 { 912 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 913 return false; 914 915 return dmub->hw_funcs.should_detect(dmub); 916 } 917 918 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 919 { 920 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 921 return DMUB_STATUS_INVALID; 922 923 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 924 return DMUB_STATUS_OK; 925 } 926 927 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 928 { 929 uint32_t i = 0; 930 uint32_t ack = 0; 931 932 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 933 return DMUB_STATUS_INVALID; 934 935 for (i = 0; i <= timeout_us; i++) { 936 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 937 if (ack) 938 return DMUB_STATUS_OK; 939 } 940 return DMUB_STATUS_TIMEOUT; 941 } 942 943 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 944 union dmub_inbox0_data_register data) 945 { 946 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 947 return DMUB_STATUS_INVALID; 948 949 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 950 return DMUB_STATUS_OK; 951 } 952