1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn315.h" 36 #include "dmub_dcn316.h" 37 #include "dmub_dcn32.h" 38 #include "os_types.h" 39 /* 40 * Note: the DMUB service is standalone. No additional headers should be 41 * added below or above this line unless they reside within the DMUB 42 * folder. 43 */ 44 45 /* Alignment for framebuffer memory. */ 46 #define DMUB_FB_ALIGNMENT (1024 * 1024) 47 48 /* Stack size. */ 49 #define DMUB_STACK_SIZE (128 * 1024) 50 51 /* Context size. */ 52 #define DMUB_CONTEXT_SIZE (512 * 1024) 53 54 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 55 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 56 57 /* Default state size if meta is absent. */ 58 #define DMUB_FW_STATE_SIZE (64 * 1024) 59 60 /* Default tracebuffer size if meta is absent. */ 61 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 62 63 64 /* Default scratch mem size. */ 65 #define DMUB_SCRATCH_MEM_SIZE (256) 66 67 /* Number of windows in use. */ 68 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 69 /* Base addresses. */ 70 71 #define DMUB_CW0_BASE (0x60000000) 72 #define DMUB_CW1_BASE (0x61000000) 73 #define DMUB_CW3_BASE (0x63000000) 74 #define DMUB_CW4_BASE (0x64000000) 75 #define DMUB_CW5_BASE (0x65000000) 76 #define DMUB_CW6_BASE (0x66000000) 77 78 #define DMUB_REGION5_BASE (0xA0000000) 79 80 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 81 { 82 return (val + factor - 1) / factor * factor; 83 } 84 85 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 86 { 87 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 88 uint8_t buf[64]; 89 uint32_t pos, end; 90 91 /** 92 * Read 64-byte chunks since we don't want to store a 93 * large temporary buffer for this purpose. 94 */ 95 end = fb->size / sizeof(buf) * sizeof(buf); 96 97 for (pos = 0; pos < end; pos += sizeof(buf)) 98 dmub_memcpy(buf, base + pos, sizeof(buf)); 99 100 /* Read anything leftover into the buffer. */ 101 if (end < fb->size) 102 dmub_memcpy(buf, base + pos, fb->size - end); 103 } 104 105 static const struct dmub_fw_meta_info * 106 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 107 { 108 const union dmub_fw_meta *meta; 109 110 if (!blob || !blob_size) 111 return NULL; 112 113 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 114 return NULL; 115 116 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 117 sizeof(union dmub_fw_meta)); 118 119 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 120 return NULL; 121 122 return &meta->info; 123 } 124 125 static const struct dmub_fw_meta_info * 126 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 127 { 128 const struct dmub_fw_meta_info *info = NULL; 129 130 if (params->fw_bss_data && params->bss_data_size) { 131 /* Legacy metadata region. */ 132 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 133 params->bss_data_size, 134 DMUB_FW_META_OFFSET); 135 } else if (params->fw_inst_const && params->inst_const_size) { 136 /* Combined metadata region - can be aligned to 16-bytes. */ 137 uint32_t i; 138 139 for (i = 0; i < 16; ++i) { 140 info = dmub_get_fw_meta_info_from_blob( 141 params->fw_inst_const, params->inst_const_size, i); 142 143 if (info) 144 break; 145 } 146 } 147 148 return info; 149 } 150 151 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 152 { 153 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 154 155 switch (asic) { 156 case DMUB_ASIC_DCN20: 157 case DMUB_ASIC_DCN21: 158 case DMUB_ASIC_DCN30: 159 case DMUB_ASIC_DCN301: 160 case DMUB_ASIC_DCN302: 161 case DMUB_ASIC_DCN303: 162 dmub->regs = &dmub_srv_dcn20_regs; 163 164 funcs->reset = dmub_dcn20_reset; 165 funcs->reset_release = dmub_dcn20_reset_release; 166 funcs->backdoor_load = dmub_dcn20_backdoor_load; 167 funcs->setup_windows = dmub_dcn20_setup_windows; 168 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 169 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 170 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 171 funcs->is_supported = dmub_dcn20_is_supported; 172 funcs->is_hw_init = dmub_dcn20_is_hw_init; 173 funcs->set_gpint = dmub_dcn20_set_gpint; 174 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 175 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 176 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 177 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 178 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 179 funcs->get_current_time = dmub_dcn20_get_current_time; 180 181 // Out mailbox register access functions for RN and above 182 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 183 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 184 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 185 186 //outbox0 call stacks 187 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 188 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 189 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 190 191 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 192 193 if (asic == DMUB_ASIC_DCN21) { 194 dmub->regs = &dmub_srv_dcn21_regs; 195 196 funcs->is_phy_init = dmub_dcn21_is_phy_init; 197 } 198 if (asic == DMUB_ASIC_DCN30) { 199 dmub->regs = &dmub_srv_dcn30_regs; 200 201 funcs->backdoor_load = dmub_dcn30_backdoor_load; 202 funcs->setup_windows = dmub_dcn30_setup_windows; 203 } 204 if (asic == DMUB_ASIC_DCN301) { 205 dmub->regs = &dmub_srv_dcn301_regs; 206 207 funcs->backdoor_load = dmub_dcn30_backdoor_load; 208 funcs->setup_windows = dmub_dcn30_setup_windows; 209 } 210 if (asic == DMUB_ASIC_DCN302) { 211 dmub->regs = &dmub_srv_dcn302_regs; 212 213 funcs->backdoor_load = dmub_dcn30_backdoor_load; 214 funcs->setup_windows = dmub_dcn30_setup_windows; 215 } 216 if (asic == DMUB_ASIC_DCN303) { 217 dmub->regs = &dmub_srv_dcn303_regs; 218 219 funcs->backdoor_load = dmub_dcn30_backdoor_load; 220 funcs->setup_windows = dmub_dcn30_setup_windows; 221 } 222 break; 223 224 case DMUB_ASIC_DCN31: 225 case DMUB_ASIC_DCN31B: 226 case DMUB_ASIC_DCN315: 227 case DMUB_ASIC_DCN316: 228 if (asic == DMUB_ASIC_DCN315) 229 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 230 else if (asic == DMUB_ASIC_DCN316) 231 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 232 else 233 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 234 funcs->reset = dmub_dcn31_reset; 235 funcs->reset_release = dmub_dcn31_reset_release; 236 funcs->backdoor_load = dmub_dcn31_backdoor_load; 237 funcs->setup_windows = dmub_dcn31_setup_windows; 238 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 239 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 240 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 241 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 242 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 243 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 244 funcs->is_supported = dmub_dcn31_is_supported; 245 funcs->is_hw_init = dmub_dcn31_is_hw_init; 246 funcs->set_gpint = dmub_dcn31_set_gpint; 247 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 248 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 249 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 250 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 251 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 252 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 253 //outbox0 call stacks 254 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 255 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 256 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 257 258 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 259 funcs->should_detect = dmub_dcn31_should_detect; 260 funcs->get_current_time = dmub_dcn31_get_current_time; 261 262 break; 263 264 case DMUB_ASIC_DCN32: 265 case DMUB_ASIC_DCN321: 266 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 267 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 268 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 269 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 270 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 271 funcs->reset = dmub_dcn32_reset; 272 funcs->reset_release = dmub_dcn32_reset_release; 273 funcs->backdoor_load = dmub_dcn32_backdoor_load; 274 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 275 funcs->setup_windows = dmub_dcn32_setup_windows; 276 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 277 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 278 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 279 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 280 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 281 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 282 funcs->is_supported = dmub_dcn32_is_supported; 283 funcs->is_hw_init = dmub_dcn32_is_hw_init; 284 funcs->set_gpint = dmub_dcn32_set_gpint; 285 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 286 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 287 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 288 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 289 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 290 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 291 292 /* outbox0 call stacks */ 293 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 294 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 295 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 296 funcs->get_current_time = dmub_dcn32_get_current_time; 297 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 298 299 break; 300 301 default: 302 return false; 303 } 304 305 return true; 306 } 307 308 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 309 const struct dmub_srv_create_params *params) 310 { 311 enum dmub_status status = DMUB_STATUS_OK; 312 313 dmub_memset(dmub, 0, sizeof(*dmub)); 314 315 dmub->funcs = params->funcs; 316 dmub->user_ctx = params->user_ctx; 317 dmub->asic = params->asic; 318 dmub->fw_version = params->fw_version; 319 dmub->is_virtual = params->is_virtual; 320 321 /* Setup asic dependent hardware funcs. */ 322 if (!dmub_srv_hw_setup(dmub, params->asic)) { 323 status = DMUB_STATUS_INVALID; 324 goto cleanup; 325 } 326 327 /* Override (some) hardware funcs based on user params. */ 328 if (params->hw_funcs) { 329 if (params->hw_funcs->emul_get_inbox1_rptr) 330 dmub->hw_funcs.emul_get_inbox1_rptr = 331 params->hw_funcs->emul_get_inbox1_rptr; 332 333 if (params->hw_funcs->emul_set_inbox1_wptr) 334 dmub->hw_funcs.emul_set_inbox1_wptr = 335 params->hw_funcs->emul_set_inbox1_wptr; 336 337 if (params->hw_funcs->is_supported) 338 dmub->hw_funcs.is_supported = 339 params->hw_funcs->is_supported; 340 } 341 342 /* Sanity checks for required hw func pointers. */ 343 if (!dmub->hw_funcs.get_inbox1_rptr || 344 !dmub->hw_funcs.set_inbox1_wptr) { 345 status = DMUB_STATUS_INVALID; 346 goto cleanup; 347 } 348 349 cleanup: 350 if (status == DMUB_STATUS_OK) 351 dmub->sw_init = true; 352 else 353 dmub_srv_destroy(dmub); 354 355 return status; 356 } 357 358 void dmub_srv_destroy(struct dmub_srv *dmub) 359 { 360 dmub_memset(dmub, 0, sizeof(*dmub)); 361 } 362 363 enum dmub_status 364 dmub_srv_calc_region_info(struct dmub_srv *dmub, 365 const struct dmub_srv_region_params *params, 366 struct dmub_srv_region_info *out) 367 { 368 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 369 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 370 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 371 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 372 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 373 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 374 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 375 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 376 const struct dmub_fw_meta_info *fw_info; 377 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 378 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 379 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 380 381 if (!dmub->sw_init) 382 return DMUB_STATUS_INVALID; 383 384 memset(out, 0, sizeof(*out)); 385 386 out->num_regions = DMUB_NUM_WINDOWS; 387 388 inst->base = 0x0; 389 inst->top = inst->base + params->inst_const_size; 390 391 data->base = dmub_align(inst->top, 256); 392 data->top = data->base + params->bss_data_size; 393 394 /* 395 * All cache windows below should be aligned to the size 396 * of the DMCUB cache line, 64 bytes. 397 */ 398 399 stack->base = dmub_align(data->top, 256); 400 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 401 402 bios->base = dmub_align(stack->top, 256); 403 bios->top = bios->base + params->vbios_size; 404 405 mail->base = dmub_align(bios->top, 256); 406 mail->top = mail->base + DMUB_MAILBOX_SIZE; 407 408 fw_info = dmub_get_fw_meta_info(params); 409 410 if (fw_info) { 411 fw_state_size = fw_info->fw_region_size; 412 trace_buffer_size = fw_info->trace_buffer_size; 413 414 /** 415 * If DM didn't fill in a version, then fill it in based on 416 * the firmware meta now that we have it. 417 * 418 * TODO: Make it easier for driver to extract this out to 419 * pass during creation. 420 */ 421 if (dmub->fw_version == 0) 422 dmub->fw_version = fw_info->fw_version; 423 } 424 425 trace_buff->base = dmub_align(mail->top, 256); 426 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 427 428 fw_state->base = dmub_align(trace_buff->top, 256); 429 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 430 431 scratch_mem->base = dmub_align(fw_state->top, 256); 432 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 433 434 out->fb_size = dmub_align(scratch_mem->top, 4096); 435 436 return DMUB_STATUS_OK; 437 } 438 439 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 440 const struct dmub_srv_fb_params *params, 441 struct dmub_srv_fb_info *out) 442 { 443 uint8_t *cpu_base; 444 uint64_t gpu_base; 445 uint32_t i; 446 447 if (!dmub->sw_init) 448 return DMUB_STATUS_INVALID; 449 450 memset(out, 0, sizeof(*out)); 451 452 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 453 return DMUB_STATUS_INVALID; 454 455 cpu_base = (uint8_t *)params->cpu_addr; 456 gpu_base = params->gpu_addr; 457 458 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 459 const struct dmub_region *reg = 460 ¶ms->region_info->regions[i]; 461 462 out->fb[i].cpu_addr = cpu_base + reg->base; 463 out->fb[i].gpu_addr = gpu_base + reg->base; 464 out->fb[i].size = reg->top - reg->base; 465 } 466 467 out->num_fb = DMUB_NUM_WINDOWS; 468 469 return DMUB_STATUS_OK; 470 } 471 472 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 473 bool *is_supported) 474 { 475 *is_supported = false; 476 477 if (!dmub->sw_init) 478 return DMUB_STATUS_INVALID; 479 480 if (dmub->hw_funcs.is_supported) 481 *is_supported = dmub->hw_funcs.is_supported(dmub); 482 483 return DMUB_STATUS_OK; 484 } 485 486 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 487 { 488 *is_hw_init = false; 489 490 if (!dmub->sw_init) 491 return DMUB_STATUS_INVALID; 492 493 if (!dmub->hw_init) 494 return DMUB_STATUS_OK; 495 496 if (dmub->hw_funcs.is_hw_init) 497 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 498 499 return DMUB_STATUS_OK; 500 } 501 502 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 503 const struct dmub_srv_hw_params *params) 504 { 505 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 506 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 507 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 508 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 509 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 510 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 511 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 512 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 513 514 struct dmub_rb_init_params rb_params, outbox0_rb_params; 515 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 516 struct dmub_region inbox1, outbox1, outbox0; 517 518 if (!dmub->sw_init) 519 return DMUB_STATUS_INVALID; 520 521 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 522 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 523 ASSERT(0); 524 return DMUB_STATUS_INVALID; 525 } 526 527 dmub->fb_base = params->fb_base; 528 dmub->fb_offset = params->fb_offset; 529 dmub->psp_version = params->psp_version; 530 531 if (dmub->hw_funcs.reset) 532 dmub->hw_funcs.reset(dmub); 533 534 cw0.offset.quad_part = inst_fb->gpu_addr; 535 cw0.region.base = DMUB_CW0_BASE; 536 cw0.region.top = cw0.region.base + inst_fb->size - 1; 537 538 cw1.offset.quad_part = stack_fb->gpu_addr; 539 cw1.region.base = DMUB_CW1_BASE; 540 cw1.region.top = cw1.region.base + stack_fb->size - 1; 541 542 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 543 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 544 545 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 546 /** 547 * Read back all the instruction memory so we don't hang the 548 * DMCUB when backdoor loading if the write from x86 hasn't been 549 * flushed yet. This only occurs in backdoor loading. 550 */ 551 dmub_flush_buffer_mem(inst_fb); 552 553 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 554 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 555 else 556 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 557 } 558 559 cw2.offset.quad_part = data_fb->gpu_addr; 560 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 561 cw2.region.top = cw2.region.base + data_fb->size; 562 563 cw3.offset.quad_part = bios_fb->gpu_addr; 564 cw3.region.base = DMUB_CW3_BASE; 565 cw3.region.top = cw3.region.base + bios_fb->size; 566 567 cw4.offset.quad_part = mail_fb->gpu_addr; 568 cw4.region.base = DMUB_CW4_BASE; 569 cw4.region.top = cw4.region.base + mail_fb->size; 570 571 /** 572 * Doubled the mailbox region to accomodate inbox and outbox. 573 * Note: Currently, currently total mailbox size is 16KB. It is split 574 * equally into 8KB between inbox and outbox. If this config is 575 * changed, then uncached base address configuration of outbox1 576 * has to be updated in funcs->setup_out_mailbox. 577 */ 578 inbox1.base = cw4.region.base; 579 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 580 outbox1.base = inbox1.top; 581 outbox1.top = cw4.region.top; 582 583 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 584 cw5.region.base = DMUB_CW5_BASE; 585 cw5.region.top = cw5.region.base + tracebuff_fb->size; 586 587 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 588 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 589 590 cw6.offset.quad_part = fw_state_fb->gpu_addr; 591 cw6.region.base = DMUB_CW6_BASE; 592 cw6.region.top = cw6.region.base + fw_state_fb->size; 593 594 dmub->fw_state = fw_state_fb->cpu_addr; 595 596 dmub->scratch_mem_fb = *scratch_mem_fb; 597 598 if (dmub->hw_funcs.setup_windows) 599 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 600 601 if (dmub->hw_funcs.setup_outbox0) 602 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 603 604 if (dmub->hw_funcs.setup_mailbox) 605 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 606 if (dmub->hw_funcs.setup_out_mailbox) 607 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 608 609 dmub_memset(&rb_params, 0, sizeof(rb_params)); 610 rb_params.ctx = dmub; 611 rb_params.base_address = mail_fb->cpu_addr; 612 rb_params.capacity = DMUB_RB_SIZE; 613 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 614 615 // Initialize outbox1 ring buffer 616 rb_params.ctx = dmub; 617 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 618 rb_params.capacity = DMUB_RB_SIZE; 619 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 620 621 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 622 outbox0_rb_params.ctx = dmub; 623 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 624 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 625 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 626 627 /* Report to DMUB what features are supported by current driver */ 628 if (dmub->hw_funcs.enable_dmub_boot_options) 629 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 630 631 if (dmub->hw_funcs.skip_dmub_panel_power_sequence) 632 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 633 params->skip_panel_power_sequence); 634 635 if (dmub->hw_funcs.reset_release) 636 dmub->hw_funcs.reset_release(dmub); 637 638 dmub->hw_init = true; 639 640 return DMUB_STATUS_OK; 641 } 642 643 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 644 { 645 if (!dmub->sw_init) 646 return DMUB_STATUS_INVALID; 647 648 if (dmub->hw_funcs.reset) 649 dmub->hw_funcs.reset(dmub); 650 651 dmub->hw_init = false; 652 653 return DMUB_STATUS_OK; 654 } 655 656 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 657 const union dmub_rb_cmd *cmd) 658 { 659 if (!dmub->hw_init) 660 return DMUB_STATUS_INVALID; 661 662 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 663 return DMUB_STATUS_OK; 664 665 return DMUB_STATUS_QUEUE_FULL; 666 } 667 668 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 669 { 670 struct dmub_rb flush_rb; 671 672 if (!dmub->hw_init) 673 return DMUB_STATUS_INVALID; 674 675 /** 676 * Read back all the queued commands to ensure that they've 677 * been flushed to framebuffer memory. Otherwise DMCUB might 678 * read back stale, fully invalid or partially invalid data. 679 */ 680 flush_rb = dmub->inbox1_rb; 681 flush_rb.rptr = dmub->inbox1_last_wptr; 682 dmub_rb_flush_pending(&flush_rb); 683 684 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 685 686 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 687 688 return DMUB_STATUS_OK; 689 } 690 691 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 692 uint32_t timeout_us) 693 { 694 uint32_t i; 695 696 if (!dmub->hw_init) 697 return DMUB_STATUS_INVALID; 698 699 for (i = 0; i <= timeout_us; i += 100) { 700 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 701 702 if (status.bits.dal_fw && status.bits.mailbox_rdy) 703 return DMUB_STATUS_OK; 704 705 udelay(100); 706 } 707 708 return DMUB_STATUS_TIMEOUT; 709 } 710 711 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 712 uint32_t timeout_us) 713 { 714 uint32_t i = 0; 715 716 if (!dmub->hw_init) 717 return DMUB_STATUS_INVALID; 718 719 if (!dmub->hw_funcs.is_phy_init) 720 return DMUB_STATUS_OK; 721 722 for (i = 0; i <= timeout_us; i += 10) { 723 if (dmub->hw_funcs.is_phy_init(dmub)) 724 return DMUB_STATUS_OK; 725 726 udelay(10); 727 } 728 729 return DMUB_STATUS_TIMEOUT; 730 } 731 732 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 733 uint32_t timeout_us) 734 { 735 uint32_t i, rptr; 736 737 if (!dmub->hw_init) 738 return DMUB_STATUS_INVALID; 739 740 for (i = 0; i <= timeout_us; ++i) { 741 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 742 743 if (rptr > dmub->inbox1_rb.capacity) 744 return DMUB_STATUS_HW_FAILURE; 745 746 dmub->inbox1_rb.rptr = rptr; 747 748 if (dmub_rb_empty(&dmub->inbox1_rb)) 749 return DMUB_STATUS_OK; 750 751 udelay(1); 752 } 753 754 return DMUB_STATUS_TIMEOUT; 755 } 756 757 enum dmub_status 758 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 759 enum dmub_gpint_command command_code, 760 uint16_t param, uint32_t timeout_us) 761 { 762 union dmub_gpint_data_register reg; 763 uint32_t i; 764 765 if (!dmub->sw_init) 766 return DMUB_STATUS_INVALID; 767 768 if (!dmub->hw_funcs.set_gpint) 769 return DMUB_STATUS_INVALID; 770 771 if (!dmub->hw_funcs.is_gpint_acked) 772 return DMUB_STATUS_INVALID; 773 774 reg.bits.status = 1; 775 reg.bits.command_code = command_code; 776 reg.bits.param = param; 777 778 dmub->hw_funcs.set_gpint(dmub, reg); 779 780 for (i = 0; i < timeout_us; ++i) { 781 udelay(1); 782 783 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 784 return DMUB_STATUS_OK; 785 } 786 787 return DMUB_STATUS_TIMEOUT; 788 } 789 790 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 791 uint32_t *response) 792 { 793 *response = 0; 794 795 if (!dmub->sw_init) 796 return DMUB_STATUS_INVALID; 797 798 if (!dmub->hw_funcs.get_gpint_response) 799 return DMUB_STATUS_INVALID; 800 801 *response = dmub->hw_funcs.get_gpint_response(dmub); 802 803 return DMUB_STATUS_OK; 804 } 805 806 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 807 uint32_t *dataout) 808 { 809 *dataout = 0; 810 811 if (!dmub->sw_init) 812 return DMUB_STATUS_INVALID; 813 814 if (!dmub->hw_funcs.get_gpint_dataout) 815 return DMUB_STATUS_INVALID; 816 817 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 818 819 return DMUB_STATUS_OK; 820 } 821 822 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 823 union dmub_fw_boot_status *status) 824 { 825 status->all = 0; 826 827 if (!dmub->sw_init) 828 return DMUB_STATUS_INVALID; 829 830 if (dmub->hw_funcs.get_fw_status) 831 *status = dmub->hw_funcs.get_fw_status(dmub); 832 833 return DMUB_STATUS_OK; 834 } 835 836 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 837 union dmub_rb_cmd *cmd) 838 { 839 enum dmub_status status = DMUB_STATUS_OK; 840 841 // Queue command 842 status = dmub_srv_cmd_queue(dmub, cmd); 843 844 if (status != DMUB_STATUS_OK) 845 return status; 846 847 // Execute command 848 status = dmub_srv_cmd_execute(dmub); 849 850 if (status != DMUB_STATUS_OK) 851 return status; 852 853 // Wait for DMUB to process command 854 status = dmub_srv_wait_for_idle(dmub, 100000); 855 856 if (status != DMUB_STATUS_OK) 857 return status; 858 859 // Copy data back from ring buffer into command 860 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 861 862 return status; 863 } 864 865 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 866 void *entry) 867 { 868 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 869 uint64_t *dst = (uint64_t *)entry; 870 uint8_t i; 871 uint8_t loop_count; 872 873 if (rb->rptr == rb->wrpt) 874 return false; 875 876 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 877 // copying data 878 for (i = 0; i < loop_count; i++) 879 *dst++ = *src++; 880 881 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 882 883 rb->rptr %= rb->capacity; 884 885 return true; 886 } 887 888 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 889 { 890 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 891 892 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 893 } 894 895 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 896 { 897 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 898 return false; 899 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 900 return true; 901 } 902 903 bool dmub_srv_should_detect(struct dmub_srv *dmub) 904 { 905 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 906 return false; 907 908 return dmub->hw_funcs.should_detect(dmub); 909 } 910 911 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 912 { 913 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 914 return DMUB_STATUS_INVALID; 915 916 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 917 return DMUB_STATUS_OK; 918 } 919 920 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 921 { 922 uint32_t i = 0; 923 uint32_t ack = 0; 924 925 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 926 return DMUB_STATUS_INVALID; 927 928 for (i = 0; i <= timeout_us; i++) { 929 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 930 if (ack) 931 return DMUB_STATUS_OK; 932 } 933 return DMUB_STATUS_TIMEOUT; 934 } 935 936 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 937 union dmub_inbox0_data_register data) 938 { 939 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 940 return DMUB_STATUS_INVALID; 941 942 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 943 return DMUB_STATUS_OK; 944 } 945