1*5559c7baSQingqing Zhuo /* 2*5559c7baSQingqing Zhuo * Copyright 2021 Advanced Micro Devices, Inc. 3*5559c7baSQingqing Zhuo * 4*5559c7baSQingqing Zhuo * Permission is hereby granted, free of charge, to any person obtaining a 5*5559c7baSQingqing Zhuo * copy of this software and associated documentation files (the "Software"), 6*5559c7baSQingqing Zhuo * to deal in the Software without restriction, including without limitation 7*5559c7baSQingqing Zhuo * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*5559c7baSQingqing Zhuo * and/or sell copies of the Software, and to permit persons to whom the 9*5559c7baSQingqing Zhuo * Software is furnished to do so, subject to the following conditions: 10*5559c7baSQingqing Zhuo * 11*5559c7baSQingqing Zhuo * The above copyright notice and this permission notice shall be included in 12*5559c7baSQingqing Zhuo * all copies or substantial portions of the Software. 13*5559c7baSQingqing Zhuo * 14*5559c7baSQingqing Zhuo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*5559c7baSQingqing Zhuo * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*5559c7baSQingqing Zhuo * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*5559c7baSQingqing Zhuo * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*5559c7baSQingqing Zhuo * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*5559c7baSQingqing Zhuo * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*5559c7baSQingqing Zhuo * OTHER DEALINGS IN THE SOFTWARE. 21*5559c7baSQingqing Zhuo * 22*5559c7baSQingqing Zhuo * Authors: AMD 23*5559c7baSQingqing Zhuo * 24*5559c7baSQingqing Zhuo */ 25*5559c7baSQingqing Zhuo 26*5559c7baSQingqing Zhuo #ifndef _DMUB_DCN315_H_ 27*5559c7baSQingqing Zhuo #define _DMUB_DCN315_H_ 28*5559c7baSQingqing Zhuo 29*5559c7baSQingqing Zhuo #include "dmub_dcn31.h" 30*5559c7baSQingqing Zhuo 31*5559c7baSQingqing Zhuo #define DMUB_DCN315_FIELDS() \ 32*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ 33*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \ 34*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \ 35*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \ 36*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \ 37*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \ 38*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \ 39*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \ 40*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \ 41*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \ 42*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \ 43*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \ 44*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \ 45*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \ 46*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \ 47*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \ 48*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \ 49*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \ 50*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \ 51*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \ 52*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \ 53*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \ 54*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \ 55*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \ 56*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \ 57*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \ 58*5559c7baSQingqing Zhuo DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \ 59*5559c7baSQingqing Zhuo DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ 60*5559c7baSQingqing Zhuo DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ 61*5559c7baSQingqing Zhuo DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \ 62*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \ 63*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT2_INT_EN) \ 64*5559c7baSQingqing Zhuo DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT2_INT_ACK) 65*5559c7baSQingqing Zhuo 66*5559c7baSQingqing Zhuo extern const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs; 67*5559c7baSQingqing Zhuo 68*5559c7baSQingqing Zhuo #endif /* _DMUB_DCN315_H_ */ 69