1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "../dmub_srv.h"
27 #include "dmub_reg.h"
28 #include "dmub_dcn315.h"
29 
30 #include "dcn/dcn_3_1_5_offset.h"
31 #include "dcn/dcn_3_1_5_sh_mask.h"
32 
33 #define DCN_BASE__INST0_SEG0                       0x00000012
34 #define DCN_BASE__INST0_SEG1                       0x000000C0
35 #define DCN_BASE__INST0_SEG2                       0x000034C0
36 #define DCN_BASE__INST0_SEG3                       0x00009000
37 #define DCN_BASE__INST0_SEG4                       0x02403C00
38 #define DCN_BASE__INST0_SEG5                       0
39 
40 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
41 #define CTX dmub
42 #define REGS dmub->regs_dcn31
43 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
44 
45 /* Registers. */
46 
47 const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs = {
48 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
49 	{
50 		DMUB_DCN31_REGS()
51 		DMCUB_INTERNAL_REGS()
52 	},
53 #undef DMUB_SR
54 
55 #define DMUB_SF(reg, field) FD_MASK(reg, field),
56 	{ DMUB_DCN315_FIELDS() },
57 #undef DMUB_SF
58 
59 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
60 	{ DMUB_DCN315_FIELDS() },
61 #undef DMUB_SF
62 };
63