1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef _DMUB_DCN31_H_
27 #define _DMUB_DCN31_H_
28 
29 #include "dmub_dcn20.h"
30 
31 struct dmub_srv;
32 
33 /* DCN31 register definitions. */
34 
35 #define DMUB_DCN31_REGS() \
36 	DMUB_SR(DMCUB_CNTL) \
37 	DMUB_SR(DMCUB_CNTL2) \
38 	DMUB_SR(DMCUB_SEC_CNTL) \
39 	DMUB_SR(DMCUB_INBOX0_SIZE) \
40 	DMUB_SR(DMCUB_INBOX0_RPTR) \
41 	DMUB_SR(DMCUB_INBOX0_WPTR) \
42 	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
43 	DMUB_SR(DMCUB_INBOX1_SIZE) \
44 	DMUB_SR(DMCUB_INBOX1_RPTR) \
45 	DMUB_SR(DMCUB_INBOX1_WPTR) \
46 	DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
47 	DMUB_SR(DMCUB_OUTBOX0_SIZE) \
48 	DMUB_SR(DMCUB_OUTBOX0_RPTR) \
49 	DMUB_SR(DMCUB_OUTBOX0_WPTR) \
50 	DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
51 	DMUB_SR(DMCUB_OUTBOX1_SIZE) \
52 	DMUB_SR(DMCUB_OUTBOX1_RPTR) \
53 	DMUB_SR(DMCUB_OUTBOX1_WPTR) \
54 	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
55 	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
56 	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
57 	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
58 	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
59 	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
60 	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
61 	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
62 	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
63 	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
64 	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
65 	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
66 	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
67 	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
68 	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
69 	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
70 	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
71 	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
72 	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
73 	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
74 	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
75 	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
76 	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
77 	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
78 	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
79 	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
80 	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
81 	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
82 	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
83 	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
84 	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
85 	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
86 	DMUB_SR(DMCUB_REGION4_OFFSET) \
87 	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
88 	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
89 	DMUB_SR(DMCUB_REGION5_OFFSET) \
90 	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
91 	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
92 	DMUB_SR(DMCUB_SCRATCH0) \
93 	DMUB_SR(DMCUB_SCRATCH1) \
94 	DMUB_SR(DMCUB_SCRATCH2) \
95 	DMUB_SR(DMCUB_SCRATCH3) \
96 	DMUB_SR(DMCUB_SCRATCH4) \
97 	DMUB_SR(DMCUB_SCRATCH5) \
98 	DMUB_SR(DMCUB_SCRATCH6) \
99 	DMUB_SR(DMCUB_SCRATCH7) \
100 	DMUB_SR(DMCUB_SCRATCH8) \
101 	DMUB_SR(DMCUB_SCRATCH9) \
102 	DMUB_SR(DMCUB_SCRATCH10) \
103 	DMUB_SR(DMCUB_SCRATCH11) \
104 	DMUB_SR(DMCUB_SCRATCH12) \
105 	DMUB_SR(DMCUB_SCRATCH13) \
106 	DMUB_SR(DMCUB_SCRATCH14) \
107 	DMUB_SR(DMCUB_SCRATCH15) \
108 	DMUB_SR(DMCUB_GPINT_DATAIN1) \
109 	DMUB_SR(DMCUB_GPINT_DATAOUT) \
110 	DMUB_SR(CC_DC_PIPE_DIS) \
111 	DMUB_SR(MMHUBBUB_SOFT_RESET) \
112 	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
113 	DMUB_SR(DCN_VM_FB_OFFSET) \
114 	DMUB_SR(DMCUB_TIMER_CURRENT) \
115 	DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
116 	DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
117 	DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
118 	DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
119 	DMUB_SR(DMCUB_INTERRUPT_ACK)
120 
121 #define DMUB_DCN31_FIELDS() \
122 	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
123 	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
124 	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
125 	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
126 	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
127 	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
128 	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
129 	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
130 	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
131 	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
132 	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
133 	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
134 	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
135 	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
136 	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
137 	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
138 	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
139 	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
140 	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
141 	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
142 	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
143 	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
144 	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
145 	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
146 	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
147 	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
148 	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
149 	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
150 	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
151 	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
152 	DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
153 	DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
154 	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \
155 	DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS)
156 
157 struct dmub_srv_dcn31_reg_offset {
158 #define DMUB_SR(reg) uint32_t reg;
159 	DMUB_DCN31_REGS()
160 	DMCUB_INTERNAL_REGS()
161 #undef DMUB_SR
162 };
163 
164 struct dmub_srv_dcn31_reg_shift {
165 #define DMUB_SF(reg, field) uint8_t reg##__##field;
166 	DMUB_DCN31_FIELDS()
167 #undef DMUB_SF
168 };
169 
170 struct dmub_srv_dcn31_reg_mask {
171 #define DMUB_SF(reg, field) uint32_t reg##__##field;
172 	DMUB_DCN31_FIELDS()
173 #undef DMUB_SF
174 };
175 
176 struct dmub_srv_dcn31_regs {
177 	const struct dmub_srv_dcn31_reg_offset offset;
178 	const struct dmub_srv_dcn31_reg_mask mask;
179 	const struct dmub_srv_dcn31_reg_shift shift;
180 };
181 
182 extern const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs;
183 
184 /* Hardware functions. */
185 
186 
187 void dmub_dcn31_init(struct dmub_srv *dmub);
188 
189 void dmub_dcn31_reset(struct dmub_srv *dmub);
190 
191 void dmub_dcn31_reset_release(struct dmub_srv *dmub);
192 
193 void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
194 			      const struct dmub_window *cw0,
195 			      const struct dmub_window *cw1);
196 
197 void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
198 			      const struct dmub_window *cw2,
199 			      const struct dmub_window *cw3,
200 			      const struct dmub_window *cw4,
201 			      const struct dmub_window *cw5,
202 			      const struct dmub_window *cw6);
203 
204 void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
205 			      const struct dmub_region *inbox1);
206 
207 uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub);
208 
209 uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);
210 
211 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
212 
213 void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
214 			      const struct dmub_region *outbox1);
215 
216 uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);
217 
218 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
219 
220 bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);
221 
222 bool dmub_dcn31_is_supported(struct dmub_srv *dmub);
223 
224 bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub);
225 
226 void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
227 			  union dmub_gpint_data_register reg);
228 
229 bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
230 			       union dmub_gpint_data_register reg);
231 
232 uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);
233 
234 uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);
235 
236 void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
237 
238 void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
239 
240 union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);
241 
242 void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
243 			      const struct dmub_region *outbox0);
244 
245 uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);
246 
247 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
248 
249 uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);
250 
251 void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);
252 
253 bool dmub_dcn31_should_detect(struct dmub_srv *dmub);
254 
255 #endif /* _DMUB_DCN31_H_ */
256