1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "../dmub_srv.h"
27 #include "dmub_reg.h"
28 #include "dmub_dcn31.h"
29 
30 #include "yellow_carp_offset.h"
31 #include "dcn/dcn_3_1_2_offset.h"
32 #include "dcn/dcn_3_1_2_sh_mask.h"
33 
34 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
35 #define CTX dmub
36 #define REGS dmub->regs_dcn31
37 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
38 
39 const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = {
40 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
41 	{
42 		DMUB_DCN31_REGS()
43 		DMCUB_INTERNAL_REGS()
44 	},
45 #undef DMUB_SR
46 
47 #define DMUB_SF(reg, field) FD_MASK(reg, field),
48 	{ DMUB_DCN31_FIELDS() },
49 #undef DMUB_SF
50 
51 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
52 	{ DMUB_DCN31_FIELDS() },
53 #undef DMUB_SF
54 };
55 
56 static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,
57 					  uint64_t *fb_base,
58 					  uint64_t *fb_offset)
59 {
60 	uint32_t tmp;
61 
62 	if (dmub->fb_base || dmub->fb_offset) {
63 		*fb_base = dmub->fb_base;
64 		*fb_offset = dmub->fb_offset;
65 		return;
66 	}
67 
68 	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
69 	*fb_base = (uint64_t)tmp << 24;
70 
71 	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
72 	*fb_offset = (uint64_t)tmp << 24;
73 }
74 
75 static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,
76 					     uint64_t fb_base,
77 					     uint64_t fb_offset,
78 					     union dmub_addr *addr_out)
79 {
80 	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
81 }
82 
83 void dmub_dcn31_reset(struct dmub_srv *dmub)
84 {
85 	union dmub_gpint_data_register cmd;
86 	const uint32_t timeout = 100;
87 	uint32_t in_reset, scratch, i, pwait_mode;
88 
89 	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
90 
91 	if (in_reset == 0) {
92 		cmd.bits.status = 1;
93 		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
94 		cmd.bits.param = 0;
95 
96 		dmub->hw_funcs.set_gpint(dmub, cmd);
97 
98 		/**
99 		 * Timeout covers both the ACK and the wait
100 		 * for remaining work to finish.
101 		 */
102 
103 		for (i = 0; i < timeout; ++i) {
104 			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
105 				break;
106 
107 			udelay(1);
108 		}
109 
110 		for (i = 0; i < timeout; ++i) {
111 			scratch = dmub->hw_funcs.get_gpint_response(dmub);
112 			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
113 				break;
114 
115 			udelay(1);
116 		}
117 
118 		for (i = 0; i < timeout; ++i) {
119 			REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
120 			if (pwait_mode & (1 << 0))
121 				break;
122 
123 			udelay(1);
124 		}
125 		/* Force reset in case we timed out, DMCUB is likely hung. */
126 	}
127 
128 	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
129 	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
130 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
131 	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
132 	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
133 	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
134 	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
135 	REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
136 	REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
137 	REG_WRITE(DMCUB_SCRATCH0, 0);
138 
139 	/* Clear the GPINT command manually so we don't send anything during boot. */
140 	cmd.all = 0;
141 	dmub->hw_funcs.set_gpint(dmub, cmd);
142 }
143 
144 void dmub_dcn31_reset_release(struct dmub_srv *dmub)
145 {
146 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
147 	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
148 	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
149 	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
150 }
151 
152 void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
153 			      const struct dmub_window *cw0,
154 			      const struct dmub_window *cw1)
155 {
156 	union dmub_addr offset;
157 	uint64_t fb_base, fb_offset;
158 
159 	dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset);
160 
161 	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
162 
163 	dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
164 
165 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
166 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
167 	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
168 	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
169 		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
170 		  DMCUB_REGION3_CW0_ENABLE, 1);
171 
172 	dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
173 
174 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
175 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
176 	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
177 	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
178 		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
179 		  DMCUB_REGION3_CW1_ENABLE, 1);
180 
181 	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
182 		     0x20);
183 }
184 
185 void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
186 			      const struct dmub_window *cw2,
187 			      const struct dmub_window *cw3,
188 			      const struct dmub_window *cw4,
189 			      const struct dmub_window *cw5,
190 			      const struct dmub_window *cw6)
191 {
192 	union dmub_addr offset;
193 
194 	offset = cw3->offset;
195 
196 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
197 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
198 	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
199 	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
200 		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
201 		  DMCUB_REGION3_CW3_ENABLE, 1);
202 
203 	offset = cw4->offset;
204 
205 	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
206 	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
207 	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
208 	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
209 		  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
210 		  DMCUB_REGION3_CW4_ENABLE, 1);
211 
212 	offset = cw5->offset;
213 
214 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
215 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
216 	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
217 	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
218 		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
219 		  DMCUB_REGION3_CW5_ENABLE, 1);
220 
221 	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
222 	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
223 	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
224 		  DMCUB_REGION5_TOP_ADDRESS,
225 		  cw5->region.top - cw5->region.base - 1,
226 		  DMCUB_REGION5_ENABLE, 1);
227 
228 	offset = cw6->offset;
229 
230 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
231 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
232 	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
233 	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
234 		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
235 		  DMCUB_REGION3_CW6_ENABLE, 1);
236 }
237 
238 void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
239 			      const struct dmub_region *inbox1)
240 {
241 	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
242 	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
243 }
244 
245 uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)
246 {
247 	return REG_READ(DMCUB_INBOX1_RPTR);
248 }
249 
250 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
251 {
252 	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
253 }
254 
255 void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
256 			      const struct dmub_region *outbox1)
257 {
258 	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
259 	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
260 }
261 
262 uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)
263 {
264 	/**
265 	 * outbox1 wptr register is accessed without locks (dal & dc)
266 	 * and to be called only by dmub_srv_stat_get_notification()
267 	 */
268 	return REG_READ(DMCUB_OUTBOX1_WPTR);
269 }
270 
271 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
272 {
273 	/**
274 	 * outbox1 rptr register is accessed without locks (dal & dc)
275 	 * and to be called only by dmub_srv_stat_get_notification()
276 	 */
277 	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
278 }
279 
280 bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)
281 {
282 	union dmub_fw_boot_status status;
283 	uint32_t is_enable;
284 
285 	status.all = REG_READ(DMCUB_SCRATCH0);
286 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
287 
288 	return is_enable != 0 && status.bits.dal_fw;
289 }
290 
291 bool dmub_dcn31_is_supported(struct dmub_srv *dmub)
292 {
293 	uint32_t supported = 0;
294 
295 	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
296 
297 	return supported;
298 }
299 
300 void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
301 			  union dmub_gpint_data_register reg)
302 {
303 	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
304 }
305 
306 bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
307 			       union dmub_gpint_data_register reg)
308 {
309 	union dmub_gpint_data_register test;
310 
311 	reg.bits.status = 0;
312 	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
313 
314 	return test.all == reg.all;
315 }
316 
317 uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)
318 {
319 	return REG_READ(DMCUB_SCRATCH7);
320 }
321 
322 uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)
323 {
324 	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
325 
326 	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
327 
328 	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
329 	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
330 	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
331 
332 	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
333 
334 	return dataout;
335 }
336 
337 union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)
338 {
339 	union dmub_fw_boot_status status;
340 
341 	status.all = REG_READ(DMCUB_SCRATCH0);
342 	return status;
343 }
344 
345 void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
346 {
347 	union dmub_fw_boot_options boot_options = {0};
348 
349 	boot_options.bits.z10_disable = params->disable_z10;
350 	boot_options.bits.dpia_supported = params->dpia_supported;
351 	boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;
352 	boot_options.bits.usb4_cm_version = params->usb4_cm_version;
353 	boot_options.bits.power_optimization = params->power_optimization;
354 
355 	boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;
356 
357 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
358 }
359 
360 void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
361 {
362 	union dmub_fw_boot_options boot_options;
363 	boot_options.all = REG_READ(DMCUB_SCRATCH14);
364 	boot_options.bits.skip_phy_init_panel_sequence = skip;
365 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
366 }
367 
368 void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
369 			      const struct dmub_region *outbox0)
370 {
371 	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
372 
373 	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
374 }
375 
376 uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)
377 {
378 	return REG_READ(DMCUB_OUTBOX0_WPTR);
379 }
380 
381 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
382 {
383 	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
384 }
385 
386 uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)
387 {
388 	return REG_READ(DMCUB_TIMER_CURRENT);
389 }
390 
391 void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
392 {
393 	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
394 	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
395 
396 	if (!dmub || !diag_data)
397 		return;
398 
399 	memset(diag_data, 0, sizeof(*diag_data));
400 
401 	diag_data->dmcub_version = dmub->fw_version;
402 
403 	diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
404 	diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
405 	diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
406 	diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
407 	diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
408 	diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
409 	diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
410 	diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
411 	diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
412 	diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
413 	diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
414 	diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
415 	diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
416 	diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
417 	diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
418 	diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
419 
420 	diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
421 	diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
422 	diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
423 
424 	diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
425 	diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
426 	diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
427 
428 	diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
429 	diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
430 	diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
431 
432 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
433 	diag_data->is_dmcub_enabled = is_dmub_enabled;
434 
435 	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
436 	diag_data->is_dmcub_soft_reset = is_soft_reset;
437 
438 	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
439 	diag_data->is_dmcub_secure_reset = is_sec_reset;
440 
441 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
442 	diag_data->is_traceport_en  = is_traceport_enabled;
443 
444 	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
445 	diag_data->is_cw0_enabled = is_cw0_enabled;
446 
447 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
448 	diag_data->is_cw6_enabled = is_cw6_enabled;
449 }
450 
451 bool dmub_dcn31_should_detect(struct dmub_srv *dmub)
452 {
453 	uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
454 	bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
455 	return should_detect;
456 }
457 
458