1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_reg.h" 28 #include "dmub_dcn20.h" 29 #include "dmub_dcn30.h" 30 31 #include "sienna_cichlid_ip_offset.h" 32 #include "dcn/dcn_3_0_0_offset.h" 33 #include "dcn/dcn_3_0_0_sh_mask.h" 34 35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg 36 #define CTX dmub 37 #define REGS dmub->regs 38 39 /* Registers. */ 40 41 const struct dmub_srv_common_regs dmub_srv_dcn30_regs = { 42 #define DMUB_SR(reg) REG_OFFSET(reg), 43 { DMUB_COMMON_REGS() }, 44 #undef DMUB_SR 45 46 #define DMUB_SF(reg, field) FD_MASK(reg, field), 47 { DMUB_COMMON_FIELDS() }, 48 #undef DMUB_SF 49 50 #define DMUB_SF(reg, field) FD_SHIFT(reg, field), 51 { DMUB_COMMON_FIELDS() }, 52 #undef DMUB_SF 53 }; 54 55 /* Shared functions. */ 56 57 static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub, 58 uint64_t *fb_base, 59 uint64_t *fb_offset) 60 { 61 uint32_t tmp; 62 63 if (dmub->fb_base || dmub->fb_offset) { 64 *fb_base = dmub->fb_base; 65 *fb_offset = dmub->fb_offset; 66 return; 67 } 68 69 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 70 *fb_base = (uint64_t)tmp << 24; 71 72 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 73 *fb_offset = (uint64_t)tmp << 24; 74 } 75 76 static inline void dmub_dcn30_translate_addr(const union dmub_addr *addr_in, 77 uint64_t fb_base, 78 uint64_t fb_offset, 79 union dmub_addr *addr_out) 80 { 81 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 82 } 83 84 void dmub_dcn30_backdoor_load(struct dmub_srv *dmub, 85 const struct dmub_window *cw0, 86 const struct dmub_window *cw1) 87 { 88 union dmub_addr offset; 89 uint64_t fb_base, fb_offset; 90 91 dmub_dcn30_get_fb_base_offset(dmub, &fb_base, &fb_offset); 92 93 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 94 95 /* MEM_CTNL read/write space doesn't exist. */ 96 97 dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 98 99 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 100 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 101 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 102 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 103 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 104 DMCUB_REGION3_CW0_ENABLE, 1); 105 106 dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 107 108 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 109 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 110 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 111 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 112 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 113 DMCUB_REGION3_CW1_ENABLE, 1); 114 115 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 116 0x20); 117 } 118 119 void dmub_dcn30_setup_windows(struct dmub_srv *dmub, 120 const struct dmub_window *cw2, 121 const struct dmub_window *cw3, 122 const struct dmub_window *cw4, 123 const struct dmub_window *cw5, 124 const struct dmub_window *cw6) 125 { 126 union dmub_addr offset; 127 128 /* sienna_cichlid has hardwired virtual addressing for CW2-CW7 */ 129 130 offset = cw2->offset; 131 132 if (cw2->region.base != cw2->region.top) { 133 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); 134 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); 135 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); 136 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, 137 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, 138 DMCUB_REGION3_CW2_ENABLE, 1); 139 } else { 140 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0); 141 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0); 142 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0); 143 REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0); 144 } 145 146 offset = cw3->offset; 147 148 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 149 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 150 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 151 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 152 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 153 DMCUB_REGION3_CW3_ENABLE, 1); 154 155 offset = cw4->offset; 156 157 /* New firmware can support CW4. */ 158 if (dmub_dcn20_use_cached_inbox(dmub)) { 159 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 160 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 161 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 162 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 163 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 164 DMCUB_REGION3_CW4_ENABLE, 1); 165 } else { 166 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); 167 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); 168 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, 169 DMCUB_REGION4_TOP_ADDRESS, 170 cw4->region.top - cw4->region.base - 1, 171 DMCUB_REGION4_ENABLE, 1); 172 } 173 174 offset = cw5->offset; 175 176 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 177 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 178 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 179 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 180 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 181 DMCUB_REGION3_CW5_ENABLE, 1); 182 183 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); 184 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); 185 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, 186 DMCUB_REGION5_TOP_ADDRESS, 187 cw5->region.top - cw5->region.base - 1, 188 DMCUB_REGION5_ENABLE, 1); 189 190 offset = cw6->offset; 191 192 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 193 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 194 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 195 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 196 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 197 DMCUB_REGION3_CW6_ENABLE, 1); 198 } 199