1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../inc/dmub_srv.h" 27 #include "dmub_reg.h" 28 29 #include "dcn/dcn_2_1_0_offset.h" 30 #include "dcn/dcn_2_1_0_sh_mask.h" 31 #include "renoir_ip_offset.h" 32 33 #define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg 34 #define CTX dmub 35 36 static inline void dmub_dcn21_translate_addr(const union dmub_addr *addr_in, 37 uint64_t fb_base, 38 uint64_t fb_offset, 39 union dmub_addr *addr_out) 40 { 41 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 42 } 43 44 void dmub_dcn21_backdoor_load(struct dmub_srv *dmub, 45 const struct dmub_window *cw0, 46 const struct dmub_window *cw1) 47 { 48 union dmub_addr offset; 49 uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset; 50 51 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 52 REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3, 53 DMCUB_MEM_WRITE_SPACE, 0x3); 54 55 dmub_dcn21_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 56 57 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 58 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 59 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 60 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 61 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 62 DMCUB_REGION3_CW0_ENABLE, 1); 63 64 dmub_dcn21_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 65 66 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 67 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 68 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 69 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 70 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 71 DMCUB_REGION3_CW1_ENABLE, 1); 72 73 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 74 0x20); 75 } 76 77 void dmub_dcn21_setup_windows(struct dmub_srv *dmub, 78 const struct dmub_window *cw2, 79 const struct dmub_window *cw3, 80 const struct dmub_window *cw4, 81 const struct dmub_window *cw5) 82 { 83 union dmub_addr offset; 84 uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset; 85 86 dmub_dcn21_translate_addr(&cw2->offset, fb_base, fb_offset, &offset); 87 88 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); 89 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); 90 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); 91 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, 92 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, 93 DMCUB_REGION3_CW2_ENABLE, 1); 94 95 dmub_dcn21_translate_addr(&cw3->offset, fb_base, fb_offset, &offset); 96 97 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 98 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 99 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 100 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 101 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 102 DMCUB_REGION3_CW3_ENABLE, 1); 103 104 /* TODO: Move this to CW4. */ 105 dmub_dcn21_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); 106 107 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); 108 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); 109 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS, 110 cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE, 111 1); 112 113 dmub_dcn21_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); 114 115 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 116 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 117 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 118 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 119 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 120 DMCUB_REGION3_CW5_ENABLE, 1); 121 } 122 123 bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub) 124 { 125 return (REG_READ(DMCUB_SCRATCH0) == 3); 126 } 127