1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "../dmub_srv.h"
27 #include "dmub_reg.h"
28 #include "dmub_dcn20.h"
29 
30 #include "dcn/dcn_2_0_0_offset.h"
31 #include "dcn/dcn_2_0_0_sh_mask.h"
32 #include "soc15_hw_ip.h"
33 #include "vega10_ip_offset.h"
34 
35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
36 #define CTX dmub
37 #define REGS dmub->regs
38 
39 /* Registers. */
40 
41 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
42 #define DMUB_SR(reg) REG_OFFSET(reg),
43 	{ DMUB_COMMON_REGS() },
44 #undef DMUB_SR
45 
46 #define DMUB_SF(reg, field) FD_MASK(reg, field),
47 	{ DMUB_COMMON_FIELDS() },
48 #undef DMUB_SF
49 
50 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
51 	{ DMUB_COMMON_FIELDS() },
52 #undef DMUB_SF
53 };
54 
55 /* Shared functions. */
56 
57 static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
58 					  uint64_t *fb_base,
59 					  uint64_t *fb_offset)
60 {
61 	uint32_t tmp;
62 
63 	if (dmub->fb_base || dmub->fb_offset) {
64 		*fb_base = dmub->fb_base;
65 		*fb_offset = dmub->fb_offset;
66 		return;
67 	}
68 
69 	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
70 	*fb_base = (uint64_t)tmp << 24;
71 
72 	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
73 	*fb_offset = (uint64_t)tmp << 24;
74 }
75 
76 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
77 					     uint64_t fb_base,
78 					     uint64_t fb_offset,
79 					     union dmub_addr *addr_out)
80 {
81 	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
82 }
83 
84 bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
85 {
86 	/* Cached inbox is not supported in this fw version range */
87 	return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&
88 		 dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0));
89 }
90 
91 void dmub_dcn20_reset(struct dmub_srv *dmub)
92 {
93 	union dmub_gpint_data_register cmd;
94 	const uint32_t timeout = 30;
95 	uint32_t in_reset, scratch, i;
96 
97 	REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset);
98 
99 	if (in_reset == 0) {
100 		cmd.bits.status = 1;
101 		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
102 		cmd.bits.param = 0;
103 
104 		dmub->hw_funcs.set_gpint(dmub, cmd);
105 
106 		/**
107 		 * Timeout covers both the ACK and the wait
108 		 * for remaining work to finish.
109 		 *
110 		 * This is mostly bound by the PHY disable sequence.
111 		 * Each register check will be greater than 1us, so
112 		 * don't bother using udelay.
113 		 */
114 
115 		for (i = 0; i < timeout; ++i) {
116 			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
117 				break;
118 		}
119 
120 		for (i = 0; i < timeout; ++i) {
121 			scratch = dmub->hw_funcs.get_gpint_response(dmub);
122 			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
123 				break;
124 		}
125 
126 		/* Clear the GPINT command manually so we don't reset again. */
127 		cmd.all = 0;
128 		dmub->hw_funcs.set_gpint(dmub, cmd);
129 
130 		/* Force reset in case we timed out, DMCUB is likely hung. */
131 	}
132 
133 	REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
134 	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
135 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
136 	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
137 	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
138 	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
139 	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
140 	REG_WRITE(DMCUB_SCRATCH0, 0);
141 }
142 
143 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
144 {
145 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
146 	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
147 	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
148 	REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
149 }
150 
151 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
152 			      const struct dmub_window *cw0,
153 			      const struct dmub_window *cw1)
154 {
155 	union dmub_addr offset;
156 	uint64_t fb_base, fb_offset;
157 
158 	dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
159 
160 	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
161 	REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
162 		     DMCUB_MEM_WRITE_SPACE, 0x3);
163 
164 	dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
165 
166 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
167 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
168 	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
169 	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
170 		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
171 		  DMCUB_REGION3_CW0_ENABLE, 1);
172 
173 	dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
174 
175 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
176 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
177 	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
178 	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
179 		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
180 		  DMCUB_REGION3_CW1_ENABLE, 1);
181 
182 	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
183 		     0x20);
184 }
185 
186 void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
187 			      const struct dmub_window *cw2,
188 			      const struct dmub_window *cw3,
189 			      const struct dmub_window *cw4,
190 			      const struct dmub_window *cw5,
191 			      const struct dmub_window *cw6)
192 {
193 	union dmub_addr offset;
194 	uint64_t fb_base, fb_offset;
195 
196 	dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
197 
198 	if (cw2->region.base != cw2->region.top) {
199 		dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset,
200 					  &offset);
201 
202 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
203 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
204 		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
205 		REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
206 			  DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
207 			  DMCUB_REGION3_CW2_ENABLE, 1);
208 	} else {
209 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
210 		REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
211 		REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
212 		REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
213 	}
214 
215 	dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
216 
217 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
218 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
219 	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
220 	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
221 		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
222 		  DMCUB_REGION3_CW3_ENABLE, 1);
223 
224 	/* TODO: Move this to CW4. */
225 	dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
226 
227 	/* New firmware can support CW4. */
228 	if (dmub_dcn20_use_cached_inbox(dmub)) {
229 		REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
230 		REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
231 		REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
232 		REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
233 			  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
234 			  DMCUB_REGION3_CW4_ENABLE, 1);
235 	} else {
236 		REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
237 		REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
238 		REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
239 			  DMCUB_REGION4_TOP_ADDRESS,
240 			  cw4->region.top - cw4->region.base - 1,
241 			  DMCUB_REGION4_ENABLE, 1);
242 	}
243 
244 	dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
245 
246 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
247 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
248 	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
249 	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
250 		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
251 		  DMCUB_REGION3_CW5_ENABLE, 1);
252 
253 	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
254 	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
255 	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
256 		  DMCUB_REGION5_TOP_ADDRESS,
257 		  cw5->region.top - cw5->region.base - 1,
258 		  DMCUB_REGION5_ENABLE, 1);
259 
260 	dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
261 
262 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
263 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
264 	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
265 	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
266 		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
267 		  DMCUB_REGION3_CW6_ENABLE, 1);
268 }
269 
270 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
271 			      const struct dmub_region *inbox1)
272 {
273 	/* New firmware can support CW4 for the inbox. */
274 	if (dmub_dcn20_use_cached_inbox(dmub))
275 		REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
276 	else
277 		REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
278 
279 	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
280 }
281 
282 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
283 {
284 	return REG_READ(DMCUB_INBOX1_RPTR);
285 }
286 
287 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
288 {
289 	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
290 }
291 
292 void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,
293 			      const struct dmub_region *outbox1)
294 {
295 	/* New firmware can support CW4 for the outbox. */
296 	if (dmub_dcn20_use_cached_inbox(dmub))
297 		REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
298 	else
299 		REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
300 
301 	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
302 }
303 
304 uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)
305 {
306 	/**
307 	 * outbox1 wptr register is accessed without locks (dal & dc)
308 	 * and to be called only by dmub_srv_stat_get_notification()
309 	 */
310 	return REG_READ(DMCUB_OUTBOX1_WPTR);
311 }
312 
313 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
314 {
315 	/**
316 	 * outbox1 rptr register is accessed without locks (dal & dc)
317 	 * and to be called only by dmub_srv_stat_get_notification()
318 	 */
319 	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
320 }
321 
322 void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,
323 			      const struct dmub_region *outbox0)
324 {
325 	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
326 
327 	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
328 }
329 
330 uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)
331 {
332 	return REG_READ(DMCUB_OUTBOX0_WPTR);
333 }
334 
335 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
336 {
337 	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
338 }
339 
340 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
341 {
342 	uint32_t is_hw_init;
343 
344 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
345 
346 	return is_hw_init != 0;
347 }
348 
349 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
350 {
351 	uint32_t supported = 0;
352 
353 	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
354 
355 	return supported;
356 }
357 
358 void dmub_dcn20_set_gpint(struct dmub_srv *dmub,
359 			  union dmub_gpint_data_register reg)
360 {
361 	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
362 }
363 
364 bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
365 			       union dmub_gpint_data_register reg)
366 {
367 	union dmub_gpint_data_register test;
368 
369 	reg.bits.status = 0;
370 	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
371 
372 	return test.all == reg.all;
373 }
374 
375 uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
376 {
377 	return REG_READ(DMCUB_SCRATCH7);
378 }
379 
380 union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
381 {
382 	union dmub_fw_boot_status status;
383 
384 	status.all = REG_READ(DMCUB_SCRATCH0);
385 	return status;
386 }
387 
388 void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
389 {
390 	union dmub_fw_boot_options boot_options = {0};
391 
392 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
393 }
394 
395 void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
396 {
397 	union dmub_fw_boot_options boot_options;
398 	boot_options.all = REG_READ(DMCUB_SCRATCH14);
399 	boot_options.bits.skip_phy_init_panel_sequence = skip;
400 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
401 }
402