1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_reg.h" 28 #include "dmub_dcn20.h" 29 30 #include "dcn/dcn_2_0_0_offset.h" 31 #include "dcn/dcn_2_0_0_sh_mask.h" 32 #include "soc15_hw_ip.h" 33 #include "vega10_ip_offset.h" 34 35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg 36 #define CTX dmub 37 #define REGS dmub->regs 38 39 /* Registers. */ 40 41 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = { 42 #define DMUB_SR(reg) REG_OFFSET(reg), 43 { DMUB_COMMON_REGS() }, 44 #undef DMUB_SR 45 46 #define DMUB_SF(reg, field) FD_MASK(reg, field), 47 { DMUB_COMMON_FIELDS() }, 48 #undef DMUB_SF 49 50 #define DMUB_SF(reg, field) FD_SHIFT(reg, field), 51 { DMUB_COMMON_FIELDS() }, 52 #undef DMUB_SF 53 }; 54 55 /* Shared functions. */ 56 57 static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub, 58 uint64_t *fb_base, 59 uint64_t *fb_offset) 60 { 61 uint32_t tmp; 62 63 if (dmub->fb_base || dmub->fb_offset) { 64 *fb_base = dmub->fb_base; 65 *fb_offset = dmub->fb_offset; 66 return; 67 } 68 69 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 70 *fb_base = (uint64_t)tmp << 24; 71 72 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 73 *fb_offset = (uint64_t)tmp << 24; 74 } 75 76 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in, 77 uint64_t fb_base, 78 uint64_t fb_offset, 79 union dmub_addr *addr_out) 80 { 81 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 82 } 83 84 bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub) 85 { 86 /* Cached inbox is not supported in this fw version range */ 87 return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) && 88 dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0)); 89 } 90 91 void dmub_dcn20_reset(struct dmub_srv *dmub) 92 { 93 union dmub_gpint_data_register cmd; 94 const uint32_t timeout = 30; 95 uint32_t in_reset, scratch, i; 96 97 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset); 98 99 if (in_reset == 0) { 100 cmd.bits.status = 1; 101 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 102 cmd.bits.param = 0; 103 104 dmub->hw_funcs.set_gpint(dmub, cmd); 105 106 /** 107 * Timeout covers both the ACK and the wait 108 * for remaining work to finish. 109 * 110 * This is mostly bound by the PHY disable sequence. 111 * Each register check will be greater than 1us, so 112 * don't bother using udelay. 113 */ 114 115 for (i = 0; i < timeout; ++i) { 116 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) 117 break; 118 } 119 120 for (i = 0; i < timeout; ++i) { 121 scratch = dmub->hw_funcs.get_gpint_response(dmub); 122 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 123 break; 124 } 125 126 /* Clear the GPINT command manually so we don't reset again. */ 127 cmd.all = 0; 128 dmub->hw_funcs.set_gpint(dmub, cmd); 129 130 /* Force reset in case we timed out, DMCUB is likely hung. */ 131 } 132 133 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1); 134 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 135 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 136 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 137 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 138 REG_WRITE(DMCUB_SCRATCH0, 0); 139 } 140 141 void dmub_dcn20_reset_release(struct dmub_srv *dmub) 142 { 143 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 144 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 145 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 146 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0); 147 } 148 149 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, 150 const struct dmub_window *cw0, 151 const struct dmub_window *cw1) 152 { 153 union dmub_addr offset; 154 uint64_t fb_base, fb_offset; 155 156 dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset); 157 158 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 159 REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3, 160 DMCUB_MEM_WRITE_SPACE, 0x3); 161 162 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 163 164 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 165 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 166 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 167 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 168 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 169 DMCUB_REGION3_CW0_ENABLE, 1); 170 171 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 172 173 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 174 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 175 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 176 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 177 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 178 DMCUB_REGION3_CW1_ENABLE, 1); 179 180 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 181 0x20); 182 } 183 184 void dmub_dcn20_setup_windows(struct dmub_srv *dmub, 185 const struct dmub_window *cw2, 186 const struct dmub_window *cw3, 187 const struct dmub_window *cw4, 188 const struct dmub_window *cw5, 189 const struct dmub_window *cw6) 190 { 191 union dmub_addr offset; 192 uint64_t fb_base, fb_offset; 193 194 dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset); 195 196 if (cw2->region.base != cw2->region.top) { 197 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, 198 &offset); 199 200 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); 201 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); 202 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); 203 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, 204 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, 205 DMCUB_REGION3_CW2_ENABLE, 1); 206 } else { 207 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0); 208 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0); 209 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0); 210 REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0); 211 } 212 213 dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset); 214 215 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 216 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 217 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 218 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 219 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 220 DMCUB_REGION3_CW3_ENABLE, 1); 221 222 /* TODO: Move this to CW4. */ 223 dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); 224 225 /* New firmware can support CW4. */ 226 if (dmub_dcn20_use_cached_inbox(dmub)) { 227 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 228 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 229 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 230 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 231 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 232 DMCUB_REGION3_CW4_ENABLE, 1); 233 } else { 234 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); 235 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); 236 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, 237 DMCUB_REGION4_TOP_ADDRESS, 238 cw4->region.top - cw4->region.base - 1, 239 DMCUB_REGION4_ENABLE, 1); 240 } 241 242 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); 243 244 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 245 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 246 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 247 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 248 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 249 DMCUB_REGION3_CW5_ENABLE, 1); 250 251 dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); 252 253 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 254 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 255 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 256 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 257 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 258 DMCUB_REGION3_CW6_ENABLE, 1); 259 } 260 261 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, 262 const struct dmub_region *inbox1) 263 { 264 /* New firmware can support CW4 for the inbox. */ 265 if (dmub_dcn20_use_cached_inbox(dmub)) 266 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); 267 else 268 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000); 269 270 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 271 } 272 273 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub) 274 { 275 return REG_READ(DMCUB_INBOX1_RPTR); 276 } 277 278 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 279 { 280 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 281 } 282 283 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub) 284 { 285 uint32_t is_hw_init; 286 287 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); 288 289 return is_hw_init != 0; 290 } 291 292 bool dmub_dcn20_is_supported(struct dmub_srv *dmub) 293 { 294 uint32_t supported = 0; 295 296 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); 297 298 return supported; 299 } 300 301 void dmub_dcn20_set_gpint(struct dmub_srv *dmub, 302 union dmub_gpint_data_register reg) 303 { 304 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); 305 } 306 307 bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub, 308 union dmub_gpint_data_register reg) 309 { 310 union dmub_gpint_data_register test; 311 312 reg.bits.status = 0; 313 test.all = REG_READ(DMCUB_GPINT_DATAIN1); 314 315 return test.all == reg.all; 316 } 317 318 uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub) 319 { 320 return REG_READ(DMCUB_SCRATCH7); 321 } 322 323 union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub) 324 { 325 union dmub_fw_boot_status status; 326 327 status.all = REG_READ(DMCUB_SCRATCH0); 328 return status; 329 } 330 331 void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub) 332 { 333 union dmub_fw_boot_options boot_options = {0}; 334 335 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 336 } 337 338 void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 339 { 340 union dmub_fw_boot_options boot_options; 341 boot_options.all = REG_READ(DMCUB_SCRATCH14); 342 boot_options.bits.skip_phy_init_panel_sequence = skip; 343 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 344 } 345