1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 #define ABM_NUM_OF_ACE_SEGMENTS 5 174 175 union abm_flags { 176 struct { 177 /** 178 * @abm_enabled: Indicates if ABM is enabled. 179 */ 180 unsigned int abm_enabled : 1; 181 182 /** 183 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 184 */ 185 unsigned int disable_abm_requested : 1; 186 187 /** 188 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled 189 * immediately. 190 */ 191 unsigned int disable_abm_immediately : 1; 192 193 /** 194 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 195 * to be disabled immediately and keep gain. 196 */ 197 unsigned int disable_abm_immediate_keep_gain : 1; 198 199 /** 200 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 201 */ 202 unsigned int fractional_pwm : 1; 203 204 /** 205 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 206 * of user backlight level. 207 */ 208 unsigned int abm_gradual_bl_change : 1; 209 } bitfields; 210 211 unsigned int u32All; 212 }; 213 214 struct abm_save_restore { 215 /** 216 * @flags: Misc. ABM flags. 217 */ 218 union abm_flags flags; 219 220 /** 221 * @pause: true: pause ABM and get state 222 * false: unpause ABM after setting state 223 */ 224 uint32_t pause; 225 226 /** 227 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 228 */ 229 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 230 231 /** 232 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 233 */ 234 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 235 236 /** 237 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 238 */ 239 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 240 241 242 /** 243 * @knee_threshold: Current x-position of ACE knee (u0.16). 244 */ 245 uint32_t knee_threshold; 246 /** 247 * @current_gain: Current backlight reduction (u16.16). 248 */ 249 uint32_t current_gain; 250 /** 251 * @curr_bl_level: Current actual backlight level converging to target backlight level. 252 */ 253 uint16_t curr_bl_level; 254 255 /** 256 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 257 */ 258 uint16_t curr_user_bl_level; 259 260 }; 261 262 /** 263 * union dmub_addr - DMUB physical/virtual 64-bit address. 264 */ 265 union dmub_addr { 266 struct { 267 uint32_t low_part; /**< Lower 32 bits */ 268 uint32_t high_part; /**< Upper 32 bits */ 269 } u; /*<< Low/high bit access */ 270 uint64_t quad_part; /*<< 64 bit address */ 271 }; 272 #pragma pack(pop) 273 274 /** 275 * Dirty rect definition. 276 */ 277 struct dmub_rect { 278 /** 279 * Dirty rect x offset. 280 */ 281 uint32_t x; 282 283 /** 284 * Dirty rect y offset. 285 */ 286 uint32_t y; 287 288 /** 289 * Dirty rect width. 290 */ 291 uint32_t width; 292 293 /** 294 * Dirty rect height. 295 */ 296 uint32_t height; 297 }; 298 299 /** 300 * Flags that can be set by driver to change some PSR behaviour. 301 */ 302 union dmub_psr_debug_flags { 303 /** 304 * Debug flags. 305 */ 306 struct { 307 /** 308 * Enable visual confirm in FW. 309 */ 310 uint32_t visual_confirm : 1; 311 312 /** 313 * Force all selective updates to bw full frame updates. 314 */ 315 uint32_t force_full_frame_update : 1; 316 317 /** 318 * Use HW Lock Mgr object to do HW locking in FW. 319 */ 320 uint32_t use_hw_lock_mgr : 1; 321 322 /** 323 * Use TPS3 signal when restore main link. 324 */ 325 uint32_t force_wakeup_by_tps3 : 1; 326 327 /** 328 * Back to back flip, therefore cannot power down PHY 329 */ 330 uint32_t back_to_back_flip : 1; 331 332 } bitfields; 333 334 /** 335 * Union for debug flags. 336 */ 337 uint32_t u32All; 338 }; 339 340 /** 341 * Flags that can be set by driver to change some Replay behaviour. 342 */ 343 union replay_debug_flags { 344 struct { 345 /** 346 * Enable visual confirm in FW. 347 */ 348 uint32_t visual_confirm : 1; 349 350 /** 351 * @skip_crc: Set if need to skip CRC. 352 */ 353 uint32_t skip_crc : 1; 354 355 /** 356 * @force_link_power_on: Force disable ALPM control 357 */ 358 uint32_t force_link_power_on : 1; 359 360 /** 361 * @force_phy_power_on: Force phy power on 362 */ 363 uint32_t force_phy_power_on : 1; 364 365 /** 366 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 367 */ 368 uint32_t timing_resync_disabled : 1; 369 370 /** 371 * @skip_crtc_disabled: CRTC disable skipped 372 */ 373 uint32_t skip_crtc_disabled : 1; 374 375 /** 376 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 377 */ 378 uint32_t force_defer_one_frame_update : 1; 379 /** 380 * @disable_delay_alpm_on: Force disable delay alpm on 381 */ 382 uint32_t disable_delay_alpm_on : 1; 383 /** 384 * @disable_desync_error_check: Force disable desync error check 385 */ 386 uint32_t disable_desync_error_check : 1; 387 /** 388 * @disable_desync_error_check: Force disable desync error check 389 */ 390 uint32_t disable_dmub_save_restore : 1; 391 392 uint32_t reserved : 22; 393 } bitfields; 394 395 uint32_t u32All; 396 }; 397 398 union replay_hw_flags { 399 struct { 400 /** 401 * @allow_alpm_fw_standby_mode: To indicate whether the 402 * ALPM FW standby mode is allowed 403 */ 404 uint32_t allow_alpm_fw_standby_mode : 1; 405 406 /* 407 * @dsc_enable_status: DSC enable status in driver 408 */ 409 uint32_t dsc_enable_status : 1; 410 411 /** 412 * @fec_enable_status: receive fec enable/disable status from driver 413 */ 414 uint32_t fec_enable_status : 1; 415 416 /* 417 * @smu_optimizations_en: SMU power optimization. 418 * Only when active display is Replay capable and display enters Replay. 419 * Trigger interrupt to SMU to powerup/down. 420 */ 421 uint32_t smu_optimizations_en : 1; 422 423 /** 424 * @otg_powered_down: Flag to keep track of OTG power state. 425 */ 426 uint32_t otg_powered_down : 1; 427 428 /** 429 * @phy_power_state: Indicates current phy power state 430 */ 431 uint32_t phy_power_state : 1; 432 433 /** 434 * @link_power_state: Indicates current link power state 435 */ 436 uint32_t link_power_state : 1; 437 /** 438 * Use TPS3 signal when restore main link. 439 */ 440 uint32_t force_wakeup_by_tps3 : 1; 441 } bitfields; 442 443 uint32_t u32All; 444 }; 445 446 /** 447 * DMUB visual confirm color 448 */ 449 struct dmub_feature_caps { 450 /** 451 * Max PSR version supported by FW. 452 */ 453 uint8_t psr; 454 uint8_t fw_assisted_mclk_switch; 455 uint8_t reserved[4]; 456 uint8_t subvp_psr_support; 457 uint8_t gecc_enable; 458 }; 459 460 struct dmub_visual_confirm_color { 461 /** 462 * Maximum 10 bits color value 463 */ 464 uint16_t color_r_cr; 465 uint16_t color_g_y; 466 uint16_t color_b_cb; 467 uint16_t panel_inst; 468 }; 469 470 #if defined(__cplusplus) 471 } 472 #endif 473 474 //============================================================================== 475 //</DMUB_TYPES>================================================================= 476 //============================================================================== 477 //< DMUB_META>================================================================== 478 //============================================================================== 479 #pragma pack(push, 1) 480 481 /* Magic value for identifying dmub_fw_meta_info */ 482 #define DMUB_FW_META_MAGIC 0x444D5542 483 484 /* Offset from the end of the file to the dmub_fw_meta_info */ 485 #define DMUB_FW_META_OFFSET 0x24 486 487 /** 488 * struct dmub_fw_meta_info - metadata associated with fw binary 489 * 490 * NOTE: This should be considered a stable API. Fields should 491 * not be repurposed or reordered. New fields should be 492 * added instead to extend the structure. 493 * 494 * @magic_value: magic value identifying DMUB firmware meta info 495 * @fw_region_size: size of the firmware state region 496 * @trace_buffer_size: size of the tracebuffer region 497 * @fw_version: the firmware version information 498 * @dal_fw: 1 if the firmware is DAL 499 */ 500 struct dmub_fw_meta_info { 501 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 502 uint32_t fw_region_size; /**< size of the firmware state region */ 503 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 504 uint32_t fw_version; /**< the firmware version information */ 505 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 506 uint8_t reserved[3]; /**< padding bits */ 507 }; 508 509 /** 510 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 511 */ 512 union dmub_fw_meta { 513 struct dmub_fw_meta_info info; /**< metadata info */ 514 uint8_t reserved[64]; /**< padding bits */ 515 }; 516 517 #pragma pack(pop) 518 519 //============================================================================== 520 //< DMUB Trace Buffer>================================================================ 521 //============================================================================== 522 /** 523 * dmub_trace_code_t - firmware trace code, 32-bits 524 */ 525 typedef uint32_t dmub_trace_code_t; 526 527 /** 528 * struct dmcub_trace_buf_entry - Firmware trace entry 529 */ 530 struct dmcub_trace_buf_entry { 531 dmub_trace_code_t trace_code; /**< trace code for the event */ 532 uint32_t tick_count; /**< the tick count at time of trace */ 533 uint32_t param0; /**< trace defined parameter 0 */ 534 uint32_t param1; /**< trace defined parameter 1 */ 535 }; 536 537 //============================================================================== 538 //< DMUB_STATUS>================================================================ 539 //============================================================================== 540 541 /** 542 * DMCUB scratch registers can be used to determine firmware status. 543 * Current scratch register usage is as follows: 544 * 545 * SCRATCH0: FW Boot Status register 546 * SCRATCH5: LVTMA Status Register 547 * SCRATCH15: FW Boot Options register 548 */ 549 550 /** 551 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 552 */ 553 union dmub_fw_boot_status { 554 struct { 555 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 556 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 557 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 558 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 559 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 560 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 561 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 562 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 563 } bits; /**< status bits */ 564 uint32_t all; /**< 32-bit access to status bits */ 565 }; 566 567 /** 568 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 569 */ 570 enum dmub_fw_boot_status_bit { 571 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 572 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 573 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 574 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 575 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 576 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 577 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 578 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 579 }; 580 581 /* Register bit definition for SCRATCH5 */ 582 union dmub_lvtma_status { 583 struct { 584 uint32_t psp_ok : 1; 585 uint32_t edp_on : 1; 586 uint32_t reserved : 30; 587 } bits; 588 uint32_t all; 589 }; 590 591 enum dmub_lvtma_status_bit { 592 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 593 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 594 }; 595 596 enum dmub_ips_disable_type { 597 DMUB_IPS_DISABLE_IPS1 = 1, 598 DMUB_IPS_DISABLE_IPS2 = 2, 599 DMUB_IPS_DISABLE_IPS2_Z10 = 3, 600 }; 601 602 /** 603 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 604 */ 605 union dmub_fw_boot_options { 606 struct { 607 uint32_t pemu_env : 1; /**< 1 if PEMU */ 608 uint32_t fpga_env : 1; /**< 1 if FPGA */ 609 uint32_t optimized_init : 1; /**< 1 if optimized init */ 610 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 611 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 612 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 613 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 614 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 615 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 616 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 617 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 618 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 619 uint32_t power_optimization: 1; 620 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 621 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 622 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 623 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 624 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 625 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 626 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 627 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 628 uint32_t ips_disable: 2; /* options to disable ips support*/ 629 uint32_t reserved : 10; /**< reserved */ 630 } bits; /**< boot bits */ 631 uint32_t all; /**< 32-bit access to bits */ 632 }; 633 634 enum dmub_fw_boot_options_bit { 635 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 636 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 637 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 638 }; 639 640 //============================================================================== 641 //</DMUB_STATUS>================================================================ 642 //============================================================================== 643 //< DMUB_VBIOS>================================================================= 644 //============================================================================== 645 646 /* 647 * enum dmub_cmd_vbios_type - VBIOS commands. 648 * 649 * Command IDs should be treated as stable ABI. 650 * Do not reuse or modify IDs. 651 */ 652 enum dmub_cmd_vbios_type { 653 /** 654 * Configures the DIG encoder. 655 */ 656 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 657 /** 658 * Controls the PHY. 659 */ 660 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 661 /** 662 * Sets the pixel clock/symbol clock. 663 */ 664 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 665 /** 666 * Enables or disables power gating. 667 */ 668 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 669 /** 670 * Controls embedded panels. 671 */ 672 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 673 /** 674 * Query DP alt status on a transmitter. 675 */ 676 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 677 /** 678 * Controls domain power gating 679 */ 680 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 681 }; 682 683 //============================================================================== 684 //</DMUB_VBIOS>================================================================= 685 //============================================================================== 686 //< DMUB_GPINT>================================================================= 687 //============================================================================== 688 689 /** 690 * The shifts and masks below may alternatively be used to format and read 691 * the command register bits. 692 */ 693 694 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 695 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 696 697 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 698 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 699 700 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 701 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 702 703 /** 704 * Command responses. 705 */ 706 707 /** 708 * Return response for DMUB_GPINT__STOP_FW command. 709 */ 710 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 711 712 /** 713 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 714 */ 715 union dmub_gpint_data_register { 716 struct { 717 uint32_t param : 16; /**< 16-bit parameter */ 718 uint32_t command_code : 12; /**< GPINT command */ 719 uint32_t status : 4; /**< Command status bit */ 720 } bits; /**< GPINT bit access */ 721 uint32_t all; /**< GPINT 32-bit access */ 722 }; 723 724 /* 725 * enum dmub_gpint_command - GPINT command to DMCUB FW 726 * 727 * Command IDs should be treated as stable ABI. 728 * Do not reuse or modify IDs. 729 */ 730 enum dmub_gpint_command { 731 /** 732 * Invalid command, ignored. 733 */ 734 DMUB_GPINT__INVALID_COMMAND = 0, 735 /** 736 * DESC: Queries the firmware version. 737 * RETURN: Firmware version. 738 */ 739 DMUB_GPINT__GET_FW_VERSION = 1, 740 /** 741 * DESC: Halts the firmware. 742 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 743 */ 744 DMUB_GPINT__STOP_FW = 2, 745 /** 746 * DESC: Get PSR state from FW. 747 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 748 */ 749 DMUB_GPINT__GET_PSR_STATE = 7, 750 /** 751 * DESC: Notifies DMCUB of the currently active streams. 752 * ARGS: Stream mask, 1 bit per active stream index. 753 */ 754 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 755 /** 756 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 757 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 758 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 759 * RETURN: PSR residency in milli-percent. 760 */ 761 DMUB_GPINT__PSR_RESIDENCY = 9, 762 763 /** 764 * DESC: Get REPLAY state from FW. 765 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 766 */ 767 DMUB_GPINT__GET_REPLAY_STATE = 13, 768 769 /** 770 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 771 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 772 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 773 * RETURN: REPLAY residency in milli-percent. 774 */ 775 DMUB_GPINT__REPLAY_RESIDENCY = 14, 776 777 778 /** 779 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 780 */ 781 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 782 }; 783 784 /** 785 * INBOX0 generic command definition 786 */ 787 union dmub_inbox0_cmd_common { 788 struct { 789 uint32_t command_code: 8; /**< INBOX0 command code */ 790 uint32_t param: 24; /**< 24-bit parameter */ 791 } bits; 792 uint32_t all; 793 }; 794 795 /** 796 * INBOX0 hw_lock command definition 797 */ 798 union dmub_inbox0_cmd_lock_hw { 799 struct { 800 uint32_t command_code: 8; 801 802 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 803 uint32_t hw_lock_client: 2; 804 805 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 806 uint32_t otg_inst: 3; 807 uint32_t opp_inst: 3; 808 uint32_t dig_inst: 3; 809 810 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 811 uint32_t lock_pipe: 1; 812 uint32_t lock_cursor: 1; 813 uint32_t lock_dig: 1; 814 uint32_t triple_buffer_lock: 1; 815 816 uint32_t lock: 1; /**< Lock */ 817 uint32_t should_release: 1; /**< Release */ 818 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 819 } bits; 820 uint32_t all; 821 }; 822 823 union dmub_inbox0_data_register { 824 union dmub_inbox0_cmd_common inbox0_cmd_common; 825 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 826 }; 827 828 enum dmub_inbox0_command { 829 /** 830 * DESC: Invalid command, ignored. 831 */ 832 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 833 /** 834 * DESC: Notification to acquire/release HW lock 835 * ARGS: 836 */ 837 DMUB_INBOX0_CMD__HW_LOCK = 1, 838 }; 839 //============================================================================== 840 //</DMUB_GPINT>================================================================= 841 //============================================================================== 842 //< DMUB_CMD>=================================================================== 843 //============================================================================== 844 845 /** 846 * Size in bytes of each DMUB command. 847 */ 848 #define DMUB_RB_CMD_SIZE 64 849 850 /** 851 * Maximum number of items in the DMUB ringbuffer. 852 */ 853 #define DMUB_RB_MAX_ENTRY 128 854 855 /** 856 * Ringbuffer size in bytes. 857 */ 858 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 859 860 /** 861 * REG_SET mask for reg offload. 862 */ 863 #define REG_SET_MASK 0xFFFF 864 865 /* 866 * enum dmub_cmd_type - DMUB inbox command. 867 * 868 * Command IDs should be treated as stable ABI. 869 * Do not reuse or modify IDs. 870 */ 871 enum dmub_cmd_type { 872 /** 873 * Invalid command. 874 */ 875 DMUB_CMD__NULL = 0, 876 /** 877 * Read modify write register sequence offload. 878 */ 879 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 880 /** 881 * Field update register sequence offload. 882 */ 883 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 884 /** 885 * Burst write sequence offload. 886 */ 887 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 888 /** 889 * Reg wait sequence offload. 890 */ 891 DMUB_CMD__REG_REG_WAIT = 4, 892 /** 893 * Workaround to avoid HUBP underflow during NV12 playback. 894 */ 895 DMUB_CMD__PLAT_54186_WA = 5, 896 /** 897 * Command type used to query FW feature caps. 898 */ 899 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 900 /** 901 * Command type used to get visual confirm color. 902 */ 903 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 904 /** 905 * Command type used for all PSR commands. 906 */ 907 DMUB_CMD__PSR = 64, 908 /** 909 * Command type used for all MALL commands. 910 */ 911 DMUB_CMD__MALL = 65, 912 /** 913 * Command type used for all ABM commands. 914 */ 915 DMUB_CMD__ABM = 66, 916 /** 917 * Command type used to update dirty rects in FW. 918 */ 919 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 920 /** 921 * Command type used to update cursor info in FW. 922 */ 923 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 924 /** 925 * Command type used for HW locking in FW. 926 */ 927 DMUB_CMD__HW_LOCK = 69, 928 /** 929 * Command type used to access DP AUX. 930 */ 931 DMUB_CMD__DP_AUX_ACCESS = 70, 932 /** 933 * Command type used for OUTBOX1 notification enable 934 */ 935 DMUB_CMD__OUTBOX1_ENABLE = 71, 936 937 /** 938 * Command type used for all idle optimization commands. 939 */ 940 DMUB_CMD__IDLE_OPT = 72, 941 /** 942 * Command type used for all clock manager commands. 943 */ 944 DMUB_CMD__CLK_MGR = 73, 945 /** 946 * Command type used for all panel control commands. 947 */ 948 DMUB_CMD__PANEL_CNTL = 74, 949 /** 950 * Command type used for <TODO:description> 951 */ 952 DMUB_CMD__CAB_FOR_SS = 75, 953 954 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 955 956 /** 957 * Command type used for interfacing with DPIA. 958 */ 959 DMUB_CMD__DPIA = 77, 960 /** 961 * Command type used for EDID CEA parsing 962 */ 963 DMUB_CMD__EDID_CEA = 79, 964 /** 965 * Command type used for getting usbc cable ID 966 */ 967 DMUB_CMD_GET_USBC_CABLE_ID = 81, 968 /** 969 * Command type used to query HPD state. 970 */ 971 DMUB_CMD__QUERY_HPD_STATE = 82, 972 /** 973 * Command type used for all VBIOS interface commands. 974 */ 975 976 /** 977 * Command type used for all REPLAY commands. 978 */ 979 DMUB_CMD__REPLAY = 83, 980 981 /** 982 * Command type used for all SECURE_DISPLAY commands. 983 */ 984 DMUB_CMD__SECURE_DISPLAY = 85, 985 986 /** 987 * Command type used to set DPIA HPD interrupt state 988 */ 989 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 990 991 DMUB_CMD__VBIOS = 128, 992 }; 993 994 /** 995 * enum dmub_out_cmd_type - DMUB outbox commands. 996 */ 997 enum dmub_out_cmd_type { 998 /** 999 * Invalid outbox command, ignored. 1000 */ 1001 DMUB_OUT_CMD__NULL = 0, 1002 /** 1003 * Command type used for DP AUX Reply data notification 1004 */ 1005 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1006 /** 1007 * Command type used for DP HPD event notification 1008 */ 1009 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1010 /** 1011 * Command type used for SET_CONFIG Reply notification 1012 */ 1013 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1014 /** 1015 * Command type used for USB4 DPIA notification 1016 */ 1017 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1018 }; 1019 1020 /* DMUB_CMD__DPIA command sub-types. */ 1021 enum dmub_cmd_dpia_type { 1022 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1023 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1024 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1025 }; 1026 1027 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1028 enum dmub_cmd_dpia_notification_type { 1029 DPIA_NOTIFY__BW_ALLOCATION = 0, 1030 }; 1031 1032 #pragma pack(push, 1) 1033 1034 /** 1035 * struct dmub_cmd_header - Common command header fields. 1036 */ 1037 struct dmub_cmd_header { 1038 unsigned int type : 8; /**< command type */ 1039 unsigned int sub_type : 8; /**< command sub type */ 1040 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1041 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1042 unsigned int reserved0 : 6; /**< reserved bits */ 1043 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1044 unsigned int reserved1 : 2; /**< reserved bits */ 1045 }; 1046 1047 /* 1048 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1049 * 1050 * 60 payload bytes can hold up to 5 sets of read modify writes, 1051 * each take 3 dwords. 1052 * 1053 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1054 * 1055 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1056 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1057 */ 1058 struct dmub_cmd_read_modify_write_sequence { 1059 uint32_t addr; /**< register address */ 1060 uint32_t modify_mask; /**< modify mask */ 1061 uint32_t modify_value; /**< modify value */ 1062 }; 1063 1064 /** 1065 * Maximum number of ops in read modify write sequence. 1066 */ 1067 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1068 1069 /** 1070 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1071 */ 1072 struct dmub_rb_cmd_read_modify_write { 1073 struct dmub_cmd_header header; /**< command header */ 1074 /** 1075 * Read modify write sequence. 1076 */ 1077 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1078 }; 1079 1080 /* 1081 * Update a register with specified masks and values sequeunce 1082 * 1083 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1084 * 1085 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1086 * 1087 * 1088 * USE CASE: 1089 * 1. auto-increment register where additional read would update pointer and produce wrong result 1090 * 2. toggle a bit without read in the middle 1091 */ 1092 1093 struct dmub_cmd_reg_field_update_sequence { 1094 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1095 uint32_t modify_value; /**< value to update with */ 1096 }; 1097 1098 /** 1099 * Maximum number of ops in field update sequence. 1100 */ 1101 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1102 1103 /** 1104 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1105 */ 1106 struct dmub_rb_cmd_reg_field_update_sequence { 1107 struct dmub_cmd_header header; /**< command header */ 1108 uint32_t addr; /**< register address */ 1109 /** 1110 * Field update sequence. 1111 */ 1112 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1113 }; 1114 1115 1116 /** 1117 * Maximum number of burst write values. 1118 */ 1119 #define DMUB_BURST_WRITE_VALUES__MAX 14 1120 1121 /* 1122 * struct dmub_rb_cmd_burst_write - Burst write 1123 * 1124 * support use case such as writing out LUTs. 1125 * 1126 * 60 payload bytes can hold up to 14 values to write to given address 1127 * 1128 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1129 */ 1130 struct dmub_rb_cmd_burst_write { 1131 struct dmub_cmd_header header; /**< command header */ 1132 uint32_t addr; /**< register start address */ 1133 /** 1134 * Burst write register values. 1135 */ 1136 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1137 }; 1138 1139 /** 1140 * struct dmub_rb_cmd_common - Common command header 1141 */ 1142 struct dmub_rb_cmd_common { 1143 struct dmub_cmd_header header; /**< command header */ 1144 /** 1145 * Padding to RB_CMD_SIZE 1146 */ 1147 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1148 }; 1149 1150 /** 1151 * struct dmub_cmd_reg_wait_data - Register wait data 1152 */ 1153 struct dmub_cmd_reg_wait_data { 1154 uint32_t addr; /**< Register address */ 1155 uint32_t mask; /**< Mask for register bits */ 1156 uint32_t condition_field_value; /**< Value to wait for */ 1157 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1158 }; 1159 1160 /** 1161 * struct dmub_rb_cmd_reg_wait - Register wait command 1162 */ 1163 struct dmub_rb_cmd_reg_wait { 1164 struct dmub_cmd_header header; /**< Command header */ 1165 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1166 }; 1167 1168 /** 1169 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1170 * 1171 * Reprograms surface parameters to avoid underflow. 1172 */ 1173 struct dmub_cmd_PLAT_54186_wa { 1174 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1175 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1176 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1177 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1178 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1179 struct { 1180 uint8_t hubp_inst : 4; /**< HUBP instance */ 1181 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 1182 uint8_t immediate :1; /**< Immediate flip */ 1183 uint8_t vmid : 4; /**< VMID */ 1184 uint8_t grph_stereo : 1; /**< 1 if stereo */ 1185 uint32_t reserved : 21; /**< Reserved */ 1186 } flip_params; /**< Pageflip parameters */ 1187 uint32_t reserved[9]; /**< Reserved bits */ 1188 }; 1189 1190 /** 1191 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1192 */ 1193 struct dmub_rb_cmd_PLAT_54186_wa { 1194 struct dmub_cmd_header header; /**< Command header */ 1195 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1196 }; 1197 1198 /** 1199 * struct dmub_rb_cmd_mall - MALL command data. 1200 */ 1201 struct dmub_rb_cmd_mall { 1202 struct dmub_cmd_header header; /**< Common command header */ 1203 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1204 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1205 uint32_t tmr_delay; /**< Timer delay */ 1206 uint32_t tmr_scale; /**< Timer scale */ 1207 uint16_t cursor_width; /**< Cursor width in pixels */ 1208 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1209 uint16_t cursor_height; /**< Cursor height in pixels */ 1210 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1211 uint8_t debug_bits; /**< Debug bits */ 1212 1213 uint8_t reserved1; /**< Reserved bits */ 1214 uint8_t reserved2; /**< Reserved bits */ 1215 }; 1216 1217 /** 1218 * enum dmub_cmd_cab_type - CAB command data. 1219 */ 1220 enum dmub_cmd_cab_type { 1221 /** 1222 * No idle optimizations (i.e. no CAB) 1223 */ 1224 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1225 /** 1226 * No DCN requests for memory 1227 */ 1228 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1229 /** 1230 * Fit surfaces in CAB (i.e. CAB enable) 1231 */ 1232 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1233 }; 1234 1235 /** 1236 * struct dmub_rb_cmd_cab - CAB command data. 1237 */ 1238 struct dmub_rb_cmd_cab_for_ss { 1239 struct dmub_cmd_header header; 1240 uint8_t cab_alloc_ways; /* total number of ways */ 1241 uint8_t debug_bits; /* debug bits */ 1242 }; 1243 1244 /** 1245 * Enum for indicating which MCLK switch mode per pipe 1246 */ 1247 enum mclk_switch_mode { 1248 NONE = 0, 1249 FPO = 1, 1250 SUBVP = 2, 1251 VBLANK = 3, 1252 }; 1253 1254 /* Per pipe struct which stores the MCLK switch mode 1255 * data to be sent to DMUB. 1256 * Named "v2" for now -- once FPO and SUBVP are fully merged 1257 * the type name can be updated 1258 */ 1259 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1260 union { 1261 struct { 1262 uint32_t pix_clk_100hz; 1263 uint16_t main_vblank_start; 1264 uint16_t main_vblank_end; 1265 uint16_t mall_region_lines; 1266 uint16_t prefetch_lines; 1267 uint16_t prefetch_to_mall_start_lines; 1268 uint16_t processing_delay_lines; 1269 uint16_t htotal; // required to calculate line time for multi-display cases 1270 uint16_t vtotal; 1271 uint8_t main_pipe_index; 1272 uint8_t phantom_pipe_index; 1273 /* Since the microschedule is calculated in terms of OTG lines, 1274 * include any scaling factors to make sure when we get accurate 1275 * conversion when programming MALL_START_LINE (which is in terms 1276 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1277 * is 1/2 (numerator = 1, denominator = 2). 1278 */ 1279 uint8_t scale_factor_numerator; 1280 uint8_t scale_factor_denominator; 1281 uint8_t is_drr; 1282 uint8_t main_split_pipe_index; 1283 uint8_t phantom_split_pipe_index; 1284 } subvp_data; 1285 1286 struct { 1287 uint32_t pix_clk_100hz; 1288 uint16_t vblank_start; 1289 uint16_t vblank_end; 1290 uint16_t vstartup_start; 1291 uint16_t vtotal; 1292 uint16_t htotal; 1293 uint8_t vblank_pipe_index; 1294 uint8_t padding[1]; 1295 struct { 1296 uint8_t drr_in_use; 1297 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1298 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1299 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1300 uint8_t use_ramping; // Use ramping or not 1301 uint8_t drr_vblank_start_margin; 1302 } drr_info; // DRR considered as part of SubVP + VBLANK case 1303 } vblank_data; 1304 } pipe_config; 1305 1306 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1307 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1308 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1309 */ 1310 uint8_t mode; // enum mclk_switch_mode 1311 }; 1312 1313 /** 1314 * Config data for Sub-VP and FPO 1315 * Named "v2" for now -- once FPO and SUBVP are fully merged 1316 * the type name can be updated 1317 */ 1318 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1319 uint16_t watermark_a_cache; 1320 uint8_t vertical_int_margin_us; 1321 uint8_t pstate_allow_width_us; 1322 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1323 }; 1324 1325 /** 1326 * DMUB rb command definition for Sub-VP and FPO 1327 * Named "v2" for now -- once FPO and SUBVP are fully merged 1328 * the type name can be updated 1329 */ 1330 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1331 struct dmub_cmd_header header; 1332 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1333 }; 1334 1335 /** 1336 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1337 */ 1338 enum dmub_cmd_idle_opt_type { 1339 /** 1340 * DCN hardware restore. 1341 */ 1342 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1343 1344 /** 1345 * DCN hardware save. 1346 */ 1347 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1348 1349 /** 1350 * DCN hardware notify idle. 1351 */ 1352 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1353 }; 1354 1355 /** 1356 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1357 */ 1358 struct dmub_rb_cmd_idle_opt_dcn_restore { 1359 struct dmub_cmd_header header; /**< header */ 1360 }; 1361 1362 /** 1363 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1364 */ 1365 struct dmub_dcn_notify_idle_cntl_data { 1366 uint8_t driver_idle; 1367 uint8_t pad[1]; 1368 }; 1369 1370 /** 1371 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1372 */ 1373 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1374 struct dmub_cmd_header header; /**< header */ 1375 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1376 }; 1377 1378 /** 1379 * struct dmub_clocks - Clock update notification. 1380 */ 1381 struct dmub_clocks { 1382 uint32_t dispclk_khz; /**< dispclk kHz */ 1383 uint32_t dppclk_khz; /**< dppclk kHz */ 1384 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1385 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1386 }; 1387 1388 /** 1389 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1390 */ 1391 enum dmub_cmd_clk_mgr_type { 1392 /** 1393 * Notify DMCUB of clock update. 1394 */ 1395 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1396 }; 1397 1398 /** 1399 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1400 */ 1401 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1402 struct dmub_cmd_header header; /**< header */ 1403 struct dmub_clocks clocks; /**< clock data */ 1404 }; 1405 1406 /** 1407 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1408 */ 1409 struct dmub_cmd_digx_encoder_control_data { 1410 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1411 }; 1412 1413 /** 1414 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1415 */ 1416 struct dmub_rb_cmd_digx_encoder_control { 1417 struct dmub_cmd_header header; /**< header */ 1418 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1419 }; 1420 1421 /** 1422 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1423 */ 1424 struct dmub_cmd_set_pixel_clock_data { 1425 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1426 }; 1427 1428 /** 1429 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1430 */ 1431 struct dmub_rb_cmd_set_pixel_clock { 1432 struct dmub_cmd_header header; /**< header */ 1433 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1434 }; 1435 1436 /** 1437 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1438 */ 1439 struct dmub_cmd_enable_disp_power_gating_data { 1440 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1441 }; 1442 1443 /** 1444 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1445 */ 1446 struct dmub_rb_cmd_enable_disp_power_gating { 1447 struct dmub_cmd_header header; /**< header */ 1448 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1449 }; 1450 1451 /** 1452 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1453 */ 1454 struct dmub_dig_transmitter_control_data_v1_7 { 1455 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1456 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1457 union { 1458 uint8_t digmode; /**< enum atom_encode_mode_def */ 1459 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1460 } mode_laneset; 1461 uint8_t lanenum; /**< Number of lanes */ 1462 union { 1463 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1464 } symclk_units; 1465 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1466 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1467 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1468 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1469 uint8_t reserved1; /**< For future use */ 1470 uint8_t reserved2[3]; /**< For future use */ 1471 uint32_t reserved3[11]; /**< For future use */ 1472 }; 1473 1474 /** 1475 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1476 */ 1477 union dmub_cmd_dig1_transmitter_control_data { 1478 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1479 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1480 }; 1481 1482 /** 1483 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1484 */ 1485 struct dmub_rb_cmd_dig1_transmitter_control { 1486 struct dmub_cmd_header header; /**< header */ 1487 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1488 }; 1489 1490 /** 1491 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1492 */ 1493 struct dmub_rb_cmd_domain_control_data { 1494 uint8_t inst : 6; /**< DOMAIN instance to control */ 1495 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1496 uint8_t reserved[3]; /**< Reserved for future use */ 1497 }; 1498 1499 /** 1500 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1501 */ 1502 struct dmub_rb_cmd_domain_control { 1503 struct dmub_cmd_header header; /**< header */ 1504 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1505 }; 1506 1507 /** 1508 * DPIA tunnel command parameters. 1509 */ 1510 struct dmub_cmd_dig_dpia_control_data { 1511 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1512 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1513 union { 1514 uint8_t digmode; /** enum atom_encode_mode_def */ 1515 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1516 } mode_laneset; 1517 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1518 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1519 uint8_t hpdsel; /** =0: HPD is not assigned */ 1520 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1521 uint8_t dpia_id; /** Index of DPIA */ 1522 uint8_t fec_rdy : 1; 1523 uint8_t reserved : 7; 1524 uint32_t reserved1; 1525 }; 1526 1527 /** 1528 * DMUB command for DPIA tunnel control. 1529 */ 1530 struct dmub_rb_cmd_dig1_dpia_control { 1531 struct dmub_cmd_header header; 1532 struct dmub_cmd_dig_dpia_control_data dpia_control; 1533 }; 1534 1535 /** 1536 * SET_CONFIG Command Payload 1537 */ 1538 struct set_config_cmd_payload { 1539 uint8_t msg_type; /* set config message type */ 1540 uint8_t msg_data; /* set config message data */ 1541 }; 1542 1543 /** 1544 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1545 */ 1546 struct dmub_cmd_set_config_control_data { 1547 struct set_config_cmd_payload cmd_pkt; 1548 uint8_t instance; /* DPIA instance */ 1549 uint8_t immed_status; /* Immediate status returned in case of error */ 1550 }; 1551 1552 /** 1553 * DMUB command structure for SET_CONFIG command. 1554 */ 1555 struct dmub_rb_cmd_set_config_access { 1556 struct dmub_cmd_header header; /* header */ 1557 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1558 }; 1559 1560 /** 1561 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1562 */ 1563 struct dmub_cmd_mst_alloc_slots_control_data { 1564 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1565 uint8_t instance; /* DPIA instance */ 1566 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1567 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1568 }; 1569 1570 /** 1571 * DMUB command structure for SET_ command. 1572 */ 1573 struct dmub_rb_cmd_set_mst_alloc_slots { 1574 struct dmub_cmd_header header; /* header */ 1575 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1576 }; 1577 1578 /** 1579 * DMUB command structure for DPIA HPD int enable control. 1580 */ 1581 struct dmub_rb_cmd_dpia_hpd_int_enable { 1582 struct dmub_cmd_header header; /* header */ 1583 uint32_t enable; /* dpia hpd interrupt enable */ 1584 }; 1585 1586 /** 1587 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1588 */ 1589 struct dmub_rb_cmd_dpphy_init { 1590 struct dmub_cmd_header header; /**< header */ 1591 uint8_t reserved[60]; /**< reserved bits */ 1592 }; 1593 1594 /** 1595 * enum dp_aux_request_action - DP AUX request command listing. 1596 * 1597 * 4 AUX request command bits are shifted to high nibble. 1598 */ 1599 enum dp_aux_request_action { 1600 /** I2C-over-AUX write request */ 1601 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1602 /** I2C-over-AUX read request */ 1603 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1604 /** I2C-over-AUX write status request */ 1605 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1606 /** I2C-over-AUX write request with MOT=1 */ 1607 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1608 /** I2C-over-AUX read request with MOT=1 */ 1609 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1610 /** I2C-over-AUX write status request with MOT=1 */ 1611 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1612 /** Native AUX write request */ 1613 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1614 /** Native AUX read request */ 1615 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1616 }; 1617 1618 /** 1619 * enum aux_return_code_type - DP AUX process return code listing. 1620 */ 1621 enum aux_return_code_type { 1622 /** AUX process succeeded */ 1623 AUX_RET_SUCCESS = 0, 1624 /** AUX process failed with unknown reason */ 1625 AUX_RET_ERROR_UNKNOWN, 1626 /** AUX process completed with invalid reply */ 1627 AUX_RET_ERROR_INVALID_REPLY, 1628 /** AUX process timed out */ 1629 AUX_RET_ERROR_TIMEOUT, 1630 /** HPD was low during AUX process */ 1631 AUX_RET_ERROR_HPD_DISCON, 1632 /** Failed to acquire AUX engine */ 1633 AUX_RET_ERROR_ENGINE_ACQUIRE, 1634 /** AUX request not supported */ 1635 AUX_RET_ERROR_INVALID_OPERATION, 1636 /** AUX process not available */ 1637 AUX_RET_ERROR_PROTOCOL_ERROR, 1638 }; 1639 1640 /** 1641 * enum aux_channel_type - DP AUX channel type listing. 1642 */ 1643 enum aux_channel_type { 1644 /** AUX thru Legacy DP AUX */ 1645 AUX_CHANNEL_LEGACY_DDC, 1646 /** AUX thru DPIA DP tunneling */ 1647 AUX_CHANNEL_DPIA 1648 }; 1649 1650 /** 1651 * struct aux_transaction_parameters - DP AUX request transaction data 1652 */ 1653 struct aux_transaction_parameters { 1654 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1655 uint8_t action; /**< enum dp_aux_request_action */ 1656 uint8_t length; /**< DP AUX request data length */ 1657 uint8_t reserved; /**< For future use */ 1658 uint32_t address; /**< DP AUX address */ 1659 uint8_t data[16]; /**< DP AUX write data */ 1660 }; 1661 1662 /** 1663 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1664 */ 1665 struct dmub_cmd_dp_aux_control_data { 1666 uint8_t instance; /**< AUX instance or DPIA instance */ 1667 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1668 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1669 uint8_t reserved0; /**< For future use */ 1670 uint16_t timeout; /**< timeout time in us */ 1671 uint16_t reserved1; /**< For future use */ 1672 enum aux_channel_type type; /**< enum aux_channel_type */ 1673 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1674 }; 1675 1676 /** 1677 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1678 */ 1679 struct dmub_rb_cmd_dp_aux_access { 1680 /** 1681 * Command header. 1682 */ 1683 struct dmub_cmd_header header; 1684 /** 1685 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1686 */ 1687 struct dmub_cmd_dp_aux_control_data aux_control; 1688 }; 1689 1690 /** 1691 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1692 */ 1693 struct dmub_rb_cmd_outbox1_enable { 1694 /** 1695 * Command header. 1696 */ 1697 struct dmub_cmd_header header; 1698 /** 1699 * enable: 0x0 -> disable outbox1 notification (default value) 1700 * 0x1 -> enable outbox1 notification 1701 */ 1702 uint32_t enable; 1703 }; 1704 1705 /* DP AUX Reply command - OutBox Cmd */ 1706 /** 1707 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1708 */ 1709 struct aux_reply_data { 1710 /** 1711 * Aux cmd 1712 */ 1713 uint8_t command; 1714 /** 1715 * Aux reply data length (max: 16 bytes) 1716 */ 1717 uint8_t length; 1718 /** 1719 * Alignment only 1720 */ 1721 uint8_t pad[2]; 1722 /** 1723 * Aux reply data 1724 */ 1725 uint8_t data[16]; 1726 }; 1727 1728 /** 1729 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1730 */ 1731 struct aux_reply_control_data { 1732 /** 1733 * Reserved for future use 1734 */ 1735 uint32_t handle; 1736 /** 1737 * Aux Instance 1738 */ 1739 uint8_t instance; 1740 /** 1741 * Aux transaction result: definition in enum aux_return_code_type 1742 */ 1743 uint8_t result; 1744 /** 1745 * Alignment only 1746 */ 1747 uint16_t pad; 1748 }; 1749 1750 /** 1751 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1752 */ 1753 struct dmub_rb_cmd_dp_aux_reply { 1754 /** 1755 * Command header. 1756 */ 1757 struct dmub_cmd_header header; 1758 /** 1759 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1760 */ 1761 struct aux_reply_control_data control; 1762 /** 1763 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1764 */ 1765 struct aux_reply_data reply_data; 1766 }; 1767 1768 /* DP HPD Notify command - OutBox Cmd */ 1769 /** 1770 * DP HPD Type 1771 */ 1772 enum dp_hpd_type { 1773 /** 1774 * Normal DP HPD 1775 */ 1776 DP_HPD = 0, 1777 /** 1778 * DP HPD short pulse 1779 */ 1780 DP_IRQ 1781 }; 1782 1783 /** 1784 * DP HPD Status 1785 */ 1786 enum dp_hpd_status { 1787 /** 1788 * DP_HPD status low 1789 */ 1790 DP_HPD_UNPLUG = 0, 1791 /** 1792 * DP_HPD status high 1793 */ 1794 DP_HPD_PLUG 1795 }; 1796 1797 /** 1798 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1799 */ 1800 struct dp_hpd_data { 1801 /** 1802 * DP HPD instance 1803 */ 1804 uint8_t instance; 1805 /** 1806 * HPD type 1807 */ 1808 uint8_t hpd_type; 1809 /** 1810 * HPD status: only for type: DP_HPD to indicate status 1811 */ 1812 uint8_t hpd_status; 1813 /** 1814 * Alignment only 1815 */ 1816 uint8_t pad; 1817 }; 1818 1819 /** 1820 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1821 */ 1822 struct dmub_rb_cmd_dp_hpd_notify { 1823 /** 1824 * Command header. 1825 */ 1826 struct dmub_cmd_header header; 1827 /** 1828 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1829 */ 1830 struct dp_hpd_data hpd_data; 1831 }; 1832 1833 /** 1834 * Definition of a SET_CONFIG reply from DPOA. 1835 */ 1836 enum set_config_status { 1837 SET_CONFIG_PENDING = 0, 1838 SET_CONFIG_ACK_RECEIVED, 1839 SET_CONFIG_RX_TIMEOUT, 1840 SET_CONFIG_UNKNOWN_ERROR, 1841 }; 1842 1843 /** 1844 * Definition of a set_config reply 1845 */ 1846 struct set_config_reply_control_data { 1847 uint8_t instance; /* DPIA Instance */ 1848 uint8_t status; /* Set Config reply */ 1849 uint16_t pad; /* Alignment */ 1850 }; 1851 1852 /** 1853 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1854 */ 1855 struct dmub_rb_cmd_dp_set_config_reply { 1856 struct dmub_cmd_header header; 1857 struct set_config_reply_control_data set_config_reply_control; 1858 }; 1859 1860 /** 1861 * Definition of a DPIA notification header 1862 */ 1863 struct dpia_notification_header { 1864 uint8_t instance; /**< DPIA Instance */ 1865 uint8_t reserved[3]; 1866 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1867 }; 1868 1869 /** 1870 * Definition of the common data struct of DPIA notification 1871 */ 1872 struct dpia_notification_common { 1873 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1874 - sizeof(struct dpia_notification_header)]; 1875 }; 1876 1877 /** 1878 * Definition of a DPIA notification data 1879 */ 1880 struct dpia_bw_allocation_notify_data { 1881 union { 1882 struct { 1883 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1884 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1885 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1886 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1887 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1888 uint16_t reserved: 11; /**< Reserved */ 1889 } bits; 1890 1891 uint16_t flags; 1892 }; 1893 1894 uint8_t cm_id; /**< CM ID */ 1895 uint8_t group_id; /**< Group ID */ 1896 uint8_t granularity; /**< BW Allocation Granularity */ 1897 uint8_t estimated_bw; /**< Estimated_BW */ 1898 uint8_t allocated_bw; /**< Allocated_BW */ 1899 uint8_t reserved; 1900 }; 1901 1902 /** 1903 * union dpia_notify_data_type - DPIA Notification in Outbox command 1904 */ 1905 union dpia_notification_data { 1906 /** 1907 * DPIA Notification for common data struct 1908 */ 1909 struct dpia_notification_common common_data; 1910 1911 /** 1912 * DPIA Notification for DP BW Allocation support 1913 */ 1914 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1915 }; 1916 1917 /** 1918 * Definition of a DPIA notification payload 1919 */ 1920 struct dpia_notification_payload { 1921 struct dpia_notification_header header; 1922 union dpia_notification_data data; /**< DPIA notification payload data */ 1923 }; 1924 1925 /** 1926 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1927 */ 1928 struct dmub_rb_cmd_dpia_notification { 1929 struct dmub_cmd_header header; /**< DPIA notification header */ 1930 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1931 }; 1932 1933 /** 1934 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1935 */ 1936 struct dmub_cmd_hpd_state_query_data { 1937 uint8_t instance; /**< HPD instance or DPIA instance */ 1938 uint8_t result; /**< For returning HPD state */ 1939 uint16_t pad; /** < Alignment */ 1940 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1941 enum aux_return_code_type status; /**< for returning the status of command */ 1942 }; 1943 1944 /** 1945 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1946 */ 1947 struct dmub_rb_cmd_query_hpd_state { 1948 /** 1949 * Command header. 1950 */ 1951 struct dmub_cmd_header header; 1952 /** 1953 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1954 */ 1955 struct dmub_cmd_hpd_state_query_data data; 1956 }; 1957 1958 /* 1959 * Command IDs should be treated as stable ABI. 1960 * Do not reuse or modify IDs. 1961 */ 1962 1963 /** 1964 * PSR command sub-types. 1965 */ 1966 enum dmub_cmd_psr_type { 1967 /** 1968 * Set PSR version support. 1969 */ 1970 DMUB_CMD__PSR_SET_VERSION = 0, 1971 /** 1972 * Copy driver-calculated parameters to PSR state. 1973 */ 1974 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1975 /** 1976 * Enable PSR. 1977 */ 1978 DMUB_CMD__PSR_ENABLE = 2, 1979 1980 /** 1981 * Disable PSR. 1982 */ 1983 DMUB_CMD__PSR_DISABLE = 3, 1984 1985 /** 1986 * Set PSR level. 1987 * PSR level is a 16-bit value dicated by driver that 1988 * will enable/disable different functionality. 1989 */ 1990 DMUB_CMD__PSR_SET_LEVEL = 4, 1991 1992 /** 1993 * Forces PSR enabled until an explicit PSR disable call. 1994 */ 1995 DMUB_CMD__PSR_FORCE_STATIC = 5, 1996 /** 1997 * Set vtotal in psr active for FreeSync PSR. 1998 */ 1999 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2000 /** 2001 * Set PSR power option 2002 */ 2003 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2004 }; 2005 2006 enum dmub_cmd_fams_type { 2007 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2008 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2009 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2010 /** 2011 * For SubVP set manual trigger in FW because it 2012 * triggers DRR_UPDATE_PENDING which SubVP relies 2013 * on (for any SubVP cases that use a DRR display) 2014 */ 2015 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2016 }; 2017 2018 /** 2019 * PSR versions. 2020 */ 2021 enum psr_version { 2022 /** 2023 * PSR version 1. 2024 */ 2025 PSR_VERSION_1 = 0, 2026 /** 2027 * Freesync PSR SU. 2028 */ 2029 PSR_VERSION_SU_1 = 1, 2030 /** 2031 * PSR not supported. 2032 */ 2033 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 2034 }; 2035 2036 /** 2037 * enum dmub_cmd_mall_type - MALL commands 2038 */ 2039 enum dmub_cmd_mall_type { 2040 /** 2041 * Allows display refresh from MALL. 2042 */ 2043 DMUB_CMD__MALL_ACTION_ALLOW = 0, 2044 /** 2045 * Disallows display refresh from MALL. 2046 */ 2047 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 2048 /** 2049 * Cursor copy for MALL. 2050 */ 2051 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 2052 /** 2053 * Controls DF requests. 2054 */ 2055 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 2056 }; 2057 2058 /** 2059 * PHY Link rate for DP. 2060 */ 2061 enum phy_link_rate { 2062 /** 2063 * not supported. 2064 */ 2065 PHY_RATE_UNKNOWN = 0, 2066 /** 2067 * Rate_1 (RBR) - 1.62 Gbps/Lane 2068 */ 2069 PHY_RATE_162 = 1, 2070 /** 2071 * Rate_2 - 2.16 Gbps/Lane 2072 */ 2073 PHY_RATE_216 = 2, 2074 /** 2075 * Rate_3 - 2.43 Gbps/Lane 2076 */ 2077 PHY_RATE_243 = 3, 2078 /** 2079 * Rate_4 (HBR) - 2.70 Gbps/Lane 2080 */ 2081 PHY_RATE_270 = 4, 2082 /** 2083 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2084 */ 2085 PHY_RATE_324 = 5, 2086 /** 2087 * Rate_6 - 4.32 Gbps/Lane 2088 */ 2089 PHY_RATE_432 = 6, 2090 /** 2091 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2092 */ 2093 PHY_RATE_540 = 7, 2094 /** 2095 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2096 */ 2097 PHY_RATE_810 = 8, 2098 /** 2099 * UHBR10 - 10.0 Gbps/Lane 2100 */ 2101 PHY_RATE_1000 = 9, 2102 /** 2103 * UHBR13.5 - 13.5 Gbps/Lane 2104 */ 2105 PHY_RATE_1350 = 10, 2106 /** 2107 * UHBR10 - 20.0 Gbps/Lane 2108 */ 2109 PHY_RATE_2000 = 11, 2110 }; 2111 2112 /** 2113 * enum dmub_phy_fsm_state - PHY FSM states. 2114 * PHY FSM state to transit to during PSR enable/disable. 2115 */ 2116 enum dmub_phy_fsm_state { 2117 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2118 DMUB_PHY_FSM_RESET, 2119 DMUB_PHY_FSM_RESET_RELEASED, 2120 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2121 DMUB_PHY_FSM_INITIALIZED, 2122 DMUB_PHY_FSM_CALIBRATED, 2123 DMUB_PHY_FSM_CALIBRATED_LP, 2124 DMUB_PHY_FSM_CALIBRATED_PG, 2125 DMUB_PHY_FSM_POWER_DOWN, 2126 DMUB_PHY_FSM_PLL_EN, 2127 DMUB_PHY_FSM_TX_EN, 2128 DMUB_PHY_FSM_FAST_LP, 2129 }; 2130 2131 /** 2132 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2133 */ 2134 struct dmub_cmd_psr_copy_settings_data { 2135 /** 2136 * Flags that can be set by driver to change some PSR behaviour. 2137 */ 2138 union dmub_psr_debug_flags debug; 2139 /** 2140 * 16-bit value dicated by driver that will enable/disable different functionality. 2141 */ 2142 uint16_t psr_level; 2143 /** 2144 * DPP HW instance. 2145 */ 2146 uint8_t dpp_inst; 2147 /** 2148 * MPCC HW instance. 2149 * Not used in dmub fw, 2150 * dmub fw will get active opp by reading odm registers. 2151 */ 2152 uint8_t mpcc_inst; 2153 /** 2154 * OPP HW instance. 2155 * Not used in dmub fw, 2156 * dmub fw will get active opp by reading odm registers. 2157 */ 2158 uint8_t opp_inst; 2159 /** 2160 * OTG HW instance. 2161 */ 2162 uint8_t otg_inst; 2163 /** 2164 * DIG FE HW instance. 2165 */ 2166 uint8_t digfe_inst; 2167 /** 2168 * DIG BE HW instance. 2169 */ 2170 uint8_t digbe_inst; 2171 /** 2172 * DP PHY HW instance. 2173 */ 2174 uint8_t dpphy_inst; 2175 /** 2176 * AUX HW instance. 2177 */ 2178 uint8_t aux_inst; 2179 /** 2180 * Determines if SMU optimzations are enabled/disabled. 2181 */ 2182 uint8_t smu_optimizations_en; 2183 /** 2184 * Unused. 2185 * TODO: Remove. 2186 */ 2187 uint8_t frame_delay; 2188 /** 2189 * If RFB setup time is greater than the total VBLANK time, 2190 * it is not possible for the sink to capture the video frame 2191 * in the same frame the SDP is sent. In this case, 2192 * the frame capture indication bit should be set and an extra 2193 * static frame should be transmitted to the sink. 2194 */ 2195 uint8_t frame_cap_ind; 2196 /** 2197 * Granularity of Y offset supported by sink. 2198 */ 2199 uint8_t su_y_granularity; 2200 /** 2201 * Indicates whether sink should start capturing 2202 * immediately following active scan line, 2203 * or starting with the 2nd active scan line. 2204 */ 2205 uint8_t line_capture_indication; 2206 /** 2207 * Multi-display optimizations are implemented on certain ASICs. 2208 */ 2209 uint8_t multi_disp_optimizations_en; 2210 /** 2211 * The last possible line SDP may be transmitted without violating 2212 * the RFB setup time or entering the active video frame. 2213 */ 2214 uint16_t init_sdp_deadline; 2215 /** 2216 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2217 */ 2218 uint8_t rate_control_caps ; 2219 /* 2220 * Force PSRSU always doing full frame update 2221 */ 2222 uint8_t force_ffu_mode; 2223 /** 2224 * Length of each horizontal line in us. 2225 */ 2226 uint32_t line_time_in_us; 2227 /** 2228 * FEC enable status in driver 2229 */ 2230 uint8_t fec_enable_status; 2231 /** 2232 * FEC re-enable delay when PSR exit. 2233 * unit is 100us, range form 0~255(0xFF). 2234 */ 2235 uint8_t fec_enable_delay_in100us; 2236 /** 2237 * PSR control version. 2238 */ 2239 uint8_t cmd_version; 2240 /** 2241 * Panel Instance. 2242 * Panel instance to identify which psr_state to use 2243 * Currently the support is only for 0 or 1 2244 */ 2245 uint8_t panel_inst; 2246 /* 2247 * DSC enable status in driver 2248 */ 2249 uint8_t dsc_enable_status; 2250 /* 2251 * Use FSM state for PSR power up/down 2252 */ 2253 uint8_t use_phy_fsm; 2254 /** 2255 * frame delay for frame re-lock 2256 */ 2257 uint8_t relock_delay_frame_cnt; 2258 /** 2259 * Explicit padding to 2 byte boundary. 2260 */ 2261 uint8_t pad3; 2262 /** 2263 * DSC Slice height. 2264 */ 2265 uint16_t dsc_slice_height; 2266 /** 2267 * Explicit padding to 4 byte boundary. 2268 */ 2269 uint16_t pad; 2270 }; 2271 2272 /** 2273 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2274 */ 2275 struct dmub_rb_cmd_psr_copy_settings { 2276 /** 2277 * Command header. 2278 */ 2279 struct dmub_cmd_header header; 2280 /** 2281 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2282 */ 2283 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2284 }; 2285 2286 /** 2287 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2288 */ 2289 struct dmub_cmd_psr_set_level_data { 2290 /** 2291 * 16-bit value dicated by driver that will enable/disable different functionality. 2292 */ 2293 uint16_t psr_level; 2294 /** 2295 * PSR control version. 2296 */ 2297 uint8_t cmd_version; 2298 /** 2299 * Panel Instance. 2300 * Panel instance to identify which psr_state to use 2301 * Currently the support is only for 0 or 1 2302 */ 2303 uint8_t panel_inst; 2304 }; 2305 2306 /** 2307 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2308 */ 2309 struct dmub_rb_cmd_psr_set_level { 2310 /** 2311 * Command header. 2312 */ 2313 struct dmub_cmd_header header; 2314 /** 2315 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2316 */ 2317 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2318 }; 2319 2320 struct dmub_rb_cmd_psr_enable_data { 2321 /** 2322 * PSR control version. 2323 */ 2324 uint8_t cmd_version; 2325 /** 2326 * Panel Instance. 2327 * Panel instance to identify which psr_state to use 2328 * Currently the support is only for 0 or 1 2329 */ 2330 uint8_t panel_inst; 2331 /** 2332 * Phy state to enter. 2333 * Values to use are defined in dmub_phy_fsm_state 2334 */ 2335 uint8_t phy_fsm_state; 2336 /** 2337 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2338 * Set this using enum phy_link_rate. 2339 * This does not support HDMI/DP2 for now. 2340 */ 2341 uint8_t phy_rate; 2342 }; 2343 2344 /** 2345 * Definition of a DMUB_CMD__PSR_ENABLE command. 2346 * PSR enable/disable is controlled using the sub_type. 2347 */ 2348 struct dmub_rb_cmd_psr_enable { 2349 /** 2350 * Command header. 2351 */ 2352 struct dmub_cmd_header header; 2353 2354 struct dmub_rb_cmd_psr_enable_data data; 2355 }; 2356 2357 /** 2358 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2359 */ 2360 struct dmub_cmd_psr_set_version_data { 2361 /** 2362 * PSR version that FW should implement. 2363 */ 2364 enum psr_version version; 2365 /** 2366 * PSR control version. 2367 */ 2368 uint8_t cmd_version; 2369 /** 2370 * Panel Instance. 2371 * Panel instance to identify which psr_state to use 2372 * Currently the support is only for 0 or 1 2373 */ 2374 uint8_t panel_inst; 2375 /** 2376 * Explicit padding to 4 byte boundary. 2377 */ 2378 uint8_t pad[2]; 2379 }; 2380 2381 /** 2382 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2383 */ 2384 struct dmub_rb_cmd_psr_set_version { 2385 /** 2386 * Command header. 2387 */ 2388 struct dmub_cmd_header header; 2389 /** 2390 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2391 */ 2392 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2393 }; 2394 2395 struct dmub_cmd_psr_force_static_data { 2396 /** 2397 * PSR control version. 2398 */ 2399 uint8_t cmd_version; 2400 /** 2401 * Panel Instance. 2402 * Panel instance to identify which psr_state to use 2403 * Currently the support is only for 0 or 1 2404 */ 2405 uint8_t panel_inst; 2406 /** 2407 * Explicit padding to 4 byte boundary. 2408 */ 2409 uint8_t pad[2]; 2410 }; 2411 2412 /** 2413 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2414 */ 2415 struct dmub_rb_cmd_psr_force_static { 2416 /** 2417 * Command header. 2418 */ 2419 struct dmub_cmd_header header; 2420 /** 2421 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2422 */ 2423 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2424 }; 2425 2426 /** 2427 * PSR SU debug flags. 2428 */ 2429 union dmub_psr_su_debug_flags { 2430 /** 2431 * PSR SU debug flags. 2432 */ 2433 struct { 2434 /** 2435 * Update dirty rect in SW only. 2436 */ 2437 uint8_t update_dirty_rect_only : 1; 2438 /** 2439 * Reset the cursor/plane state before processing the call. 2440 */ 2441 uint8_t reset_state : 1; 2442 } bitfields; 2443 2444 /** 2445 * Union for debug flags. 2446 */ 2447 uint32_t u32All; 2448 }; 2449 2450 /** 2451 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2452 * This triggers a selective update for PSR SU. 2453 */ 2454 struct dmub_cmd_update_dirty_rect_data { 2455 /** 2456 * Dirty rects from OS. 2457 */ 2458 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2459 /** 2460 * PSR SU debug flags. 2461 */ 2462 union dmub_psr_su_debug_flags debug_flags; 2463 /** 2464 * OTG HW instance. 2465 */ 2466 uint8_t pipe_idx; 2467 /** 2468 * Number of dirty rects. 2469 */ 2470 uint8_t dirty_rect_count; 2471 /** 2472 * PSR control version. 2473 */ 2474 uint8_t cmd_version; 2475 /** 2476 * Panel Instance. 2477 * Panel instance to identify which psr_state to use 2478 * Currently the support is only for 0 or 1 2479 */ 2480 uint8_t panel_inst; 2481 }; 2482 2483 /** 2484 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2485 */ 2486 struct dmub_rb_cmd_update_dirty_rect { 2487 /** 2488 * Command header. 2489 */ 2490 struct dmub_cmd_header header; 2491 /** 2492 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2493 */ 2494 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2495 }; 2496 2497 /** 2498 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2499 */ 2500 union dmub_reg_cursor_control_cfg { 2501 struct { 2502 uint32_t cur_enable: 1; 2503 uint32_t reser0: 3; 2504 uint32_t cur_2x_magnify: 1; 2505 uint32_t reser1: 3; 2506 uint32_t mode: 3; 2507 uint32_t reser2: 5; 2508 uint32_t pitch: 2; 2509 uint32_t reser3: 6; 2510 uint32_t line_per_chunk: 5; 2511 uint32_t reser4: 3; 2512 } bits; 2513 uint32_t raw; 2514 }; 2515 struct dmub_cursor_position_cache_hubp { 2516 union dmub_reg_cursor_control_cfg cur_ctl; 2517 union dmub_reg_position_cfg { 2518 struct { 2519 uint32_t cur_x_pos: 16; 2520 uint32_t cur_y_pos: 16; 2521 } bits; 2522 uint32_t raw; 2523 } position; 2524 union dmub_reg_hot_spot_cfg { 2525 struct { 2526 uint32_t hot_x: 16; 2527 uint32_t hot_y: 16; 2528 } bits; 2529 uint32_t raw; 2530 } hot_spot; 2531 union dmub_reg_dst_offset_cfg { 2532 struct { 2533 uint32_t dst_x_offset: 13; 2534 uint32_t reserved: 19; 2535 } bits; 2536 uint32_t raw; 2537 } dst_offset; 2538 }; 2539 2540 union dmub_reg_cur0_control_cfg { 2541 struct { 2542 uint32_t cur0_enable: 1; 2543 uint32_t expansion_mode: 1; 2544 uint32_t reser0: 1; 2545 uint32_t cur0_rom_en: 1; 2546 uint32_t mode: 3; 2547 uint32_t reserved: 25; 2548 } bits; 2549 uint32_t raw; 2550 }; 2551 struct dmub_cursor_position_cache_dpp { 2552 union dmub_reg_cur0_control_cfg cur0_ctl; 2553 }; 2554 struct dmub_cursor_position_cfg { 2555 struct dmub_cursor_position_cache_hubp pHubp; 2556 struct dmub_cursor_position_cache_dpp pDpp; 2557 uint8_t pipe_idx; 2558 /* 2559 * Padding is required. To be 4 Bytes Aligned. 2560 */ 2561 uint8_t padding[3]; 2562 }; 2563 2564 struct dmub_cursor_attribute_cache_hubp { 2565 uint32_t SURFACE_ADDR_HIGH; 2566 uint32_t SURFACE_ADDR; 2567 union dmub_reg_cursor_control_cfg cur_ctl; 2568 union dmub_reg_cursor_size_cfg { 2569 struct { 2570 uint32_t width: 16; 2571 uint32_t height: 16; 2572 } bits; 2573 uint32_t raw; 2574 } size; 2575 union dmub_reg_cursor_settings_cfg { 2576 struct { 2577 uint32_t dst_y_offset: 8; 2578 uint32_t chunk_hdl_adjust: 2; 2579 uint32_t reserved: 22; 2580 } bits; 2581 uint32_t raw; 2582 } settings; 2583 }; 2584 struct dmub_cursor_attribute_cache_dpp { 2585 union dmub_reg_cur0_control_cfg cur0_ctl; 2586 }; 2587 struct dmub_cursor_attributes_cfg { 2588 struct dmub_cursor_attribute_cache_hubp aHubp; 2589 struct dmub_cursor_attribute_cache_dpp aDpp; 2590 }; 2591 2592 struct dmub_cmd_update_cursor_payload0 { 2593 /** 2594 * Cursor dirty rects. 2595 */ 2596 struct dmub_rect cursor_rect; 2597 /** 2598 * PSR SU debug flags. 2599 */ 2600 union dmub_psr_su_debug_flags debug_flags; 2601 /** 2602 * Cursor enable/disable. 2603 */ 2604 uint8_t enable; 2605 /** 2606 * OTG HW instance. 2607 */ 2608 uint8_t pipe_idx; 2609 /** 2610 * PSR control version. 2611 */ 2612 uint8_t cmd_version; 2613 /** 2614 * Panel Instance. 2615 * Panel instance to identify which psr_state to use 2616 * Currently the support is only for 0 or 1 2617 */ 2618 uint8_t panel_inst; 2619 /** 2620 * Cursor Position Register. 2621 * Registers contains Hubp & Dpp modules 2622 */ 2623 struct dmub_cursor_position_cfg position_cfg; 2624 }; 2625 2626 struct dmub_cmd_update_cursor_payload1 { 2627 struct dmub_cursor_attributes_cfg attribute_cfg; 2628 }; 2629 2630 union dmub_cmd_update_cursor_info_data { 2631 struct dmub_cmd_update_cursor_payload0 payload0; 2632 struct dmub_cmd_update_cursor_payload1 payload1; 2633 }; 2634 /** 2635 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2636 */ 2637 struct dmub_rb_cmd_update_cursor_info { 2638 /** 2639 * Command header. 2640 */ 2641 struct dmub_cmd_header header; 2642 /** 2643 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2644 */ 2645 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2646 }; 2647 2648 /** 2649 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2650 */ 2651 struct dmub_cmd_psr_set_vtotal_data { 2652 /** 2653 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2654 */ 2655 uint16_t psr_vtotal_idle; 2656 /** 2657 * PSR control version. 2658 */ 2659 uint8_t cmd_version; 2660 /** 2661 * Panel Instance. 2662 * Panel instance to identify which psr_state to use 2663 * Currently the support is only for 0 or 1 2664 */ 2665 uint8_t panel_inst; 2666 /* 2667 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2668 */ 2669 uint16_t psr_vtotal_su; 2670 /** 2671 * Explicit padding to 4 byte boundary. 2672 */ 2673 uint8_t pad2[2]; 2674 }; 2675 2676 /** 2677 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2678 */ 2679 struct dmub_rb_cmd_psr_set_vtotal { 2680 /** 2681 * Command header. 2682 */ 2683 struct dmub_cmd_header header; 2684 /** 2685 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2686 */ 2687 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2688 }; 2689 2690 /** 2691 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2692 */ 2693 struct dmub_cmd_psr_set_power_opt_data { 2694 /** 2695 * PSR control version. 2696 */ 2697 uint8_t cmd_version; 2698 /** 2699 * Panel Instance. 2700 * Panel instance to identify which psr_state to use 2701 * Currently the support is only for 0 or 1 2702 */ 2703 uint8_t panel_inst; 2704 /** 2705 * Explicit padding to 4 byte boundary. 2706 */ 2707 uint8_t pad[2]; 2708 /** 2709 * PSR power option 2710 */ 2711 uint32_t power_opt; 2712 }; 2713 2714 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 2715 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 2716 2717 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2718 # define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 2719 # define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2720 2721 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2722 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2723 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2724 2725 enum replay_state { 2726 REPLAY_STATE_0 = 0x0, 2727 REPLAY_STATE_1 = 0x10, 2728 REPLAY_STATE_1A = 0x11, 2729 REPLAY_STATE_2 = 0x20, 2730 REPLAY_STATE_3 = 0x30, 2731 REPLAY_STATE_3INIT = 0x31, 2732 REPLAY_STATE_4 = 0x40, 2733 REPLAY_STATE_4A = 0x41, 2734 REPLAY_STATE_4B = 0x42, 2735 REPLAY_STATE_4C = 0x43, 2736 REPLAY_STATE_4D = 0x44, 2737 REPLAY_STATE_4B_LOCKED = 0x4A, 2738 REPLAY_STATE_4C_UNLOCKED = 0x4B, 2739 REPLAY_STATE_5 = 0x50, 2740 REPLAY_STATE_5A = 0x51, 2741 REPLAY_STATE_5B = 0x52, 2742 REPLAY_STATE_5A_LOCKED = 0x5A, 2743 REPLAY_STATE_5B_UNLOCKED = 0x5B, 2744 REPLAY_STATE_6 = 0x60, 2745 REPLAY_STATE_6A = 0x61, 2746 REPLAY_STATE_6B = 0x62, 2747 REPLAY_STATE_INVALID = 0xFF, 2748 }; 2749 2750 /** 2751 * Replay command sub-types. 2752 */ 2753 enum dmub_cmd_replay_type { 2754 /** 2755 * Copy driver-calculated parameters to REPLAY state. 2756 */ 2757 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 2758 /** 2759 * Enable REPLAY. 2760 */ 2761 DMUB_CMD__REPLAY_ENABLE = 1, 2762 /** 2763 * Set Replay power option. 2764 */ 2765 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 2766 /** 2767 * Set coasting vtotal. 2768 */ 2769 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 2770 }; 2771 2772 /** 2773 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2774 */ 2775 struct dmub_cmd_replay_copy_settings_data { 2776 /** 2777 * Flags that can be set by driver to change some replay behaviour. 2778 */ 2779 union replay_debug_flags debug; 2780 2781 /** 2782 * @flags: Flags used to determine feature functionality. 2783 */ 2784 union replay_hw_flags flags; 2785 2786 /** 2787 * DPP HW instance. 2788 */ 2789 uint8_t dpp_inst; 2790 /** 2791 * OTG HW instance. 2792 */ 2793 uint8_t otg_inst; 2794 /** 2795 * DIG FE HW instance. 2796 */ 2797 uint8_t digfe_inst; 2798 /** 2799 * DIG BE HW instance. 2800 */ 2801 uint8_t digbe_inst; 2802 /** 2803 * AUX HW instance. 2804 */ 2805 uint8_t aux_inst; 2806 /** 2807 * Panel Instance. 2808 * Panel isntance to identify which psr_state to use 2809 * Currently the support is only for 0 or 1 2810 */ 2811 uint8_t panel_inst; 2812 /** 2813 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 2814 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 2815 */ 2816 uint8_t pixel_deviation_per_line; 2817 /** 2818 * @max_deviation_line: The max number of deviation line that can keep the timing 2819 * synchronized between the Source and Sink during Replay normal sleep mode. 2820 */ 2821 uint8_t max_deviation_line; 2822 /** 2823 * Length of each horizontal line in ns. 2824 */ 2825 uint32_t line_time_in_ns; 2826 /** 2827 * PHY instance. 2828 */ 2829 uint8_t dpphy_inst; 2830 /** 2831 * Determines if SMU optimzations are enabled/disabled. 2832 */ 2833 uint8_t smu_optimizations_en; 2834 /** 2835 * Determines if timing sync are enabled/disabled. 2836 */ 2837 uint8_t replay_timing_sync_supported; 2838 /* 2839 * Use FSM state for Replay power up/down 2840 */ 2841 uint8_t use_phy_fsm; 2842 }; 2843 2844 /** 2845 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2846 */ 2847 struct dmub_rb_cmd_replay_copy_settings { 2848 /** 2849 * Command header. 2850 */ 2851 struct dmub_cmd_header header; 2852 /** 2853 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 2854 */ 2855 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 2856 }; 2857 2858 /** 2859 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 2860 */ 2861 enum replay_enable { 2862 /** 2863 * Disable REPLAY. 2864 */ 2865 REPLAY_DISABLE = 0, 2866 /** 2867 * Enable REPLAY. 2868 */ 2869 REPLAY_ENABLE = 1, 2870 }; 2871 2872 /** 2873 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 2874 */ 2875 struct dmub_rb_cmd_replay_enable_data { 2876 /** 2877 * Replay enable or disable. 2878 */ 2879 uint8_t enable; 2880 /** 2881 * Panel Instance. 2882 * Panel isntance to identify which replay_state to use 2883 * Currently the support is only for 0 or 1 2884 */ 2885 uint8_t panel_inst; 2886 /** 2887 * Phy state to enter. 2888 * Values to use are defined in dmub_phy_fsm_state 2889 */ 2890 uint8_t phy_fsm_state; 2891 /** 2892 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2893 * Set this using enum phy_link_rate. 2894 * This does not support HDMI/DP2 for now. 2895 */ 2896 uint8_t phy_rate; 2897 }; 2898 2899 /** 2900 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 2901 * Replay enable/disable is controlled using action in data. 2902 */ 2903 struct dmub_rb_cmd_replay_enable { 2904 /** 2905 * Command header. 2906 */ 2907 struct dmub_cmd_header header; 2908 2909 struct dmub_rb_cmd_replay_enable_data data; 2910 }; 2911 2912 /** 2913 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 2914 */ 2915 struct dmub_cmd_replay_set_power_opt_data { 2916 /** 2917 * Panel Instance. 2918 * Panel isntance to identify which replay_state to use 2919 * Currently the support is only for 0 or 1 2920 */ 2921 uint8_t panel_inst; 2922 /** 2923 * Explicit padding to 4 byte boundary. 2924 */ 2925 uint8_t pad[3]; 2926 /** 2927 * REPLAY power option 2928 */ 2929 uint32_t power_opt; 2930 }; 2931 2932 /** 2933 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 2934 */ 2935 struct dmub_rb_cmd_replay_set_power_opt { 2936 /** 2937 * Command header. 2938 */ 2939 struct dmub_cmd_header header; 2940 /** 2941 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 2942 */ 2943 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 2944 }; 2945 2946 /** 2947 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 2948 */ 2949 struct dmub_cmd_replay_set_coasting_vtotal_data { 2950 /** 2951 * 16-bit value dicated by driver that indicates the coasting vtotal. 2952 */ 2953 uint16_t coasting_vtotal; 2954 /** 2955 * REPLAY control version. 2956 */ 2957 uint8_t cmd_version; 2958 /** 2959 * Panel Instance. 2960 * Panel isntance to identify which replay_state to use 2961 * Currently the support is only for 0 or 1 2962 */ 2963 uint8_t panel_inst; 2964 }; 2965 2966 /** 2967 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 2968 */ 2969 struct dmub_rb_cmd_replay_set_coasting_vtotal { 2970 /** 2971 * Command header. 2972 */ 2973 struct dmub_cmd_header header; 2974 /** 2975 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 2976 */ 2977 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 2978 }; 2979 2980 /** 2981 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2982 */ 2983 struct dmub_rb_cmd_psr_set_power_opt { 2984 /** 2985 * Command header. 2986 */ 2987 struct dmub_cmd_header header; 2988 /** 2989 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2990 */ 2991 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2992 }; 2993 2994 /** 2995 * Set of HW components that can be locked. 2996 * 2997 * Note: If updating with more HW components, fields 2998 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2999 */ 3000 union dmub_hw_lock_flags { 3001 /** 3002 * Set of HW components that can be locked. 3003 */ 3004 struct { 3005 /** 3006 * Lock/unlock OTG master update lock. 3007 */ 3008 uint8_t lock_pipe : 1; 3009 /** 3010 * Lock/unlock cursor. 3011 */ 3012 uint8_t lock_cursor : 1; 3013 /** 3014 * Lock/unlock global update lock. 3015 */ 3016 uint8_t lock_dig : 1; 3017 /** 3018 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3019 */ 3020 uint8_t triple_buffer_lock : 1; 3021 } bits; 3022 3023 /** 3024 * Union for HW Lock flags. 3025 */ 3026 uint8_t u8All; 3027 }; 3028 3029 /** 3030 * Instances of HW to be locked. 3031 * 3032 * Note: If updating with more HW components, fields 3033 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3034 */ 3035 struct dmub_hw_lock_inst_flags { 3036 /** 3037 * OTG HW instance for OTG master update lock. 3038 */ 3039 uint8_t otg_inst; 3040 /** 3041 * OPP instance for cursor lock. 3042 */ 3043 uint8_t opp_inst; 3044 /** 3045 * OTG HW instance for global update lock. 3046 * TODO: Remove, and re-use otg_inst. 3047 */ 3048 uint8_t dig_inst; 3049 /** 3050 * Explicit pad to 4 byte boundary. 3051 */ 3052 uint8_t pad; 3053 }; 3054 3055 /** 3056 * Clients that can acquire the HW Lock Manager. 3057 * 3058 * Note: If updating with more clients, fields in 3059 * dmub_inbox0_cmd_lock_hw must be updated to match. 3060 */ 3061 enum hw_lock_client { 3062 /** 3063 * Driver is the client of HW Lock Manager. 3064 */ 3065 HW_LOCK_CLIENT_DRIVER = 0, 3066 /** 3067 * PSR SU is the client of HW Lock Manager. 3068 */ 3069 HW_LOCK_CLIENT_PSR_SU = 1, 3070 /** 3071 * Replay is the client of HW Lock Manager. 3072 */ 3073 HW_LOCK_CLIENT_REPLAY = 4, 3074 /** 3075 * Invalid client. 3076 */ 3077 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3078 }; 3079 3080 /** 3081 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3082 */ 3083 struct dmub_cmd_lock_hw_data { 3084 /** 3085 * Specifies the client accessing HW Lock Manager. 3086 */ 3087 enum hw_lock_client client; 3088 /** 3089 * HW instances to be locked. 3090 */ 3091 struct dmub_hw_lock_inst_flags inst_flags; 3092 /** 3093 * Which components to be locked. 3094 */ 3095 union dmub_hw_lock_flags hw_locks; 3096 /** 3097 * Specifies lock/unlock. 3098 */ 3099 uint8_t lock; 3100 /** 3101 * HW can be unlocked separately from releasing the HW Lock Mgr. 3102 * This flag is set if the client wishes to release the object. 3103 */ 3104 uint8_t should_release; 3105 /** 3106 * Explicit padding to 4 byte boundary. 3107 */ 3108 uint8_t pad; 3109 }; 3110 3111 /** 3112 * Definition of a DMUB_CMD__HW_LOCK command. 3113 * Command is used by driver and FW. 3114 */ 3115 struct dmub_rb_cmd_lock_hw { 3116 /** 3117 * Command header. 3118 */ 3119 struct dmub_cmd_header header; 3120 /** 3121 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3122 */ 3123 struct dmub_cmd_lock_hw_data lock_hw_data; 3124 }; 3125 3126 /** 3127 * ABM command sub-types. 3128 */ 3129 enum dmub_cmd_abm_type { 3130 /** 3131 * Initialize parameters for ABM algorithm. 3132 * Data is passed through an indirect buffer. 3133 */ 3134 DMUB_CMD__ABM_INIT_CONFIG = 0, 3135 /** 3136 * Set OTG and panel HW instance. 3137 */ 3138 DMUB_CMD__ABM_SET_PIPE = 1, 3139 /** 3140 * Set user requested backklight level. 3141 */ 3142 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3143 /** 3144 * Set ABM operating/aggression level. 3145 */ 3146 DMUB_CMD__ABM_SET_LEVEL = 3, 3147 /** 3148 * Set ambient light level. 3149 */ 3150 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3151 /** 3152 * Enable/disable fractional duty cycle for backlight PWM. 3153 */ 3154 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 3155 3156 /** 3157 * unregister vertical interrupt after steady state is reached 3158 */ 3159 DMUB_CMD__ABM_PAUSE = 6, 3160 3161 /** 3162 * Save and Restore ABM state. On save we save parameters, and 3163 * on restore we update state with passed in data. 3164 */ 3165 DMUB_CMD__ABM_SAVE_RESTORE = 7, 3166 }; 3167 3168 /** 3169 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 3170 * Requirements: 3171 * - Padded explicitly to 32-bit boundary. 3172 * - Must ensure this structure matches the one on driver-side, 3173 * otherwise it won't be aligned. 3174 */ 3175 struct abm_config_table { 3176 /** 3177 * Gamma curve thresholds, used for crgb conversion. 3178 */ 3179 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 3180 /** 3181 * Gamma curve offsets, used for crgb conversion. 3182 */ 3183 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 3184 /** 3185 * Gamma curve slopes, used for crgb conversion. 3186 */ 3187 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 3188 /** 3189 * Custom backlight curve thresholds. 3190 */ 3191 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 3192 /** 3193 * Custom backlight curve offsets. 3194 */ 3195 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 3196 /** 3197 * Ambient light thresholds. 3198 */ 3199 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 3200 /** 3201 * Minimum programmable backlight. 3202 */ 3203 uint16_t min_abm_backlight; // 122B 3204 /** 3205 * Minimum reduction values. 3206 */ 3207 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 3208 /** 3209 * Maximum reduction values. 3210 */ 3211 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 3212 /** 3213 * Bright positive gain. 3214 */ 3215 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 3216 /** 3217 * Dark negative gain. 3218 */ 3219 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 3220 /** 3221 * Hybrid factor. 3222 */ 3223 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 3224 /** 3225 * Contrast factor. 3226 */ 3227 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 3228 /** 3229 * Deviation gain. 3230 */ 3231 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 3232 /** 3233 * Minimum knee. 3234 */ 3235 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 3236 /** 3237 * Maximum knee. 3238 */ 3239 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 3240 /** 3241 * Unused. 3242 */ 3243 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 3244 /** 3245 * Explicit padding to 4 byte boundary. 3246 */ 3247 uint8_t pad3[3]; // 229B 3248 /** 3249 * Backlight ramp reduction. 3250 */ 3251 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 3252 /** 3253 * Backlight ramp start. 3254 */ 3255 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 3256 }; 3257 3258 /** 3259 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3260 */ 3261 struct dmub_cmd_abm_set_pipe_data { 3262 /** 3263 * OTG HW instance. 3264 */ 3265 uint8_t otg_inst; 3266 3267 /** 3268 * Panel Control HW instance. 3269 */ 3270 uint8_t panel_inst; 3271 3272 /** 3273 * Controls how ABM will interpret a set pipe or set level command. 3274 */ 3275 uint8_t set_pipe_option; 3276 3277 /** 3278 * Unused. 3279 * TODO: Remove. 3280 */ 3281 uint8_t ramping_boundary; 3282 }; 3283 3284 /** 3285 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3286 */ 3287 struct dmub_rb_cmd_abm_set_pipe { 3288 /** 3289 * Command header. 3290 */ 3291 struct dmub_cmd_header header; 3292 3293 /** 3294 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3295 */ 3296 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 3297 }; 3298 3299 /** 3300 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3301 */ 3302 struct dmub_cmd_abm_set_backlight_data { 3303 /** 3304 * Number of frames to ramp to backlight user level. 3305 */ 3306 uint32_t frame_ramp; 3307 3308 /** 3309 * Requested backlight level from user. 3310 */ 3311 uint32_t backlight_user_level; 3312 3313 /** 3314 * ABM control version. 3315 */ 3316 uint8_t version; 3317 3318 /** 3319 * Panel Control HW instance mask. 3320 * Bit 0 is Panel Control HW instance 0. 3321 * Bit 1 is Panel Control HW instance 1. 3322 */ 3323 uint8_t panel_mask; 3324 3325 /** 3326 * Explicit padding to 4 byte boundary. 3327 */ 3328 uint8_t pad[2]; 3329 }; 3330 3331 /** 3332 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3333 */ 3334 struct dmub_rb_cmd_abm_set_backlight { 3335 /** 3336 * Command header. 3337 */ 3338 struct dmub_cmd_header header; 3339 3340 /** 3341 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3342 */ 3343 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 3344 }; 3345 3346 /** 3347 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3348 */ 3349 struct dmub_cmd_abm_set_level_data { 3350 /** 3351 * Set current ABM operating/aggression level. 3352 */ 3353 uint32_t level; 3354 3355 /** 3356 * ABM control version. 3357 */ 3358 uint8_t version; 3359 3360 /** 3361 * Panel Control HW instance mask. 3362 * Bit 0 is Panel Control HW instance 0. 3363 * Bit 1 is Panel Control HW instance 1. 3364 */ 3365 uint8_t panel_mask; 3366 3367 /** 3368 * Explicit padding to 4 byte boundary. 3369 */ 3370 uint8_t pad[2]; 3371 }; 3372 3373 /** 3374 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3375 */ 3376 struct dmub_rb_cmd_abm_set_level { 3377 /** 3378 * Command header. 3379 */ 3380 struct dmub_cmd_header header; 3381 3382 /** 3383 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3384 */ 3385 struct dmub_cmd_abm_set_level_data abm_set_level_data; 3386 }; 3387 3388 /** 3389 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3390 */ 3391 struct dmub_cmd_abm_set_ambient_level_data { 3392 /** 3393 * Ambient light sensor reading from OS. 3394 */ 3395 uint32_t ambient_lux; 3396 3397 /** 3398 * ABM control version. 3399 */ 3400 uint8_t version; 3401 3402 /** 3403 * Panel Control HW instance mask. 3404 * Bit 0 is Panel Control HW instance 0. 3405 * Bit 1 is Panel Control HW instance 1. 3406 */ 3407 uint8_t panel_mask; 3408 3409 /** 3410 * Explicit padding to 4 byte boundary. 3411 */ 3412 uint8_t pad[2]; 3413 }; 3414 3415 /** 3416 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3417 */ 3418 struct dmub_rb_cmd_abm_set_ambient_level { 3419 /** 3420 * Command header. 3421 */ 3422 struct dmub_cmd_header header; 3423 3424 /** 3425 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3426 */ 3427 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 3428 }; 3429 3430 /** 3431 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3432 */ 3433 struct dmub_cmd_abm_set_pwm_frac_data { 3434 /** 3435 * Enable/disable fractional duty cycle for backlight PWM. 3436 * TODO: Convert to uint8_t. 3437 */ 3438 uint32_t fractional_pwm; 3439 3440 /** 3441 * ABM control version. 3442 */ 3443 uint8_t version; 3444 3445 /** 3446 * Panel Control HW instance mask. 3447 * Bit 0 is Panel Control HW instance 0. 3448 * Bit 1 is Panel Control HW instance 1. 3449 */ 3450 uint8_t panel_mask; 3451 3452 /** 3453 * Explicit padding to 4 byte boundary. 3454 */ 3455 uint8_t pad[2]; 3456 }; 3457 3458 /** 3459 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3460 */ 3461 struct dmub_rb_cmd_abm_set_pwm_frac { 3462 /** 3463 * Command header. 3464 */ 3465 struct dmub_cmd_header header; 3466 3467 /** 3468 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3469 */ 3470 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 3471 }; 3472 3473 /** 3474 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3475 */ 3476 struct dmub_cmd_abm_init_config_data { 3477 /** 3478 * Location of indirect buffer used to pass init data to ABM. 3479 */ 3480 union dmub_addr src; 3481 3482 /** 3483 * Indirect buffer length. 3484 */ 3485 uint16_t bytes; 3486 3487 3488 /** 3489 * ABM control version. 3490 */ 3491 uint8_t version; 3492 3493 /** 3494 * Panel Control HW instance mask. 3495 * Bit 0 is Panel Control HW instance 0. 3496 * Bit 1 is Panel Control HW instance 1. 3497 */ 3498 uint8_t panel_mask; 3499 3500 /** 3501 * Explicit padding to 4 byte boundary. 3502 */ 3503 uint8_t pad[2]; 3504 }; 3505 3506 /** 3507 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3508 */ 3509 struct dmub_rb_cmd_abm_init_config { 3510 /** 3511 * Command header. 3512 */ 3513 struct dmub_cmd_header header; 3514 3515 /** 3516 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3517 */ 3518 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3519 }; 3520 3521 /** 3522 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3523 */ 3524 3525 struct dmub_cmd_abm_pause_data { 3526 3527 /** 3528 * Panel Control HW instance mask. 3529 * Bit 0 is Panel Control HW instance 0. 3530 * Bit 1 is Panel Control HW instance 1. 3531 */ 3532 uint8_t panel_mask; 3533 3534 /** 3535 * OTG hw instance 3536 */ 3537 uint8_t otg_inst; 3538 3539 /** 3540 * Enable or disable ABM pause 3541 */ 3542 uint8_t enable; 3543 3544 /** 3545 * Explicit padding to 4 byte boundary. 3546 */ 3547 uint8_t pad[1]; 3548 }; 3549 3550 3551 /** 3552 * Definition of a DMUB_CMD__ABM_PAUSE command. 3553 */ 3554 struct dmub_rb_cmd_abm_pause { 3555 /** 3556 * Command header. 3557 */ 3558 struct dmub_cmd_header header; 3559 3560 /** 3561 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3562 */ 3563 struct dmub_cmd_abm_pause_data abm_pause_data; 3564 }; 3565 3566 /** 3567 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3568 */ 3569 struct dmub_rb_cmd_abm_save_restore { 3570 /** 3571 * Command header. 3572 */ 3573 struct dmub_cmd_header header; 3574 3575 /** 3576 * OTG hw instance 3577 */ 3578 uint8_t otg_inst; 3579 3580 /** 3581 * Enable or disable ABM pause 3582 */ 3583 uint8_t freeze; 3584 3585 /** 3586 * Explicit padding to 4 byte boundary. 3587 */ 3588 uint8_t debug; 3589 3590 /** 3591 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3592 */ 3593 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3594 }; 3595 3596 /** 3597 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3598 */ 3599 struct dmub_cmd_query_feature_caps_data { 3600 /** 3601 * DMUB feature capabilities. 3602 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3603 */ 3604 struct dmub_feature_caps feature_caps; 3605 }; 3606 3607 /** 3608 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3609 */ 3610 struct dmub_rb_cmd_query_feature_caps { 3611 /** 3612 * Command header. 3613 */ 3614 struct dmub_cmd_header header; 3615 /** 3616 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3617 */ 3618 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3619 }; 3620 3621 /** 3622 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3623 */ 3624 struct dmub_cmd_visual_confirm_color_data { 3625 /** 3626 * DMUB feature capabilities. 3627 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3628 */ 3629 struct dmub_visual_confirm_color visual_confirm_color; 3630 }; 3631 3632 /** 3633 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3634 */ 3635 struct dmub_rb_cmd_get_visual_confirm_color { 3636 /** 3637 * Command header. 3638 */ 3639 struct dmub_cmd_header header; 3640 /** 3641 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3642 */ 3643 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3644 }; 3645 3646 struct dmub_optc_state { 3647 uint32_t v_total_max; 3648 uint32_t v_total_min; 3649 uint32_t tg_inst; 3650 }; 3651 3652 struct dmub_rb_cmd_drr_update { 3653 struct dmub_cmd_header header; 3654 struct dmub_optc_state dmub_optc_state_req; 3655 }; 3656 3657 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3658 uint32_t pix_clk_100hz; 3659 uint8_t max_ramp_step; 3660 uint8_t pipes; 3661 uint8_t min_refresh_in_hz; 3662 uint8_t pipe_count; 3663 uint8_t pipe_index[4]; 3664 }; 3665 3666 struct dmub_cmd_fw_assisted_mclk_switch_config { 3667 uint8_t fams_enabled; 3668 uint8_t visual_confirm_enabled; 3669 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3670 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3671 }; 3672 3673 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3674 struct dmub_cmd_header header; 3675 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3676 }; 3677 3678 /** 3679 * enum dmub_cmd_panel_cntl_type - Panel control command. 3680 */ 3681 enum dmub_cmd_panel_cntl_type { 3682 /** 3683 * Initializes embedded panel hardware blocks. 3684 */ 3685 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3686 /** 3687 * Queries backlight info for the embedded panel. 3688 */ 3689 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3690 }; 3691 3692 /** 3693 * struct dmub_cmd_panel_cntl_data - Panel control data. 3694 */ 3695 struct dmub_cmd_panel_cntl_data { 3696 uint32_t inst; /**< panel instance */ 3697 uint32_t current_backlight; /* in/out */ 3698 uint32_t bl_pwm_cntl; /* in/out */ 3699 uint32_t bl_pwm_period_cntl; /* in/out */ 3700 uint32_t bl_pwm_ref_div1; /* in/out */ 3701 uint8_t is_backlight_on : 1; /* in/out */ 3702 uint8_t is_powered_on : 1; /* in/out */ 3703 uint8_t padding[3]; 3704 uint32_t bl_pwm_ref_div2; /* in/out */ 3705 uint8_t reserved[4]; 3706 }; 3707 3708 /** 3709 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3710 */ 3711 struct dmub_rb_cmd_panel_cntl { 3712 struct dmub_cmd_header header; /**< header */ 3713 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3714 }; 3715 3716 /** 3717 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3718 */ 3719 struct dmub_cmd_lvtma_control_data { 3720 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3721 uint8_t bypass_panel_control_wait; 3722 uint8_t reserved_0[2]; /**< For future use */ 3723 uint8_t panel_inst; /**< LVTMA control instance */ 3724 uint8_t reserved_1[3]; /**< For future use */ 3725 }; 3726 3727 /** 3728 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3729 */ 3730 struct dmub_rb_cmd_lvtma_control { 3731 /** 3732 * Command header. 3733 */ 3734 struct dmub_cmd_header header; 3735 /** 3736 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3737 */ 3738 struct dmub_cmd_lvtma_control_data data; 3739 }; 3740 3741 /** 3742 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3743 */ 3744 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3745 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3746 uint8_t is_usb; /**< is phy is usb */ 3747 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3748 uint8_t is_dp4; /**< is dp in 4 lane */ 3749 }; 3750 3751 /** 3752 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3753 */ 3754 struct dmub_rb_cmd_transmitter_query_dp_alt { 3755 struct dmub_cmd_header header; /**< header */ 3756 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3757 }; 3758 3759 /** 3760 * Maximum number of bytes a chunk sent to DMUB for parsing 3761 */ 3762 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3763 3764 /** 3765 * Represent a chunk of CEA blocks sent to DMUB for parsing 3766 */ 3767 struct dmub_cmd_send_edid_cea { 3768 uint16_t offset; /**< offset into the CEA block */ 3769 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3770 uint16_t cea_total_length; /**< total length of the CEA block */ 3771 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3772 uint8_t pad[3]; /**< padding and for future expansion */ 3773 }; 3774 3775 /** 3776 * Result of VSDB parsing from CEA block 3777 */ 3778 struct dmub_cmd_edid_cea_amd_vsdb { 3779 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3780 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3781 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3782 uint16_t min_frame_rate; /**< Maximum frame rate */ 3783 uint16_t max_frame_rate; /**< Minimum frame rate */ 3784 }; 3785 3786 /** 3787 * Result of sending a CEA chunk 3788 */ 3789 struct dmub_cmd_edid_cea_ack { 3790 uint16_t offset; /**< offset of the chunk into the CEA block */ 3791 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3792 uint8_t pad; /**< padding and for future expansion */ 3793 }; 3794 3795 /** 3796 * Specify whether the result is an ACK/NACK or the parsing has finished 3797 */ 3798 enum dmub_cmd_edid_cea_reply_type { 3799 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3800 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3801 }; 3802 3803 /** 3804 * Definition of a DMUB_CMD__EDID_CEA command. 3805 */ 3806 struct dmub_rb_cmd_edid_cea { 3807 struct dmub_cmd_header header; /**< Command header */ 3808 union dmub_cmd_edid_cea_data { 3809 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3810 struct dmub_cmd_edid_cea_output { /**< output with results */ 3811 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3812 union { 3813 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3814 struct dmub_cmd_edid_cea_ack ack; 3815 }; 3816 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3817 } data; /**< Command data */ 3818 3819 }; 3820 3821 /** 3822 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3823 */ 3824 struct dmub_cmd_cable_id_input { 3825 uint8_t phy_inst; /**< phy inst for cable id data */ 3826 }; 3827 3828 /** 3829 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3830 */ 3831 struct dmub_cmd_cable_id_output { 3832 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3833 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3834 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3835 uint8_t RESERVED :2; /**< reserved means not defined */ 3836 }; 3837 3838 /** 3839 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3840 */ 3841 struct dmub_rb_cmd_get_usbc_cable_id { 3842 struct dmub_cmd_header header; /**< Command header */ 3843 /** 3844 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3845 */ 3846 union dmub_cmd_cable_id_data { 3847 struct dmub_cmd_cable_id_input input; /**< Input */ 3848 struct dmub_cmd_cable_id_output output; /**< Output */ 3849 uint8_t output_raw; /**< Raw data output */ 3850 } data; 3851 }; 3852 3853 /** 3854 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3855 */ 3856 enum dmub_cmd_secure_display_type { 3857 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3858 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3859 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3860 }; 3861 3862 /** 3863 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3864 */ 3865 struct dmub_rb_cmd_secure_display { 3866 struct dmub_cmd_header header; 3867 /** 3868 * Data passed from driver to dmub firmware. 3869 */ 3870 struct dmub_cmd_roi_info { 3871 uint16_t x_start; 3872 uint16_t x_end; 3873 uint16_t y_start; 3874 uint16_t y_end; 3875 uint8_t otg_id; 3876 uint8_t phy_id; 3877 } roi_info; 3878 }; 3879 3880 /** 3881 * union dmub_rb_cmd - DMUB inbox command. 3882 */ 3883 union dmub_rb_cmd { 3884 /** 3885 * Elements shared with all commands. 3886 */ 3887 struct dmub_rb_cmd_common cmd_common; 3888 /** 3889 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3890 */ 3891 struct dmub_rb_cmd_read_modify_write read_modify_write; 3892 /** 3893 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3894 */ 3895 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3896 /** 3897 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3898 */ 3899 struct dmub_rb_cmd_burst_write burst_write; 3900 /** 3901 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3902 */ 3903 struct dmub_rb_cmd_reg_wait reg_wait; 3904 /** 3905 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3906 */ 3907 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3908 /** 3909 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3910 */ 3911 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3912 /** 3913 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3914 */ 3915 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3916 /** 3917 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3918 */ 3919 struct dmub_rb_cmd_dpphy_init dpphy_init; 3920 /** 3921 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3922 */ 3923 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3924 /** 3925 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3926 */ 3927 struct dmub_rb_cmd_domain_control domain_control; 3928 /** 3929 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3930 */ 3931 struct dmub_rb_cmd_psr_set_version psr_set_version; 3932 /** 3933 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3934 */ 3935 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3936 /** 3937 * Definition of a DMUB_CMD__PSR_ENABLE command. 3938 */ 3939 struct dmub_rb_cmd_psr_enable psr_enable; 3940 /** 3941 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3942 */ 3943 struct dmub_rb_cmd_psr_set_level psr_set_level; 3944 /** 3945 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3946 */ 3947 struct dmub_rb_cmd_psr_force_static psr_force_static; 3948 /** 3949 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3950 */ 3951 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3952 /** 3953 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3954 */ 3955 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3956 /** 3957 * Definition of a DMUB_CMD__HW_LOCK command. 3958 * Command is used by driver and FW. 3959 */ 3960 struct dmub_rb_cmd_lock_hw lock_hw; 3961 /** 3962 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3963 */ 3964 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3965 /** 3966 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3967 */ 3968 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3969 /** 3970 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3971 */ 3972 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3973 /** 3974 * Definition of a DMUB_CMD__MALL command. 3975 */ 3976 struct dmub_rb_cmd_mall mall; 3977 /** 3978 * Definition of a DMUB_CMD__CAB command. 3979 */ 3980 struct dmub_rb_cmd_cab_for_ss cab; 3981 3982 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3983 3984 /** 3985 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3986 */ 3987 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3988 3989 /** 3990 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3991 */ 3992 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3993 3994 /** 3995 * Definition of DMUB_CMD__PANEL_CNTL commands. 3996 */ 3997 struct dmub_rb_cmd_panel_cntl panel_cntl; 3998 /** 3999 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4000 */ 4001 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 4002 4003 /** 4004 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4005 */ 4006 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 4007 4008 /** 4009 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4010 */ 4011 struct dmub_rb_cmd_abm_set_level abm_set_level; 4012 4013 /** 4014 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4015 */ 4016 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 4017 4018 /** 4019 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4020 */ 4021 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 4022 4023 /** 4024 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4025 */ 4026 struct dmub_rb_cmd_abm_init_config abm_init_config; 4027 4028 /** 4029 * Definition of a DMUB_CMD__ABM_PAUSE command. 4030 */ 4031 struct dmub_rb_cmd_abm_pause abm_pause; 4032 4033 /** 4034 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4035 */ 4036 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 4037 4038 /** 4039 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 4040 */ 4041 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 4042 4043 /** 4044 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 4045 */ 4046 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 4047 4048 /** 4049 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4050 */ 4051 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 4052 4053 /** 4054 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4055 */ 4056 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 4057 struct dmub_rb_cmd_drr_update drr_update; 4058 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 4059 4060 /** 4061 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4062 */ 4063 struct dmub_rb_cmd_lvtma_control lvtma_control; 4064 /** 4065 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4066 */ 4067 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 4068 /** 4069 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 4070 */ 4071 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 4072 /** 4073 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 4074 */ 4075 struct dmub_rb_cmd_set_config_access set_config_access; 4076 /** 4077 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 4078 */ 4079 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 4080 /** 4081 * Definition of a DMUB_CMD__EDID_CEA command. 4082 */ 4083 struct dmub_rb_cmd_edid_cea edid_cea; 4084 /** 4085 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 4086 */ 4087 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 4088 4089 /** 4090 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 4091 */ 4092 struct dmub_rb_cmd_query_hpd_state query_hpd; 4093 /** 4094 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 4095 */ 4096 struct dmub_rb_cmd_secure_display secure_display; 4097 4098 /** 4099 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 4100 */ 4101 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 4102 /** 4103 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 4104 */ 4105 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 4106 /* 4107 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4108 */ 4109 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 4110 /** 4111 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4112 */ 4113 struct dmub_rb_cmd_replay_enable replay_enable; 4114 /** 4115 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4116 */ 4117 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 4118 /** 4119 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4120 */ 4121 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 4122 }; 4123 4124 /** 4125 * union dmub_rb_out_cmd - Outbox command 4126 */ 4127 union dmub_rb_out_cmd { 4128 /** 4129 * Parameters common to every command. 4130 */ 4131 struct dmub_rb_cmd_common cmd_common; 4132 /** 4133 * AUX reply command. 4134 */ 4135 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 4136 /** 4137 * HPD notify command. 4138 */ 4139 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 4140 /** 4141 * SET_CONFIG reply command. 4142 */ 4143 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 4144 /** 4145 * DPIA notification command. 4146 */ 4147 struct dmub_rb_cmd_dpia_notification dpia_notification; 4148 }; 4149 #pragma pack(pop) 4150 4151 4152 //============================================================================== 4153 //</DMUB_CMD>=================================================================== 4154 //============================================================================== 4155 //< DMUB_RB>==================================================================== 4156 //============================================================================== 4157 4158 #if defined(__cplusplus) 4159 extern "C" { 4160 #endif 4161 4162 /** 4163 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 4164 */ 4165 struct dmub_rb_init_params { 4166 void *ctx; /**< Caller provided context pointer */ 4167 void *base_address; /**< CPU base address for ring's data */ 4168 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4169 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 4170 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 4171 }; 4172 4173 /** 4174 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 4175 */ 4176 struct dmub_rb { 4177 void *base_address; /**< CPU address for the ring's data */ 4178 uint32_t rptr; /**< Read pointer for consumer in bytes */ 4179 uint32_t wrpt; /**< Write pointer for producer in bytes */ 4180 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4181 4182 void *ctx; /**< Caller provided context pointer */ 4183 void *dmub; /**< Pointer to the DMUB interface */ 4184 }; 4185 4186 /** 4187 * @brief Checks if the ringbuffer is empty. 4188 * 4189 * @param rb DMUB Ringbuffer 4190 * @return true if empty 4191 * @return false otherwise 4192 */ 4193 static inline bool dmub_rb_empty(struct dmub_rb *rb) 4194 { 4195 return (rb->wrpt == rb->rptr); 4196 } 4197 4198 /** 4199 * @brief Checks if the ringbuffer is full 4200 * 4201 * @param rb DMUB Ringbuffer 4202 * @return true if full 4203 * @return false otherwise 4204 */ 4205 static inline bool dmub_rb_full(struct dmub_rb *rb) 4206 { 4207 uint32_t data_count; 4208 4209 if (rb->wrpt >= rb->rptr) 4210 data_count = rb->wrpt - rb->rptr; 4211 else 4212 data_count = rb->capacity - (rb->rptr - rb->wrpt); 4213 4214 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 4215 } 4216 4217 /** 4218 * @brief Pushes a command into the ringbuffer 4219 * 4220 * @param rb DMUB ringbuffer 4221 * @param cmd The command to push 4222 * @return true if the ringbuffer was not full 4223 * @return false otherwise 4224 */ 4225 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 4226 const union dmub_rb_cmd *cmd) 4227 { 4228 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 4229 const uint64_t *src = (const uint64_t *)cmd; 4230 uint8_t i; 4231 4232 if (dmub_rb_full(rb)) 4233 return false; 4234 4235 // copying data 4236 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4237 *dst++ = *src++; 4238 4239 rb->wrpt += DMUB_RB_CMD_SIZE; 4240 4241 if (rb->wrpt >= rb->capacity) 4242 rb->wrpt %= rb->capacity; 4243 4244 return true; 4245 } 4246 4247 /** 4248 * @brief Pushes a command into the DMUB outbox ringbuffer 4249 * 4250 * @param rb DMUB outbox ringbuffer 4251 * @param cmd Outbox command 4252 * @return true if not full 4253 * @return false otherwise 4254 */ 4255 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 4256 const union dmub_rb_out_cmd *cmd) 4257 { 4258 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 4259 const uint8_t *src = (const uint8_t *)cmd; 4260 4261 if (dmub_rb_full(rb)) 4262 return false; 4263 4264 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 4265 4266 rb->wrpt += DMUB_RB_CMD_SIZE; 4267 4268 if (rb->wrpt >= rb->capacity) 4269 rb->wrpt %= rb->capacity; 4270 4271 return true; 4272 } 4273 4274 /** 4275 * @brief Returns the next unprocessed command in the ringbuffer. 4276 * 4277 * @param rb DMUB ringbuffer 4278 * @param cmd The command to return 4279 * @return true if not empty 4280 * @return false otherwise 4281 */ 4282 static inline bool dmub_rb_front(struct dmub_rb *rb, 4283 union dmub_rb_cmd **cmd) 4284 { 4285 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 4286 4287 if (dmub_rb_empty(rb)) 4288 return false; 4289 4290 *cmd = (union dmub_rb_cmd *)rb_cmd; 4291 4292 return true; 4293 } 4294 4295 /** 4296 * @brief Determines the next ringbuffer offset. 4297 * 4298 * @param rb DMUB inbox ringbuffer 4299 * @param num_cmds Number of commands 4300 * @param next_rptr The next offset in the ringbuffer 4301 */ 4302 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 4303 uint32_t num_cmds, 4304 uint32_t *next_rptr) 4305 { 4306 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 4307 4308 if (*next_rptr >= rb->capacity) 4309 *next_rptr %= rb->capacity; 4310 } 4311 4312 /** 4313 * @brief Returns a pointer to a command in the inbox. 4314 * 4315 * @param rb DMUB inbox ringbuffer 4316 * @param cmd The inbox command to return 4317 * @param rptr The ringbuffer offset 4318 * @return true if not empty 4319 * @return false otherwise 4320 */ 4321 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 4322 union dmub_rb_cmd **cmd, 4323 uint32_t rptr) 4324 { 4325 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 4326 4327 if (dmub_rb_empty(rb)) 4328 return false; 4329 4330 *cmd = (union dmub_rb_cmd *)rb_cmd; 4331 4332 return true; 4333 } 4334 4335 /** 4336 * @brief Returns the next unprocessed command in the outbox. 4337 * 4338 * @param rb DMUB outbox ringbuffer 4339 * @param cmd The outbox command to return 4340 * @return true if not empty 4341 * @return false otherwise 4342 */ 4343 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 4344 union dmub_rb_out_cmd *cmd) 4345 { 4346 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 4347 uint64_t *dst = (uint64_t *)cmd; 4348 uint8_t i; 4349 4350 if (dmub_rb_empty(rb)) 4351 return false; 4352 4353 // copying data 4354 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4355 *dst++ = *src++; 4356 4357 return true; 4358 } 4359 4360 /** 4361 * @brief Removes the front entry in the ringbuffer. 4362 * 4363 * @param rb DMUB ringbuffer 4364 * @return true if the command was removed 4365 * @return false if there were no commands 4366 */ 4367 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 4368 { 4369 if (dmub_rb_empty(rb)) 4370 return false; 4371 4372 rb->rptr += DMUB_RB_CMD_SIZE; 4373 4374 if (rb->rptr >= rb->capacity) 4375 rb->rptr %= rb->capacity; 4376 4377 return true; 4378 } 4379 4380 /** 4381 * @brief Flushes commands in the ringbuffer to framebuffer memory. 4382 * 4383 * Avoids a race condition where DMCUB accesses memory while 4384 * there are still writes in flight to framebuffer. 4385 * 4386 * @param rb DMUB ringbuffer 4387 */ 4388 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 4389 { 4390 uint32_t rptr = rb->rptr; 4391 uint32_t wptr = rb->wrpt; 4392 4393 while (rptr != wptr) { 4394 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 4395 uint8_t i; 4396 4397 /* Don't remove this. 4398 * The contents need to actually be read from the ring buffer 4399 * for this function to be effective. 4400 */ 4401 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4402 (void)READ_ONCE(*data++); 4403 4404 rptr += DMUB_RB_CMD_SIZE; 4405 if (rptr >= rb->capacity) 4406 rptr %= rb->capacity; 4407 } 4408 } 4409 4410 /** 4411 * @brief Initializes a DMCUB ringbuffer 4412 * 4413 * @param rb DMUB ringbuffer 4414 * @param init_params initial configuration for the ringbuffer 4415 */ 4416 static inline void dmub_rb_init(struct dmub_rb *rb, 4417 struct dmub_rb_init_params *init_params) 4418 { 4419 rb->base_address = init_params->base_address; 4420 rb->capacity = init_params->capacity; 4421 rb->rptr = init_params->read_ptr; 4422 rb->wrpt = init_params->write_ptr; 4423 } 4424 4425 /** 4426 * @brief Copies output data from in/out commands into the given command. 4427 * 4428 * @param rb DMUB ringbuffer 4429 * @param cmd Command to copy data into 4430 */ 4431 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 4432 union dmub_rb_cmd *cmd) 4433 { 4434 // Copy rb entry back into command 4435 uint8_t *rd_ptr = (rb->rptr == 0) ? 4436 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 4437 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 4438 4439 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 4440 } 4441 4442 #if defined(__cplusplus) 4443 } 4444 #endif 4445 4446 //============================================================================== 4447 //</DMUB_RB>==================================================================== 4448 //============================================================================== 4449 4450 #endif /* _DMUB_CMD_H_ */ 4451