1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 } bitfields; 229 230 /** 231 * Union for debug flags. 232 */ 233 uint32_t u32All; 234 }; 235 236 /** 237 * DMUB visual confirm color 238 */ 239 struct dmub_feature_caps { 240 /** 241 * Max PSR version supported by FW. 242 */ 243 uint8_t psr; 244 uint8_t fw_assisted_mclk_switch; 245 uint8_t reserved[6]; 246 }; 247 248 struct dmub_visual_confirm_color { 249 /** 250 * Maximum 10 bits color value 251 */ 252 uint16_t color_r_cr; 253 uint16_t color_g_y; 254 uint16_t color_b_cb; 255 uint16_t panel_inst; 256 }; 257 258 #if defined(__cplusplus) 259 } 260 #endif 261 262 //============================================================================== 263 //</DMUB_TYPES>================================================================= 264 //============================================================================== 265 //< DMUB_META>================================================================== 266 //============================================================================== 267 #pragma pack(push, 1) 268 269 /* Magic value for identifying dmub_fw_meta_info */ 270 #define DMUB_FW_META_MAGIC 0x444D5542 271 272 /* Offset from the end of the file to the dmub_fw_meta_info */ 273 #define DMUB_FW_META_OFFSET 0x24 274 275 /** 276 * struct dmub_fw_meta_info - metadata associated with fw binary 277 * 278 * NOTE: This should be considered a stable API. Fields should 279 * not be repurposed or reordered. New fields should be 280 * added instead to extend the structure. 281 * 282 * @magic_value: magic value identifying DMUB firmware meta info 283 * @fw_region_size: size of the firmware state region 284 * @trace_buffer_size: size of the tracebuffer region 285 * @fw_version: the firmware version information 286 * @dal_fw: 1 if the firmware is DAL 287 */ 288 struct dmub_fw_meta_info { 289 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 290 uint32_t fw_region_size; /**< size of the firmware state region */ 291 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 292 uint32_t fw_version; /**< the firmware version information */ 293 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 294 uint8_t reserved[3]; /**< padding bits */ 295 }; 296 297 /** 298 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 299 */ 300 union dmub_fw_meta { 301 struct dmub_fw_meta_info info; /**< metadata info */ 302 uint8_t reserved[64]; /**< padding bits */ 303 }; 304 305 #pragma pack(pop) 306 307 //============================================================================== 308 //< DMUB Trace Buffer>================================================================ 309 //============================================================================== 310 /** 311 * dmub_trace_code_t - firmware trace code, 32-bits 312 */ 313 typedef uint32_t dmub_trace_code_t; 314 315 /** 316 * struct dmcub_trace_buf_entry - Firmware trace entry 317 */ 318 struct dmcub_trace_buf_entry { 319 dmub_trace_code_t trace_code; /**< trace code for the event */ 320 uint32_t tick_count; /**< the tick count at time of trace */ 321 uint32_t param0; /**< trace defined parameter 0 */ 322 uint32_t param1; /**< trace defined parameter 1 */ 323 }; 324 325 //============================================================================== 326 //< DMUB_STATUS>================================================================ 327 //============================================================================== 328 329 /** 330 * DMCUB scratch registers can be used to determine firmware status. 331 * Current scratch register usage is as follows: 332 * 333 * SCRATCH0: FW Boot Status register 334 * SCRATCH5: LVTMA Status Register 335 * SCRATCH15: FW Boot Options register 336 */ 337 338 /** 339 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 340 */ 341 union dmub_fw_boot_status { 342 struct { 343 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 344 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 345 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 346 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 347 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 348 uint32_t reserved : 1; 349 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 350 351 } bits; /**< status bits */ 352 uint32_t all; /**< 32-bit access to status bits */ 353 }; 354 355 /** 356 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 357 */ 358 enum dmub_fw_boot_status_bit { 359 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 360 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 361 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 362 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 363 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 364 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 365 }; 366 367 /* Register bit definition for SCRATCH5 */ 368 union dmub_lvtma_status { 369 struct { 370 uint32_t psp_ok : 1; 371 uint32_t edp_on : 1; 372 uint32_t reserved : 30; 373 } bits; 374 uint32_t all; 375 }; 376 377 enum dmub_lvtma_status_bit { 378 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 379 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 380 }; 381 382 /** 383 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 384 */ 385 union dmub_fw_boot_options { 386 struct { 387 uint32_t pemu_env : 1; /**< 1 if PEMU */ 388 uint32_t fpga_env : 1; /**< 1 if FPGA */ 389 uint32_t optimized_init : 1; /**< 1 if optimized init */ 390 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 391 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 392 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 393 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 394 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 395 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 396 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 397 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 398 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 399 uint32_t power_optimization: 1; 400 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 401 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 402 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 403 404 uint32_t reserved : 17; /**< reserved */ 405 } bits; /**< boot bits */ 406 uint32_t all; /**< 32-bit access to bits */ 407 }; 408 409 enum dmub_fw_boot_options_bit { 410 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 411 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 412 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 413 }; 414 415 //============================================================================== 416 //</DMUB_STATUS>================================================================ 417 //============================================================================== 418 //< DMUB_VBIOS>================================================================= 419 //============================================================================== 420 421 /* 422 * enum dmub_cmd_vbios_type - VBIOS commands. 423 * 424 * Command IDs should be treated as stable ABI. 425 * Do not reuse or modify IDs. 426 */ 427 enum dmub_cmd_vbios_type { 428 /** 429 * Configures the DIG encoder. 430 */ 431 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 432 /** 433 * Controls the PHY. 434 */ 435 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 436 /** 437 * Sets the pixel clock/symbol clock. 438 */ 439 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 440 /** 441 * Enables or disables power gating. 442 */ 443 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 444 /** 445 * Controls embedded panels. 446 */ 447 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 448 /** 449 * Query DP alt status on a transmitter. 450 */ 451 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 452 }; 453 454 //============================================================================== 455 //</DMUB_VBIOS>================================================================= 456 //============================================================================== 457 //< DMUB_GPINT>================================================================= 458 //============================================================================== 459 460 /** 461 * The shifts and masks below may alternatively be used to format and read 462 * the command register bits. 463 */ 464 465 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 466 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 467 468 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 469 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 470 471 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 472 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 473 474 /** 475 * Command responses. 476 */ 477 478 /** 479 * Return response for DMUB_GPINT__STOP_FW command. 480 */ 481 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 482 483 /** 484 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 485 */ 486 union dmub_gpint_data_register { 487 struct { 488 uint32_t param : 16; /**< 16-bit parameter */ 489 uint32_t command_code : 12; /**< GPINT command */ 490 uint32_t status : 4; /**< Command status bit */ 491 } bits; /**< GPINT bit access */ 492 uint32_t all; /**< GPINT 32-bit access */ 493 }; 494 495 /* 496 * enum dmub_gpint_command - GPINT command to DMCUB FW 497 * 498 * Command IDs should be treated as stable ABI. 499 * Do not reuse or modify IDs. 500 */ 501 enum dmub_gpint_command { 502 /** 503 * Invalid command, ignored. 504 */ 505 DMUB_GPINT__INVALID_COMMAND = 0, 506 /** 507 * DESC: Queries the firmware version. 508 * RETURN: Firmware version. 509 */ 510 DMUB_GPINT__GET_FW_VERSION = 1, 511 /** 512 * DESC: Halts the firmware. 513 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 514 */ 515 DMUB_GPINT__STOP_FW = 2, 516 /** 517 * DESC: Get PSR state from FW. 518 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 519 */ 520 DMUB_GPINT__GET_PSR_STATE = 7, 521 /** 522 * DESC: Notifies DMCUB of the currently active streams. 523 * ARGS: Stream mask, 1 bit per active stream index. 524 */ 525 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 526 /** 527 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 528 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 529 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 530 * RETURN: PSR residency in milli-percent. 531 */ 532 DMUB_GPINT__PSR_RESIDENCY = 9, 533 534 /** 535 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 536 */ 537 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 538 }; 539 540 /** 541 * INBOX0 generic command definition 542 */ 543 union dmub_inbox0_cmd_common { 544 struct { 545 uint32_t command_code: 8; /**< INBOX0 command code */ 546 uint32_t param: 24; /**< 24-bit parameter */ 547 } bits; 548 uint32_t all; 549 }; 550 551 /** 552 * INBOX0 hw_lock command definition 553 */ 554 union dmub_inbox0_cmd_lock_hw { 555 struct { 556 uint32_t command_code: 8; 557 558 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 559 uint32_t hw_lock_client: 2; 560 561 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 562 uint32_t otg_inst: 3; 563 uint32_t opp_inst: 3; 564 uint32_t dig_inst: 3; 565 566 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 567 uint32_t lock_pipe: 1; 568 uint32_t lock_cursor: 1; 569 uint32_t lock_dig: 1; 570 uint32_t triple_buffer_lock: 1; 571 572 uint32_t lock: 1; /**< Lock */ 573 uint32_t should_release: 1; /**< Release */ 574 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 575 } bits; 576 uint32_t all; 577 }; 578 579 union dmub_inbox0_data_register { 580 union dmub_inbox0_cmd_common inbox0_cmd_common; 581 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 582 }; 583 584 enum dmub_inbox0_command { 585 /** 586 * DESC: Invalid command, ignored. 587 */ 588 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 589 /** 590 * DESC: Notification to acquire/release HW lock 591 * ARGS: 592 */ 593 DMUB_INBOX0_CMD__HW_LOCK = 1, 594 }; 595 //============================================================================== 596 //</DMUB_GPINT>================================================================= 597 //============================================================================== 598 //< DMUB_CMD>=================================================================== 599 //============================================================================== 600 601 /** 602 * Size in bytes of each DMUB command. 603 */ 604 #define DMUB_RB_CMD_SIZE 64 605 606 /** 607 * Maximum number of items in the DMUB ringbuffer. 608 */ 609 #define DMUB_RB_MAX_ENTRY 128 610 611 /** 612 * Ringbuffer size in bytes. 613 */ 614 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 615 616 /** 617 * REG_SET mask for reg offload. 618 */ 619 #define REG_SET_MASK 0xFFFF 620 621 /* 622 * enum dmub_cmd_type - DMUB inbox command. 623 * 624 * Command IDs should be treated as stable ABI. 625 * Do not reuse or modify IDs. 626 */ 627 enum dmub_cmd_type { 628 /** 629 * Invalid command. 630 */ 631 DMUB_CMD__NULL = 0, 632 /** 633 * Read modify write register sequence offload. 634 */ 635 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 636 /** 637 * Field update register sequence offload. 638 */ 639 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 640 /** 641 * Burst write sequence offload. 642 */ 643 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 644 /** 645 * Reg wait sequence offload. 646 */ 647 DMUB_CMD__REG_REG_WAIT = 4, 648 /** 649 * Workaround to avoid HUBP underflow during NV12 playback. 650 */ 651 DMUB_CMD__PLAT_54186_WA = 5, 652 /** 653 * Command type used to query FW feature caps. 654 */ 655 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 656 /** 657 * Command type used to get visual confirm color. 658 */ 659 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 660 /** 661 * Command type used for all PSR commands. 662 */ 663 DMUB_CMD__PSR = 64, 664 /** 665 * Command type used for all MALL commands. 666 */ 667 DMUB_CMD__MALL = 65, 668 /** 669 * Command type used for all ABM commands. 670 */ 671 DMUB_CMD__ABM = 66, 672 /** 673 * Command type used to update dirty rects in FW. 674 */ 675 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 676 /** 677 * Command type used to update cursor info in FW. 678 */ 679 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 680 /** 681 * Command type used for HW locking in FW. 682 */ 683 DMUB_CMD__HW_LOCK = 69, 684 /** 685 * Command type used to access DP AUX. 686 */ 687 DMUB_CMD__DP_AUX_ACCESS = 70, 688 /** 689 * Command type used for OUTBOX1 notification enable 690 */ 691 DMUB_CMD__OUTBOX1_ENABLE = 71, 692 693 /** 694 * Command type used for all idle optimization commands. 695 */ 696 DMUB_CMD__IDLE_OPT = 72, 697 /** 698 * Command type used for all clock manager commands. 699 */ 700 DMUB_CMD__CLK_MGR = 73, 701 /** 702 * Command type used for all panel control commands. 703 */ 704 DMUB_CMD__PANEL_CNTL = 74, 705 /** 706 * Command type used for <TODO:description> 707 */ 708 DMUB_CMD__CAB_FOR_SS = 75, 709 710 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 711 712 /** 713 * Command type used for interfacing with DPIA. 714 */ 715 DMUB_CMD__DPIA = 77, 716 /** 717 * Command type used for EDID CEA parsing 718 */ 719 DMUB_CMD__EDID_CEA = 79, 720 /** 721 * Command type used for getting usbc cable ID 722 */ 723 DMUB_CMD_GET_USBC_CABLE_ID = 81, 724 /** 725 * Command type used to query HPD state. 726 */ 727 DMUB_CMD__QUERY_HPD_STATE = 82, 728 /** 729 * Command type used for all VBIOS interface commands. 730 */ 731 DMUB_CMD__VBIOS = 128, 732 }; 733 734 /** 735 * enum dmub_out_cmd_type - DMUB outbox commands. 736 */ 737 enum dmub_out_cmd_type { 738 /** 739 * Invalid outbox command, ignored. 740 */ 741 DMUB_OUT_CMD__NULL = 0, 742 /** 743 * Command type used for DP AUX Reply data notification 744 */ 745 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 746 /** 747 * Command type used for DP HPD event notification 748 */ 749 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 750 /** 751 * Command type used for SET_CONFIG Reply notification 752 */ 753 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 754 }; 755 756 /* DMUB_CMD__DPIA command sub-types. */ 757 enum dmub_cmd_dpia_type { 758 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 759 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 760 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 761 }; 762 763 #pragma pack(push, 1) 764 765 /** 766 * struct dmub_cmd_header - Common command header fields. 767 */ 768 struct dmub_cmd_header { 769 unsigned int type : 8; /**< command type */ 770 unsigned int sub_type : 8; /**< command sub type */ 771 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 772 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 773 unsigned int reserved0 : 6; /**< reserved bits */ 774 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 775 unsigned int reserved1 : 2; /**< reserved bits */ 776 }; 777 778 /* 779 * struct dmub_cmd_read_modify_write_sequence - Read modify write 780 * 781 * 60 payload bytes can hold up to 5 sets of read modify writes, 782 * each take 3 dwords. 783 * 784 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 785 * 786 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 787 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 788 */ 789 struct dmub_cmd_read_modify_write_sequence { 790 uint32_t addr; /**< register address */ 791 uint32_t modify_mask; /**< modify mask */ 792 uint32_t modify_value; /**< modify value */ 793 }; 794 795 /** 796 * Maximum number of ops in read modify write sequence. 797 */ 798 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 799 800 /** 801 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 802 */ 803 struct dmub_rb_cmd_read_modify_write { 804 struct dmub_cmd_header header; /**< command header */ 805 /** 806 * Read modify write sequence. 807 */ 808 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 809 }; 810 811 /* 812 * Update a register with specified masks and values sequeunce 813 * 814 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 815 * 816 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 817 * 818 * 819 * USE CASE: 820 * 1. auto-increment register where additional read would update pointer and produce wrong result 821 * 2. toggle a bit without read in the middle 822 */ 823 824 struct dmub_cmd_reg_field_update_sequence { 825 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 826 uint32_t modify_value; /**< value to update with */ 827 }; 828 829 /** 830 * Maximum number of ops in field update sequence. 831 */ 832 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 833 834 /** 835 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 836 */ 837 struct dmub_rb_cmd_reg_field_update_sequence { 838 struct dmub_cmd_header header; /**< command header */ 839 uint32_t addr; /**< register address */ 840 /** 841 * Field update sequence. 842 */ 843 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 844 }; 845 846 847 /** 848 * Maximum number of burst write values. 849 */ 850 #define DMUB_BURST_WRITE_VALUES__MAX 14 851 852 /* 853 * struct dmub_rb_cmd_burst_write - Burst write 854 * 855 * support use case such as writing out LUTs. 856 * 857 * 60 payload bytes can hold up to 14 values to write to given address 858 * 859 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 860 */ 861 struct dmub_rb_cmd_burst_write { 862 struct dmub_cmd_header header; /**< command header */ 863 uint32_t addr; /**< register start address */ 864 /** 865 * Burst write register values. 866 */ 867 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 868 }; 869 870 /** 871 * struct dmub_rb_cmd_common - Common command header 872 */ 873 struct dmub_rb_cmd_common { 874 struct dmub_cmd_header header; /**< command header */ 875 /** 876 * Padding to RB_CMD_SIZE 877 */ 878 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 879 }; 880 881 /** 882 * struct dmub_cmd_reg_wait_data - Register wait data 883 */ 884 struct dmub_cmd_reg_wait_data { 885 uint32_t addr; /**< Register address */ 886 uint32_t mask; /**< Mask for register bits */ 887 uint32_t condition_field_value; /**< Value to wait for */ 888 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 889 }; 890 891 /** 892 * struct dmub_rb_cmd_reg_wait - Register wait command 893 */ 894 struct dmub_rb_cmd_reg_wait { 895 struct dmub_cmd_header header; /**< Command header */ 896 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 897 }; 898 899 /** 900 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 901 * 902 * Reprograms surface parameters to avoid underflow. 903 */ 904 struct dmub_cmd_PLAT_54186_wa { 905 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 906 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 907 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 908 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 909 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 910 struct { 911 uint8_t hubp_inst : 4; /**< HUBP instance */ 912 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 913 uint8_t immediate :1; /**< Immediate flip */ 914 uint8_t vmid : 4; /**< VMID */ 915 uint8_t grph_stereo : 1; /**< 1 if stereo */ 916 uint32_t reserved : 21; /**< Reserved */ 917 } flip_params; /**< Pageflip parameters */ 918 uint32_t reserved[9]; /**< Reserved bits */ 919 }; 920 921 /** 922 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 923 */ 924 struct dmub_rb_cmd_PLAT_54186_wa { 925 struct dmub_cmd_header header; /**< Command header */ 926 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 927 }; 928 929 /** 930 * struct dmub_rb_cmd_mall - MALL command data. 931 */ 932 struct dmub_rb_cmd_mall { 933 struct dmub_cmd_header header; /**< Common command header */ 934 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 935 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 936 uint32_t tmr_delay; /**< Timer delay */ 937 uint32_t tmr_scale; /**< Timer scale */ 938 uint16_t cursor_width; /**< Cursor width in pixels */ 939 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 940 uint16_t cursor_height; /**< Cursor height in pixels */ 941 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 942 uint8_t debug_bits; /**< Debug bits */ 943 944 uint8_t reserved1; /**< Reserved bits */ 945 uint8_t reserved2; /**< Reserved bits */ 946 }; 947 948 /** 949 * enum dmub_cmd_cab_type - TODO: 950 */ 951 enum dmub_cmd_cab_type { 952 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 953 DMUB_CMD__CAB_NO_DCN_REQ = 1, 954 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 955 }; 956 957 /** 958 * struct dmub_rb_cmd_cab_for_ss - TODO: 959 */ 960 struct dmub_rb_cmd_cab_for_ss { 961 struct dmub_cmd_header header; 962 uint8_t cab_alloc_ways; /* total number of ways */ 963 uint8_t debug_bits; /* debug bits */ 964 }; 965 966 enum mclk_switch_mode { 967 NONE = 0, 968 FPO = 1, 969 SUBVP = 2, 970 VBLANK = 3, 971 }; 972 973 /* Per pipe struct which stores the MCLK switch mode 974 * data to be sent to DMUB. 975 * Named "v2" for now -- once FPO and SUBVP are fully merged 976 * the type name can be updated 977 */ 978 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 979 union { 980 struct { 981 uint32_t pix_clk_100hz; 982 uint16_t main_vblank_start; 983 uint16_t main_vblank_end; 984 uint16_t mall_region_lines; 985 uint16_t prefetch_lines; 986 uint16_t prefetch_to_mall_start_lines; 987 uint16_t processing_delay_lines; 988 uint16_t htotal; // required to calculate line time for multi-display cases 989 uint16_t vtotal; 990 uint8_t main_pipe_index; 991 uint8_t phantom_pipe_index; 992 /* Since the microschedule is calculated in terms of OTG lines, 993 * include any scaling factors to make sure when we get accurate 994 * conversion when programming MALL_START_LINE (which is in terms 995 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 996 * is 1/2 (numerator = 1, denominator = 2). 997 */ 998 uint8_t scale_factor_numerator; 999 uint8_t scale_factor_denominator; 1000 uint8_t is_drr; 1001 uint8_t pad[2]; 1002 } subvp_data; 1003 1004 struct { 1005 uint32_t pix_clk_100hz; 1006 uint16_t vblank_start; 1007 uint16_t vblank_end; 1008 uint16_t vstartup_start; 1009 uint16_t vtotal; 1010 uint16_t htotal; 1011 uint8_t vblank_pipe_index; 1012 uint8_t padding[2]; 1013 struct { 1014 uint8_t drr_in_use; 1015 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1016 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1017 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1018 uint8_t use_ramping; // Use ramping or not 1019 } drr_info; // DRR considered as part of SubVP + VBLANK case 1020 } vblank_data; 1021 } pipe_config; 1022 1023 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1024 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1025 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1026 */ 1027 uint8_t mode; // enum mclk_switch_mode 1028 }; 1029 1030 /** 1031 * Config data for Sub-VP and FPO 1032 * Named "v2" for now -- once FPO and SUBVP are fully merged 1033 * the type name can be updated 1034 */ 1035 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1036 uint16_t watermark_a_cache; 1037 uint8_t vertical_int_margin_us; 1038 uint8_t pstate_allow_width_us; 1039 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1040 }; 1041 1042 /** 1043 * DMUB rb command definition for Sub-VP and FPO 1044 * Named "v2" for now -- once FPO and SUBVP are fully merged 1045 * the type name can be updated 1046 */ 1047 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1048 struct dmub_cmd_header header; 1049 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1050 }; 1051 1052 /** 1053 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1054 */ 1055 enum dmub_cmd_idle_opt_type { 1056 /** 1057 * DCN hardware restore. 1058 */ 1059 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1060 1061 /** 1062 * DCN hardware save. 1063 */ 1064 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1065 }; 1066 1067 /** 1068 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1069 */ 1070 struct dmub_rb_cmd_idle_opt_dcn_restore { 1071 struct dmub_cmd_header header; /**< header */ 1072 }; 1073 1074 /** 1075 * struct dmub_clocks - Clock update notification. 1076 */ 1077 struct dmub_clocks { 1078 uint32_t dispclk_khz; /**< dispclk kHz */ 1079 uint32_t dppclk_khz; /**< dppclk kHz */ 1080 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1081 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1082 }; 1083 1084 /** 1085 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1086 */ 1087 enum dmub_cmd_clk_mgr_type { 1088 /** 1089 * Notify DMCUB of clock update. 1090 */ 1091 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1092 }; 1093 1094 /** 1095 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1096 */ 1097 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1098 struct dmub_cmd_header header; /**< header */ 1099 struct dmub_clocks clocks; /**< clock data */ 1100 }; 1101 1102 /** 1103 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1104 */ 1105 struct dmub_cmd_digx_encoder_control_data { 1106 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1107 }; 1108 1109 /** 1110 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1111 */ 1112 struct dmub_rb_cmd_digx_encoder_control { 1113 struct dmub_cmd_header header; /**< header */ 1114 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1115 }; 1116 1117 /** 1118 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1119 */ 1120 struct dmub_cmd_set_pixel_clock_data { 1121 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1122 }; 1123 1124 /** 1125 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1126 */ 1127 struct dmub_rb_cmd_set_pixel_clock { 1128 struct dmub_cmd_header header; /**< header */ 1129 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1130 }; 1131 1132 /** 1133 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1134 */ 1135 struct dmub_cmd_enable_disp_power_gating_data { 1136 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1137 }; 1138 1139 /** 1140 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1141 */ 1142 struct dmub_rb_cmd_enable_disp_power_gating { 1143 struct dmub_cmd_header header; /**< header */ 1144 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1145 }; 1146 1147 /** 1148 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1149 */ 1150 struct dmub_dig_transmitter_control_data_v1_7 { 1151 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1152 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1153 union { 1154 uint8_t digmode; /**< enum atom_encode_mode_def */ 1155 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1156 } mode_laneset; 1157 uint8_t lanenum; /**< Number of lanes */ 1158 union { 1159 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1160 } symclk_units; 1161 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1162 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1163 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1164 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1165 uint8_t reserved1; /**< For future use */ 1166 uint8_t reserved2[3]; /**< For future use */ 1167 uint32_t reserved3[11]; /**< For future use */ 1168 }; 1169 1170 /** 1171 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1172 */ 1173 union dmub_cmd_dig1_transmitter_control_data { 1174 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1175 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1176 }; 1177 1178 /** 1179 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1180 */ 1181 struct dmub_rb_cmd_dig1_transmitter_control { 1182 struct dmub_cmd_header header; /**< header */ 1183 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1184 }; 1185 1186 /** 1187 * DPIA tunnel command parameters. 1188 */ 1189 struct dmub_cmd_dig_dpia_control_data { 1190 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1191 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1192 union { 1193 uint8_t digmode; /** enum atom_encode_mode_def */ 1194 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1195 } mode_laneset; 1196 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1197 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1198 uint8_t hpdsel; /** =0: HPD is not assigned */ 1199 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1200 uint8_t dpia_id; /** Index of DPIA */ 1201 uint8_t fec_rdy : 1; 1202 uint8_t reserved : 7; 1203 uint32_t reserved1; 1204 }; 1205 1206 /** 1207 * DMUB command for DPIA tunnel control. 1208 */ 1209 struct dmub_rb_cmd_dig1_dpia_control { 1210 struct dmub_cmd_header header; 1211 struct dmub_cmd_dig_dpia_control_data dpia_control; 1212 }; 1213 1214 /** 1215 * SET_CONFIG Command Payload 1216 */ 1217 struct set_config_cmd_payload { 1218 uint8_t msg_type; /* set config message type */ 1219 uint8_t msg_data; /* set config message data */ 1220 }; 1221 1222 /** 1223 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1224 */ 1225 struct dmub_cmd_set_config_control_data { 1226 struct set_config_cmd_payload cmd_pkt; 1227 uint8_t instance; /* DPIA instance */ 1228 uint8_t immed_status; /* Immediate status returned in case of error */ 1229 }; 1230 1231 /** 1232 * DMUB command structure for SET_CONFIG command. 1233 */ 1234 struct dmub_rb_cmd_set_config_access { 1235 struct dmub_cmd_header header; /* header */ 1236 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1237 }; 1238 1239 /** 1240 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1241 */ 1242 struct dmub_cmd_mst_alloc_slots_control_data { 1243 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1244 uint8_t instance; /* DPIA instance */ 1245 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1246 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1247 }; 1248 1249 /** 1250 * DMUB command structure for SET_ command. 1251 */ 1252 struct dmub_rb_cmd_set_mst_alloc_slots { 1253 struct dmub_cmd_header header; /* header */ 1254 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1255 }; 1256 1257 /** 1258 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1259 */ 1260 struct dmub_rb_cmd_dpphy_init { 1261 struct dmub_cmd_header header; /**< header */ 1262 uint8_t reserved[60]; /**< reserved bits */ 1263 }; 1264 1265 /** 1266 * enum dp_aux_request_action - DP AUX request command listing. 1267 * 1268 * 4 AUX request command bits are shifted to high nibble. 1269 */ 1270 enum dp_aux_request_action { 1271 /** I2C-over-AUX write request */ 1272 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1273 /** I2C-over-AUX read request */ 1274 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1275 /** I2C-over-AUX write status request */ 1276 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1277 /** I2C-over-AUX write request with MOT=1 */ 1278 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1279 /** I2C-over-AUX read request with MOT=1 */ 1280 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1281 /** I2C-over-AUX write status request with MOT=1 */ 1282 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1283 /** Native AUX write request */ 1284 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1285 /** Native AUX read request */ 1286 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1287 }; 1288 1289 /** 1290 * enum aux_return_code_type - DP AUX process return code listing. 1291 */ 1292 enum aux_return_code_type { 1293 /** AUX process succeeded */ 1294 AUX_RET_SUCCESS = 0, 1295 /** AUX process failed with unknown reason */ 1296 AUX_RET_ERROR_UNKNOWN, 1297 /** AUX process completed with invalid reply */ 1298 AUX_RET_ERROR_INVALID_REPLY, 1299 /** AUX process timed out */ 1300 AUX_RET_ERROR_TIMEOUT, 1301 /** HPD was low during AUX process */ 1302 AUX_RET_ERROR_HPD_DISCON, 1303 /** Failed to acquire AUX engine */ 1304 AUX_RET_ERROR_ENGINE_ACQUIRE, 1305 /** AUX request not supported */ 1306 AUX_RET_ERROR_INVALID_OPERATION, 1307 /** AUX process not available */ 1308 AUX_RET_ERROR_PROTOCOL_ERROR, 1309 }; 1310 1311 /** 1312 * enum aux_channel_type - DP AUX channel type listing. 1313 */ 1314 enum aux_channel_type { 1315 /** AUX thru Legacy DP AUX */ 1316 AUX_CHANNEL_LEGACY_DDC, 1317 /** AUX thru DPIA DP tunneling */ 1318 AUX_CHANNEL_DPIA 1319 }; 1320 1321 /** 1322 * struct aux_transaction_parameters - DP AUX request transaction data 1323 */ 1324 struct aux_transaction_parameters { 1325 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1326 uint8_t action; /**< enum dp_aux_request_action */ 1327 uint8_t length; /**< DP AUX request data length */ 1328 uint8_t reserved; /**< For future use */ 1329 uint32_t address; /**< DP AUX address */ 1330 uint8_t data[16]; /**< DP AUX write data */ 1331 }; 1332 1333 /** 1334 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1335 */ 1336 struct dmub_cmd_dp_aux_control_data { 1337 uint8_t instance; /**< AUX instance or DPIA instance */ 1338 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1339 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1340 uint8_t reserved0; /**< For future use */ 1341 uint16_t timeout; /**< timeout time in us */ 1342 uint16_t reserved1; /**< For future use */ 1343 enum aux_channel_type type; /**< enum aux_channel_type */ 1344 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1345 }; 1346 1347 /** 1348 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1349 */ 1350 struct dmub_rb_cmd_dp_aux_access { 1351 /** 1352 * Command header. 1353 */ 1354 struct dmub_cmd_header header; 1355 /** 1356 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1357 */ 1358 struct dmub_cmd_dp_aux_control_data aux_control; 1359 }; 1360 1361 /** 1362 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1363 */ 1364 struct dmub_rb_cmd_outbox1_enable { 1365 /** 1366 * Command header. 1367 */ 1368 struct dmub_cmd_header header; 1369 /** 1370 * enable: 0x0 -> disable outbox1 notification (default value) 1371 * 0x1 -> enable outbox1 notification 1372 */ 1373 uint32_t enable; 1374 }; 1375 1376 /* DP AUX Reply command - OutBox Cmd */ 1377 /** 1378 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1379 */ 1380 struct aux_reply_data { 1381 /** 1382 * Aux cmd 1383 */ 1384 uint8_t command; 1385 /** 1386 * Aux reply data length (max: 16 bytes) 1387 */ 1388 uint8_t length; 1389 /** 1390 * Alignment only 1391 */ 1392 uint8_t pad[2]; 1393 /** 1394 * Aux reply data 1395 */ 1396 uint8_t data[16]; 1397 }; 1398 1399 /** 1400 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1401 */ 1402 struct aux_reply_control_data { 1403 /** 1404 * Reserved for future use 1405 */ 1406 uint32_t handle; 1407 /** 1408 * Aux Instance 1409 */ 1410 uint8_t instance; 1411 /** 1412 * Aux transaction result: definition in enum aux_return_code_type 1413 */ 1414 uint8_t result; 1415 /** 1416 * Alignment only 1417 */ 1418 uint16_t pad; 1419 }; 1420 1421 /** 1422 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1423 */ 1424 struct dmub_rb_cmd_dp_aux_reply { 1425 /** 1426 * Command header. 1427 */ 1428 struct dmub_cmd_header header; 1429 /** 1430 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1431 */ 1432 struct aux_reply_control_data control; 1433 /** 1434 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1435 */ 1436 struct aux_reply_data reply_data; 1437 }; 1438 1439 /* DP HPD Notify command - OutBox Cmd */ 1440 /** 1441 * DP HPD Type 1442 */ 1443 enum dp_hpd_type { 1444 /** 1445 * Normal DP HPD 1446 */ 1447 DP_HPD = 0, 1448 /** 1449 * DP HPD short pulse 1450 */ 1451 DP_IRQ 1452 }; 1453 1454 /** 1455 * DP HPD Status 1456 */ 1457 enum dp_hpd_status { 1458 /** 1459 * DP_HPD status low 1460 */ 1461 DP_HPD_UNPLUG = 0, 1462 /** 1463 * DP_HPD status high 1464 */ 1465 DP_HPD_PLUG 1466 }; 1467 1468 /** 1469 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1470 */ 1471 struct dp_hpd_data { 1472 /** 1473 * DP HPD instance 1474 */ 1475 uint8_t instance; 1476 /** 1477 * HPD type 1478 */ 1479 uint8_t hpd_type; 1480 /** 1481 * HPD status: only for type: DP_HPD to indicate status 1482 */ 1483 uint8_t hpd_status; 1484 /** 1485 * Alignment only 1486 */ 1487 uint8_t pad; 1488 }; 1489 1490 /** 1491 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1492 */ 1493 struct dmub_rb_cmd_dp_hpd_notify { 1494 /** 1495 * Command header. 1496 */ 1497 struct dmub_cmd_header header; 1498 /** 1499 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1500 */ 1501 struct dp_hpd_data hpd_data; 1502 }; 1503 1504 /** 1505 * Definition of a SET_CONFIG reply from DPOA. 1506 */ 1507 enum set_config_status { 1508 SET_CONFIG_PENDING = 0, 1509 SET_CONFIG_ACK_RECEIVED, 1510 SET_CONFIG_RX_TIMEOUT, 1511 SET_CONFIG_UNKNOWN_ERROR, 1512 }; 1513 1514 /** 1515 * Definition of a set_config reply 1516 */ 1517 struct set_config_reply_control_data { 1518 uint8_t instance; /* DPIA Instance */ 1519 uint8_t status; /* Set Config reply */ 1520 uint16_t pad; /* Alignment */ 1521 }; 1522 1523 /** 1524 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1525 */ 1526 struct dmub_rb_cmd_dp_set_config_reply { 1527 struct dmub_cmd_header header; 1528 struct set_config_reply_control_data set_config_reply_control; 1529 }; 1530 1531 /** 1532 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1533 */ 1534 struct dmub_cmd_hpd_state_query_data { 1535 uint8_t instance; /**< HPD instance or DPIA instance */ 1536 uint8_t result; /**< For returning HPD state */ 1537 uint16_t pad; /** < Alignment */ 1538 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1539 enum aux_return_code_type status; /**< for returning the status of command */ 1540 }; 1541 1542 /** 1543 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1544 */ 1545 struct dmub_rb_cmd_query_hpd_state { 1546 /** 1547 * Command header. 1548 */ 1549 struct dmub_cmd_header header; 1550 /** 1551 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1552 */ 1553 struct dmub_cmd_hpd_state_query_data data; 1554 }; 1555 1556 /* 1557 * Command IDs should be treated as stable ABI. 1558 * Do not reuse or modify IDs. 1559 */ 1560 1561 /** 1562 * PSR command sub-types. 1563 */ 1564 enum dmub_cmd_psr_type { 1565 /** 1566 * Set PSR version support. 1567 */ 1568 DMUB_CMD__PSR_SET_VERSION = 0, 1569 /** 1570 * Copy driver-calculated parameters to PSR state. 1571 */ 1572 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1573 /** 1574 * Enable PSR. 1575 */ 1576 DMUB_CMD__PSR_ENABLE = 2, 1577 1578 /** 1579 * Disable PSR. 1580 */ 1581 DMUB_CMD__PSR_DISABLE = 3, 1582 1583 /** 1584 * Set PSR level. 1585 * PSR level is a 16-bit value dicated by driver that 1586 * will enable/disable different functionality. 1587 */ 1588 DMUB_CMD__PSR_SET_LEVEL = 4, 1589 1590 /** 1591 * Forces PSR enabled until an explicit PSR disable call. 1592 */ 1593 DMUB_CMD__PSR_FORCE_STATIC = 5, 1594 /** 1595 * Set vtotal in psr active for FreeSync PSR. 1596 */ 1597 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1598 /** 1599 * Set PSR power option 1600 */ 1601 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1602 }; 1603 1604 enum dmub_cmd_fams_type { 1605 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1606 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1607 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1608 /** 1609 * For SubVP set manual trigger in FW because it 1610 * triggers DRR_UPDATE_PENDING which SubVP relies 1611 * on (for any SubVP cases that use a DRR display) 1612 */ 1613 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1614 }; 1615 1616 /** 1617 * PSR versions. 1618 */ 1619 enum psr_version { 1620 /** 1621 * PSR version 1. 1622 */ 1623 PSR_VERSION_1 = 0, 1624 /** 1625 * Freesync PSR SU. 1626 */ 1627 PSR_VERSION_SU_1 = 1, 1628 /** 1629 * PSR not supported. 1630 */ 1631 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1632 }; 1633 1634 /** 1635 * enum dmub_cmd_mall_type - MALL commands 1636 */ 1637 enum dmub_cmd_mall_type { 1638 /** 1639 * Allows display refresh from MALL. 1640 */ 1641 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1642 /** 1643 * Disallows display refresh from MALL. 1644 */ 1645 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1646 /** 1647 * Cursor copy for MALL. 1648 */ 1649 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1650 /** 1651 * Controls DF requests. 1652 */ 1653 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1654 }; 1655 1656 /** 1657 * PHY Link rate for DP. 1658 */ 1659 enum phy_link_rate { 1660 /** 1661 * not supported. 1662 */ 1663 PHY_RATE_UNKNOWN = 0, 1664 /** 1665 * Rate_1 (RBR) - 1.62 Gbps/Lane 1666 */ 1667 PHY_RATE_162 = 1, 1668 /** 1669 * Rate_2 - 2.16 Gbps/Lane 1670 */ 1671 PHY_RATE_216 = 2, 1672 /** 1673 * Rate_3 - 2.43 Gbps/Lane 1674 */ 1675 PHY_RATE_243 = 3, 1676 /** 1677 * Rate_4 (HBR) - 2.70 Gbps/Lane 1678 */ 1679 PHY_RATE_270 = 4, 1680 /** 1681 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1682 */ 1683 PHY_RATE_324 = 5, 1684 /** 1685 * Rate_6 - 4.32 Gbps/Lane 1686 */ 1687 PHY_RATE_432 = 6, 1688 /** 1689 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1690 */ 1691 PHY_RATE_540 = 7, 1692 /** 1693 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1694 */ 1695 PHY_RATE_810 = 8, 1696 /** 1697 * UHBR10 - 10.0 Gbps/Lane 1698 */ 1699 PHY_RATE_1000 = 9, 1700 /** 1701 * UHBR13.5 - 13.5 Gbps/Lane 1702 */ 1703 PHY_RATE_1350 = 10, 1704 /** 1705 * UHBR10 - 20.0 Gbps/Lane 1706 */ 1707 PHY_RATE_2000 = 11, 1708 }; 1709 1710 /** 1711 * enum dmub_phy_fsm_state - PHY FSM states. 1712 * PHY FSM state to transit to during PSR enable/disable. 1713 */ 1714 enum dmub_phy_fsm_state { 1715 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1716 DMUB_PHY_FSM_RESET, 1717 DMUB_PHY_FSM_RESET_RELEASED, 1718 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1719 DMUB_PHY_FSM_INITIALIZED, 1720 DMUB_PHY_FSM_CALIBRATED, 1721 DMUB_PHY_FSM_CALIBRATED_LP, 1722 DMUB_PHY_FSM_CALIBRATED_PG, 1723 DMUB_PHY_FSM_POWER_DOWN, 1724 DMUB_PHY_FSM_PLL_EN, 1725 DMUB_PHY_FSM_TX_EN, 1726 DMUB_PHY_FSM_FAST_LP, 1727 }; 1728 1729 /** 1730 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1731 */ 1732 struct dmub_cmd_psr_copy_settings_data { 1733 /** 1734 * Flags that can be set by driver to change some PSR behaviour. 1735 */ 1736 union dmub_psr_debug_flags debug; 1737 /** 1738 * 16-bit value dicated by driver that will enable/disable different functionality. 1739 */ 1740 uint16_t psr_level; 1741 /** 1742 * DPP HW instance. 1743 */ 1744 uint8_t dpp_inst; 1745 /** 1746 * MPCC HW instance. 1747 * Not used in dmub fw, 1748 * dmub fw will get active opp by reading odm registers. 1749 */ 1750 uint8_t mpcc_inst; 1751 /** 1752 * OPP HW instance. 1753 * Not used in dmub fw, 1754 * dmub fw will get active opp by reading odm registers. 1755 */ 1756 uint8_t opp_inst; 1757 /** 1758 * OTG HW instance. 1759 */ 1760 uint8_t otg_inst; 1761 /** 1762 * DIG FE HW instance. 1763 */ 1764 uint8_t digfe_inst; 1765 /** 1766 * DIG BE HW instance. 1767 */ 1768 uint8_t digbe_inst; 1769 /** 1770 * DP PHY HW instance. 1771 */ 1772 uint8_t dpphy_inst; 1773 /** 1774 * AUX HW instance. 1775 */ 1776 uint8_t aux_inst; 1777 /** 1778 * Determines if SMU optimzations are enabled/disabled. 1779 */ 1780 uint8_t smu_optimizations_en; 1781 /** 1782 * Unused. 1783 * TODO: Remove. 1784 */ 1785 uint8_t frame_delay; 1786 /** 1787 * If RFB setup time is greater than the total VBLANK time, 1788 * it is not possible for the sink to capture the video frame 1789 * in the same frame the SDP is sent. In this case, 1790 * the frame capture indication bit should be set and an extra 1791 * static frame should be transmitted to the sink. 1792 */ 1793 uint8_t frame_cap_ind; 1794 /** 1795 * Granularity of Y offset supported by sink. 1796 */ 1797 uint8_t su_y_granularity; 1798 /** 1799 * Indicates whether sink should start capturing 1800 * immediately following active scan line, 1801 * or starting with the 2nd active scan line. 1802 */ 1803 uint8_t line_capture_indication; 1804 /** 1805 * Multi-display optimizations are implemented on certain ASICs. 1806 */ 1807 uint8_t multi_disp_optimizations_en; 1808 /** 1809 * The last possible line SDP may be transmitted without violating 1810 * the RFB setup time or entering the active video frame. 1811 */ 1812 uint16_t init_sdp_deadline; 1813 /** 1814 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1815 */ 1816 uint8_t rate_control_caps ; 1817 /* 1818 * Force PSRSU always doing full frame update 1819 */ 1820 uint8_t force_ffu_mode; 1821 /** 1822 * Length of each horizontal line in us. 1823 */ 1824 uint32_t line_time_in_us; 1825 /** 1826 * FEC enable status in driver 1827 */ 1828 uint8_t fec_enable_status; 1829 /** 1830 * FEC re-enable delay when PSR exit. 1831 * unit is 100us, range form 0~255(0xFF). 1832 */ 1833 uint8_t fec_enable_delay_in100us; 1834 /** 1835 * PSR control version. 1836 */ 1837 uint8_t cmd_version; 1838 /** 1839 * Panel Instance. 1840 * Panel isntance to identify which psr_state to use 1841 * Currently the support is only for 0 or 1 1842 */ 1843 uint8_t panel_inst; 1844 /* 1845 * DSC enable status in driver 1846 */ 1847 uint8_t dsc_enable_status; 1848 /* 1849 * Use FSM state for PSR power up/down 1850 */ 1851 uint8_t use_phy_fsm; 1852 /** 1853 * Explicit padding to 2 byte boundary. 1854 */ 1855 uint8_t pad3[2]; 1856 }; 1857 1858 /** 1859 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1860 */ 1861 struct dmub_rb_cmd_psr_copy_settings { 1862 /** 1863 * Command header. 1864 */ 1865 struct dmub_cmd_header header; 1866 /** 1867 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1868 */ 1869 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1870 }; 1871 1872 /** 1873 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1874 */ 1875 struct dmub_cmd_psr_set_level_data { 1876 /** 1877 * 16-bit value dicated by driver that will enable/disable different functionality. 1878 */ 1879 uint16_t psr_level; 1880 /** 1881 * PSR control version. 1882 */ 1883 uint8_t cmd_version; 1884 /** 1885 * Panel Instance. 1886 * Panel isntance to identify which psr_state to use 1887 * Currently the support is only for 0 or 1 1888 */ 1889 uint8_t panel_inst; 1890 }; 1891 1892 /** 1893 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1894 */ 1895 struct dmub_rb_cmd_psr_set_level { 1896 /** 1897 * Command header. 1898 */ 1899 struct dmub_cmd_header header; 1900 /** 1901 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1902 */ 1903 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1904 }; 1905 1906 struct dmub_rb_cmd_psr_enable_data { 1907 /** 1908 * PSR control version. 1909 */ 1910 uint8_t cmd_version; 1911 /** 1912 * Panel Instance. 1913 * Panel isntance to identify which psr_state to use 1914 * Currently the support is only for 0 or 1 1915 */ 1916 uint8_t panel_inst; 1917 /** 1918 * Phy state to enter. 1919 * Values to use are defined in dmub_phy_fsm_state 1920 */ 1921 uint8_t phy_fsm_state; 1922 /** 1923 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1924 * Set this using enum phy_link_rate. 1925 * This does not support HDMI/DP2 for now. 1926 */ 1927 uint8_t phy_rate; 1928 }; 1929 1930 /** 1931 * Definition of a DMUB_CMD__PSR_ENABLE command. 1932 * PSR enable/disable is controlled using the sub_type. 1933 */ 1934 struct dmub_rb_cmd_psr_enable { 1935 /** 1936 * Command header. 1937 */ 1938 struct dmub_cmd_header header; 1939 1940 struct dmub_rb_cmd_psr_enable_data data; 1941 }; 1942 1943 /** 1944 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1945 */ 1946 struct dmub_cmd_psr_set_version_data { 1947 /** 1948 * PSR version that FW should implement. 1949 */ 1950 enum psr_version version; 1951 /** 1952 * PSR control version. 1953 */ 1954 uint8_t cmd_version; 1955 /** 1956 * Panel Instance. 1957 * Panel isntance to identify which psr_state to use 1958 * Currently the support is only for 0 or 1 1959 */ 1960 uint8_t panel_inst; 1961 /** 1962 * Explicit padding to 4 byte boundary. 1963 */ 1964 uint8_t pad[2]; 1965 }; 1966 1967 /** 1968 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1969 */ 1970 struct dmub_rb_cmd_psr_set_version { 1971 /** 1972 * Command header. 1973 */ 1974 struct dmub_cmd_header header; 1975 /** 1976 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1977 */ 1978 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1979 }; 1980 1981 struct dmub_cmd_psr_force_static_data { 1982 /** 1983 * PSR control version. 1984 */ 1985 uint8_t cmd_version; 1986 /** 1987 * Panel Instance. 1988 * Panel isntance to identify which psr_state to use 1989 * Currently the support is only for 0 or 1 1990 */ 1991 uint8_t panel_inst; 1992 /** 1993 * Explicit padding to 4 byte boundary. 1994 */ 1995 uint8_t pad[2]; 1996 }; 1997 1998 /** 1999 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2000 */ 2001 struct dmub_rb_cmd_psr_force_static { 2002 /** 2003 * Command header. 2004 */ 2005 struct dmub_cmd_header header; 2006 /** 2007 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2008 */ 2009 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2010 }; 2011 2012 /** 2013 * PSR SU debug flags. 2014 */ 2015 union dmub_psr_su_debug_flags { 2016 /** 2017 * PSR SU debug flags. 2018 */ 2019 struct { 2020 /** 2021 * Update dirty rect in SW only. 2022 */ 2023 uint8_t update_dirty_rect_only : 1; 2024 /** 2025 * Reset the cursor/plane state before processing the call. 2026 */ 2027 uint8_t reset_state : 1; 2028 } bitfields; 2029 2030 /** 2031 * Union for debug flags. 2032 */ 2033 uint32_t u32All; 2034 }; 2035 2036 /** 2037 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2038 * This triggers a selective update for PSR SU. 2039 */ 2040 struct dmub_cmd_update_dirty_rect_data { 2041 /** 2042 * Dirty rects from OS. 2043 */ 2044 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2045 /** 2046 * PSR SU debug flags. 2047 */ 2048 union dmub_psr_su_debug_flags debug_flags; 2049 /** 2050 * OTG HW instance. 2051 */ 2052 uint8_t pipe_idx; 2053 /** 2054 * Number of dirty rects. 2055 */ 2056 uint8_t dirty_rect_count; 2057 /** 2058 * PSR control version. 2059 */ 2060 uint8_t cmd_version; 2061 /** 2062 * Panel Instance. 2063 * Panel isntance to identify which psr_state to use 2064 * Currently the support is only for 0 or 1 2065 */ 2066 uint8_t panel_inst; 2067 }; 2068 2069 /** 2070 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2071 */ 2072 struct dmub_rb_cmd_update_dirty_rect { 2073 /** 2074 * Command header. 2075 */ 2076 struct dmub_cmd_header header; 2077 /** 2078 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2079 */ 2080 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2081 }; 2082 2083 /** 2084 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2085 */ 2086 struct dmub_cmd_update_cursor_info_data { 2087 /** 2088 * Cursor dirty rects. 2089 */ 2090 struct dmub_rect cursor_rect; 2091 /** 2092 * PSR SU debug flags. 2093 */ 2094 union dmub_psr_su_debug_flags debug_flags; 2095 /** 2096 * Cursor enable/disable. 2097 */ 2098 uint8_t enable; 2099 /** 2100 * OTG HW instance. 2101 */ 2102 uint8_t pipe_idx; 2103 /** 2104 * PSR control version. 2105 */ 2106 uint8_t cmd_version; 2107 /** 2108 * Panel Instance. 2109 * Panel isntance to identify which psr_state to use 2110 * Currently the support is only for 0 or 1 2111 */ 2112 uint8_t panel_inst; 2113 }; 2114 /** 2115 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2116 */ 2117 struct dmub_rb_cmd_update_cursor_info { 2118 /** 2119 * Command header. 2120 */ 2121 struct dmub_cmd_header header; 2122 /** 2123 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2124 */ 2125 struct dmub_cmd_update_cursor_info_data update_cursor_info_data; 2126 }; 2127 2128 /** 2129 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2130 */ 2131 struct dmub_cmd_psr_set_vtotal_data { 2132 /** 2133 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2134 */ 2135 uint16_t psr_vtotal_idle; 2136 /** 2137 * PSR control version. 2138 */ 2139 uint8_t cmd_version; 2140 /** 2141 * Panel Instance. 2142 * Panel isntance to identify which psr_state to use 2143 * Currently the support is only for 0 or 1 2144 */ 2145 uint8_t panel_inst; 2146 /* 2147 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2148 */ 2149 uint16_t psr_vtotal_su; 2150 /** 2151 * Explicit padding to 4 byte boundary. 2152 */ 2153 uint8_t pad2[2]; 2154 }; 2155 2156 /** 2157 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2158 */ 2159 struct dmub_rb_cmd_psr_set_vtotal { 2160 /** 2161 * Command header. 2162 */ 2163 struct dmub_cmd_header header; 2164 /** 2165 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2166 */ 2167 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2168 }; 2169 2170 /** 2171 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2172 */ 2173 struct dmub_cmd_psr_set_power_opt_data { 2174 /** 2175 * PSR control version. 2176 */ 2177 uint8_t cmd_version; 2178 /** 2179 * Panel Instance. 2180 * Panel isntance to identify which psr_state to use 2181 * Currently the support is only for 0 or 1 2182 */ 2183 uint8_t panel_inst; 2184 /** 2185 * Explicit padding to 4 byte boundary. 2186 */ 2187 uint8_t pad[2]; 2188 /** 2189 * PSR power option 2190 */ 2191 uint32_t power_opt; 2192 }; 2193 2194 /** 2195 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2196 */ 2197 struct dmub_rb_cmd_psr_set_power_opt { 2198 /** 2199 * Command header. 2200 */ 2201 struct dmub_cmd_header header; 2202 /** 2203 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2204 */ 2205 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2206 }; 2207 2208 /** 2209 * Set of HW components that can be locked. 2210 * 2211 * Note: If updating with more HW components, fields 2212 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2213 */ 2214 union dmub_hw_lock_flags { 2215 /** 2216 * Set of HW components that can be locked. 2217 */ 2218 struct { 2219 /** 2220 * Lock/unlock OTG master update lock. 2221 */ 2222 uint8_t lock_pipe : 1; 2223 /** 2224 * Lock/unlock cursor. 2225 */ 2226 uint8_t lock_cursor : 1; 2227 /** 2228 * Lock/unlock global update lock. 2229 */ 2230 uint8_t lock_dig : 1; 2231 /** 2232 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2233 */ 2234 uint8_t triple_buffer_lock : 1; 2235 } bits; 2236 2237 /** 2238 * Union for HW Lock flags. 2239 */ 2240 uint8_t u8All; 2241 }; 2242 2243 /** 2244 * Instances of HW to be locked. 2245 * 2246 * Note: If updating with more HW components, fields 2247 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2248 */ 2249 struct dmub_hw_lock_inst_flags { 2250 /** 2251 * OTG HW instance for OTG master update lock. 2252 */ 2253 uint8_t otg_inst; 2254 /** 2255 * OPP instance for cursor lock. 2256 */ 2257 uint8_t opp_inst; 2258 /** 2259 * OTG HW instance for global update lock. 2260 * TODO: Remove, and re-use otg_inst. 2261 */ 2262 uint8_t dig_inst; 2263 /** 2264 * Explicit pad to 4 byte boundary. 2265 */ 2266 uint8_t pad; 2267 }; 2268 2269 /** 2270 * Clients that can acquire the HW Lock Manager. 2271 * 2272 * Note: If updating with more clients, fields in 2273 * dmub_inbox0_cmd_lock_hw must be updated to match. 2274 */ 2275 enum hw_lock_client { 2276 /** 2277 * Driver is the client of HW Lock Manager. 2278 */ 2279 HW_LOCK_CLIENT_DRIVER = 0, 2280 /** 2281 * PSR SU is the client of HW Lock Manager. 2282 */ 2283 HW_LOCK_CLIENT_PSR_SU = 1, 2284 /** 2285 * Invalid client. 2286 */ 2287 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2288 }; 2289 2290 /** 2291 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2292 */ 2293 struct dmub_cmd_lock_hw_data { 2294 /** 2295 * Specifies the client accessing HW Lock Manager. 2296 */ 2297 enum hw_lock_client client; 2298 /** 2299 * HW instances to be locked. 2300 */ 2301 struct dmub_hw_lock_inst_flags inst_flags; 2302 /** 2303 * Which components to be locked. 2304 */ 2305 union dmub_hw_lock_flags hw_locks; 2306 /** 2307 * Specifies lock/unlock. 2308 */ 2309 uint8_t lock; 2310 /** 2311 * HW can be unlocked separately from releasing the HW Lock Mgr. 2312 * This flag is set if the client wishes to release the object. 2313 */ 2314 uint8_t should_release; 2315 /** 2316 * Explicit padding to 4 byte boundary. 2317 */ 2318 uint8_t pad; 2319 }; 2320 2321 /** 2322 * Definition of a DMUB_CMD__HW_LOCK command. 2323 * Command is used by driver and FW. 2324 */ 2325 struct dmub_rb_cmd_lock_hw { 2326 /** 2327 * Command header. 2328 */ 2329 struct dmub_cmd_header header; 2330 /** 2331 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2332 */ 2333 struct dmub_cmd_lock_hw_data lock_hw_data; 2334 }; 2335 2336 /** 2337 * ABM command sub-types. 2338 */ 2339 enum dmub_cmd_abm_type { 2340 /** 2341 * Initialize parameters for ABM algorithm. 2342 * Data is passed through an indirect buffer. 2343 */ 2344 DMUB_CMD__ABM_INIT_CONFIG = 0, 2345 /** 2346 * Set OTG and panel HW instance. 2347 */ 2348 DMUB_CMD__ABM_SET_PIPE = 1, 2349 /** 2350 * Set user requested backklight level. 2351 */ 2352 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2353 /** 2354 * Set ABM operating/aggression level. 2355 */ 2356 DMUB_CMD__ABM_SET_LEVEL = 3, 2357 /** 2358 * Set ambient light level. 2359 */ 2360 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2361 /** 2362 * Enable/disable fractional duty cycle for backlight PWM. 2363 */ 2364 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2365 2366 /** 2367 * unregister vertical interrupt after steady state is reached 2368 */ 2369 DMUB_CMD__ABM_PAUSE = 6, 2370 }; 2371 2372 /** 2373 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2374 * Requirements: 2375 * - Padded explicitly to 32-bit boundary. 2376 * - Must ensure this structure matches the one on driver-side, 2377 * otherwise it won't be aligned. 2378 */ 2379 struct abm_config_table { 2380 /** 2381 * Gamma curve thresholds, used for crgb conversion. 2382 */ 2383 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2384 /** 2385 * Gamma curve offsets, used for crgb conversion. 2386 */ 2387 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2388 /** 2389 * Gamma curve slopes, used for crgb conversion. 2390 */ 2391 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2392 /** 2393 * Custom backlight curve thresholds. 2394 */ 2395 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2396 /** 2397 * Custom backlight curve offsets. 2398 */ 2399 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2400 /** 2401 * Ambient light thresholds. 2402 */ 2403 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2404 /** 2405 * Minimum programmable backlight. 2406 */ 2407 uint16_t min_abm_backlight; // 122B 2408 /** 2409 * Minimum reduction values. 2410 */ 2411 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2412 /** 2413 * Maximum reduction values. 2414 */ 2415 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2416 /** 2417 * Bright positive gain. 2418 */ 2419 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2420 /** 2421 * Dark negative gain. 2422 */ 2423 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2424 /** 2425 * Hybrid factor. 2426 */ 2427 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2428 /** 2429 * Contrast factor. 2430 */ 2431 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2432 /** 2433 * Deviation gain. 2434 */ 2435 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2436 /** 2437 * Minimum knee. 2438 */ 2439 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2440 /** 2441 * Maximum knee. 2442 */ 2443 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2444 /** 2445 * Unused. 2446 */ 2447 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2448 /** 2449 * Explicit padding to 4 byte boundary. 2450 */ 2451 uint8_t pad3[3]; // 229B 2452 /** 2453 * Backlight ramp reduction. 2454 */ 2455 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2456 /** 2457 * Backlight ramp start. 2458 */ 2459 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2460 }; 2461 2462 /** 2463 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2464 */ 2465 struct dmub_cmd_abm_set_pipe_data { 2466 /** 2467 * OTG HW instance. 2468 */ 2469 uint8_t otg_inst; 2470 2471 /** 2472 * Panel Control HW instance. 2473 */ 2474 uint8_t panel_inst; 2475 2476 /** 2477 * Controls how ABM will interpret a set pipe or set level command. 2478 */ 2479 uint8_t set_pipe_option; 2480 2481 /** 2482 * Unused. 2483 * TODO: Remove. 2484 */ 2485 uint8_t ramping_boundary; 2486 }; 2487 2488 /** 2489 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2490 */ 2491 struct dmub_rb_cmd_abm_set_pipe { 2492 /** 2493 * Command header. 2494 */ 2495 struct dmub_cmd_header header; 2496 2497 /** 2498 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2499 */ 2500 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2501 }; 2502 2503 /** 2504 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2505 */ 2506 struct dmub_cmd_abm_set_backlight_data { 2507 /** 2508 * Number of frames to ramp to backlight user level. 2509 */ 2510 uint32_t frame_ramp; 2511 2512 /** 2513 * Requested backlight level from user. 2514 */ 2515 uint32_t backlight_user_level; 2516 2517 /** 2518 * ABM control version. 2519 */ 2520 uint8_t version; 2521 2522 /** 2523 * Panel Control HW instance mask. 2524 * Bit 0 is Panel Control HW instance 0. 2525 * Bit 1 is Panel Control HW instance 1. 2526 */ 2527 uint8_t panel_mask; 2528 2529 /** 2530 * Explicit padding to 4 byte boundary. 2531 */ 2532 uint8_t pad[2]; 2533 }; 2534 2535 /** 2536 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2537 */ 2538 struct dmub_rb_cmd_abm_set_backlight { 2539 /** 2540 * Command header. 2541 */ 2542 struct dmub_cmd_header header; 2543 2544 /** 2545 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2546 */ 2547 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2548 }; 2549 2550 /** 2551 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2552 */ 2553 struct dmub_cmd_abm_set_level_data { 2554 /** 2555 * Set current ABM operating/aggression level. 2556 */ 2557 uint32_t level; 2558 2559 /** 2560 * ABM control version. 2561 */ 2562 uint8_t version; 2563 2564 /** 2565 * Panel Control HW instance mask. 2566 * Bit 0 is Panel Control HW instance 0. 2567 * Bit 1 is Panel Control HW instance 1. 2568 */ 2569 uint8_t panel_mask; 2570 2571 /** 2572 * Explicit padding to 4 byte boundary. 2573 */ 2574 uint8_t pad[2]; 2575 }; 2576 2577 /** 2578 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2579 */ 2580 struct dmub_rb_cmd_abm_set_level { 2581 /** 2582 * Command header. 2583 */ 2584 struct dmub_cmd_header header; 2585 2586 /** 2587 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2588 */ 2589 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2590 }; 2591 2592 /** 2593 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2594 */ 2595 struct dmub_cmd_abm_set_ambient_level_data { 2596 /** 2597 * Ambient light sensor reading from OS. 2598 */ 2599 uint32_t ambient_lux; 2600 2601 /** 2602 * ABM control version. 2603 */ 2604 uint8_t version; 2605 2606 /** 2607 * Panel Control HW instance mask. 2608 * Bit 0 is Panel Control HW instance 0. 2609 * Bit 1 is Panel Control HW instance 1. 2610 */ 2611 uint8_t panel_mask; 2612 2613 /** 2614 * Explicit padding to 4 byte boundary. 2615 */ 2616 uint8_t pad[2]; 2617 }; 2618 2619 /** 2620 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2621 */ 2622 struct dmub_rb_cmd_abm_set_ambient_level { 2623 /** 2624 * Command header. 2625 */ 2626 struct dmub_cmd_header header; 2627 2628 /** 2629 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2630 */ 2631 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2632 }; 2633 2634 /** 2635 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2636 */ 2637 struct dmub_cmd_abm_set_pwm_frac_data { 2638 /** 2639 * Enable/disable fractional duty cycle for backlight PWM. 2640 * TODO: Convert to uint8_t. 2641 */ 2642 uint32_t fractional_pwm; 2643 2644 /** 2645 * ABM control version. 2646 */ 2647 uint8_t version; 2648 2649 /** 2650 * Panel Control HW instance mask. 2651 * Bit 0 is Panel Control HW instance 0. 2652 * Bit 1 is Panel Control HW instance 1. 2653 */ 2654 uint8_t panel_mask; 2655 2656 /** 2657 * Explicit padding to 4 byte boundary. 2658 */ 2659 uint8_t pad[2]; 2660 }; 2661 2662 /** 2663 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2664 */ 2665 struct dmub_rb_cmd_abm_set_pwm_frac { 2666 /** 2667 * Command header. 2668 */ 2669 struct dmub_cmd_header header; 2670 2671 /** 2672 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2673 */ 2674 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2675 }; 2676 2677 /** 2678 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2679 */ 2680 struct dmub_cmd_abm_init_config_data { 2681 /** 2682 * Location of indirect buffer used to pass init data to ABM. 2683 */ 2684 union dmub_addr src; 2685 2686 /** 2687 * Indirect buffer length. 2688 */ 2689 uint16_t bytes; 2690 2691 2692 /** 2693 * ABM control version. 2694 */ 2695 uint8_t version; 2696 2697 /** 2698 * Panel Control HW instance mask. 2699 * Bit 0 is Panel Control HW instance 0. 2700 * Bit 1 is Panel Control HW instance 1. 2701 */ 2702 uint8_t panel_mask; 2703 2704 /** 2705 * Explicit padding to 4 byte boundary. 2706 */ 2707 uint8_t pad[2]; 2708 }; 2709 2710 /** 2711 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2712 */ 2713 struct dmub_rb_cmd_abm_init_config { 2714 /** 2715 * Command header. 2716 */ 2717 struct dmub_cmd_header header; 2718 2719 /** 2720 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2721 */ 2722 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2723 }; 2724 2725 /** 2726 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2727 */ 2728 2729 struct dmub_cmd_abm_pause_data { 2730 2731 /** 2732 * Panel Control HW instance mask. 2733 * Bit 0 is Panel Control HW instance 0. 2734 * Bit 1 is Panel Control HW instance 1. 2735 */ 2736 uint8_t panel_mask; 2737 2738 /** 2739 * OTG hw instance 2740 */ 2741 uint8_t otg_inst; 2742 2743 /** 2744 * Enable or disable ABM pause 2745 */ 2746 uint8_t enable; 2747 2748 /** 2749 * Explicit padding to 4 byte boundary. 2750 */ 2751 uint8_t pad[1]; 2752 }; 2753 2754 /** 2755 * Definition of a DMUB_CMD__ABM_PAUSE command. 2756 */ 2757 struct dmub_rb_cmd_abm_pause { 2758 /** 2759 * Command header. 2760 */ 2761 struct dmub_cmd_header header; 2762 2763 /** 2764 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2765 */ 2766 struct dmub_cmd_abm_pause_data abm_pause_data; 2767 }; 2768 2769 /** 2770 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2771 */ 2772 struct dmub_cmd_query_feature_caps_data { 2773 /** 2774 * DMUB feature capabilities. 2775 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2776 */ 2777 struct dmub_feature_caps feature_caps; 2778 }; 2779 2780 /** 2781 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2782 */ 2783 struct dmub_rb_cmd_query_feature_caps { 2784 /** 2785 * Command header. 2786 */ 2787 struct dmub_cmd_header header; 2788 /** 2789 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2790 */ 2791 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2792 }; 2793 2794 /** 2795 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2796 */ 2797 struct dmub_cmd_visual_confirm_color_data { 2798 /** 2799 * DMUB feature capabilities. 2800 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2801 */ 2802 struct dmub_visual_confirm_color visual_confirm_color; 2803 }; 2804 2805 /** 2806 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2807 */ 2808 struct dmub_rb_cmd_get_visual_confirm_color { 2809 /** 2810 * Command header. 2811 */ 2812 struct dmub_cmd_header header; 2813 /** 2814 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2815 */ 2816 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2817 }; 2818 2819 struct dmub_optc_state { 2820 uint32_t v_total_max; 2821 uint32_t v_total_min; 2822 uint32_t v_total_mid; 2823 uint32_t v_total_mid_frame_num; 2824 uint32_t tg_inst; 2825 uint32_t enable_manual_trigger; 2826 uint32_t clear_force_vsync; 2827 }; 2828 2829 struct dmub_rb_cmd_drr_update { 2830 struct dmub_cmd_header header; 2831 struct dmub_optc_state dmub_optc_state_req; 2832 }; 2833 2834 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2835 uint32_t pix_clk_100hz; 2836 uint8_t max_ramp_step; 2837 uint8_t pipes; 2838 uint8_t min_refresh_in_hz; 2839 uint8_t padding[1]; 2840 }; 2841 2842 struct dmub_cmd_fw_assisted_mclk_switch_config { 2843 uint8_t fams_enabled; 2844 uint8_t visual_confirm_enabled; 2845 uint8_t padding[2]; 2846 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2847 }; 2848 2849 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2850 struct dmub_cmd_header header; 2851 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2852 }; 2853 2854 /** 2855 * enum dmub_cmd_panel_cntl_type - Panel control command. 2856 */ 2857 enum dmub_cmd_panel_cntl_type { 2858 /** 2859 * Initializes embedded panel hardware blocks. 2860 */ 2861 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2862 /** 2863 * Queries backlight info for the embedded panel. 2864 */ 2865 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2866 }; 2867 2868 /** 2869 * struct dmub_cmd_panel_cntl_data - Panel control data. 2870 */ 2871 struct dmub_cmd_panel_cntl_data { 2872 uint32_t inst; /**< panel instance */ 2873 uint32_t current_backlight; /* in/out */ 2874 uint32_t bl_pwm_cntl; /* in/out */ 2875 uint32_t bl_pwm_period_cntl; /* in/out */ 2876 uint32_t bl_pwm_ref_div1; /* in/out */ 2877 uint8_t is_backlight_on : 1; /* in/out */ 2878 uint8_t is_powered_on : 1; /* in/out */ 2879 uint8_t padding[3]; 2880 uint32_t bl_pwm_ref_div2; /* in/out */ 2881 uint8_t reserved[4]; 2882 }; 2883 2884 /** 2885 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2886 */ 2887 struct dmub_rb_cmd_panel_cntl { 2888 struct dmub_cmd_header header; /**< header */ 2889 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2890 }; 2891 2892 /** 2893 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2894 */ 2895 struct dmub_cmd_lvtma_control_data { 2896 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2897 uint8_t reserved_0[3]; /**< For future use */ 2898 uint8_t panel_inst; /**< LVTMA control instance */ 2899 uint8_t reserved_1[3]; /**< For future use */ 2900 }; 2901 2902 /** 2903 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2904 */ 2905 struct dmub_rb_cmd_lvtma_control { 2906 /** 2907 * Command header. 2908 */ 2909 struct dmub_cmd_header header; 2910 /** 2911 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2912 */ 2913 struct dmub_cmd_lvtma_control_data data; 2914 }; 2915 2916 /** 2917 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2918 */ 2919 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2920 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2921 uint8_t is_usb; /**< is phy is usb */ 2922 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2923 uint8_t is_dp4; /**< is dp in 4 lane */ 2924 }; 2925 2926 /** 2927 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2928 */ 2929 struct dmub_rb_cmd_transmitter_query_dp_alt { 2930 struct dmub_cmd_header header; /**< header */ 2931 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2932 }; 2933 2934 /** 2935 * Maximum number of bytes a chunk sent to DMUB for parsing 2936 */ 2937 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2938 2939 /** 2940 * Represent a chunk of CEA blocks sent to DMUB for parsing 2941 */ 2942 struct dmub_cmd_send_edid_cea { 2943 uint16_t offset; /**< offset into the CEA block */ 2944 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2945 uint16_t cea_total_length; /**< total length of the CEA block */ 2946 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2947 uint8_t pad[3]; /**< padding and for future expansion */ 2948 }; 2949 2950 /** 2951 * Result of VSDB parsing from CEA block 2952 */ 2953 struct dmub_cmd_edid_cea_amd_vsdb { 2954 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2955 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2956 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2957 uint16_t min_frame_rate; /**< Maximum frame rate */ 2958 uint16_t max_frame_rate; /**< Minimum frame rate */ 2959 }; 2960 2961 /** 2962 * Result of sending a CEA chunk 2963 */ 2964 struct dmub_cmd_edid_cea_ack { 2965 uint16_t offset; /**< offset of the chunk into the CEA block */ 2966 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2967 uint8_t pad; /**< padding and for future expansion */ 2968 }; 2969 2970 /** 2971 * Specify whether the result is an ACK/NACK or the parsing has finished 2972 */ 2973 enum dmub_cmd_edid_cea_reply_type { 2974 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2975 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2976 }; 2977 2978 /** 2979 * Definition of a DMUB_CMD__EDID_CEA command. 2980 */ 2981 struct dmub_rb_cmd_edid_cea { 2982 struct dmub_cmd_header header; /**< Command header */ 2983 union dmub_cmd_edid_cea_data { 2984 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2985 struct dmub_cmd_edid_cea_output { /**< output with results */ 2986 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2987 union { 2988 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2989 struct dmub_cmd_edid_cea_ack ack; 2990 }; 2991 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2992 } data; /**< Command data */ 2993 2994 }; 2995 2996 /** 2997 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2998 */ 2999 struct dmub_cmd_cable_id_input { 3000 uint8_t phy_inst; /**< phy inst for cable id data */ 3001 }; 3002 3003 /** 3004 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3005 */ 3006 struct dmub_cmd_cable_id_output { 3007 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3008 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3009 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3010 uint8_t RESERVED :2; /**< reserved means not defined */ 3011 }; 3012 3013 /** 3014 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3015 */ 3016 struct dmub_rb_cmd_get_usbc_cable_id { 3017 struct dmub_cmd_header header; /**< Command header */ 3018 /** 3019 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3020 */ 3021 union dmub_cmd_cable_id_data { 3022 struct dmub_cmd_cable_id_input input; /**< Input */ 3023 struct dmub_cmd_cable_id_output output; /**< Output */ 3024 uint8_t output_raw; /**< Raw data output */ 3025 } data; 3026 }; 3027 3028 /** 3029 * union dmub_rb_cmd - DMUB inbox command. 3030 */ 3031 union dmub_rb_cmd { 3032 /** 3033 * Elements shared with all commands. 3034 */ 3035 struct dmub_rb_cmd_common cmd_common; 3036 /** 3037 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3038 */ 3039 struct dmub_rb_cmd_read_modify_write read_modify_write; 3040 /** 3041 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3042 */ 3043 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3044 /** 3045 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3046 */ 3047 struct dmub_rb_cmd_burst_write burst_write; 3048 /** 3049 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3050 */ 3051 struct dmub_rb_cmd_reg_wait reg_wait; 3052 /** 3053 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3054 */ 3055 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3056 /** 3057 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3058 */ 3059 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3060 /** 3061 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3062 */ 3063 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3064 /** 3065 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3066 */ 3067 struct dmub_rb_cmd_dpphy_init dpphy_init; 3068 /** 3069 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3070 */ 3071 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3072 /** 3073 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3074 */ 3075 struct dmub_rb_cmd_psr_set_version psr_set_version; 3076 /** 3077 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3078 */ 3079 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3080 /** 3081 * Definition of a DMUB_CMD__PSR_ENABLE command. 3082 */ 3083 struct dmub_rb_cmd_psr_enable psr_enable; 3084 /** 3085 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3086 */ 3087 struct dmub_rb_cmd_psr_set_level psr_set_level; 3088 /** 3089 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3090 */ 3091 struct dmub_rb_cmd_psr_force_static psr_force_static; 3092 /** 3093 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3094 */ 3095 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3096 /** 3097 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3098 */ 3099 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3100 /** 3101 * Definition of a DMUB_CMD__HW_LOCK command. 3102 * Command is used by driver and FW. 3103 */ 3104 struct dmub_rb_cmd_lock_hw lock_hw; 3105 /** 3106 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3107 */ 3108 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3109 /** 3110 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3111 */ 3112 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3113 /** 3114 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3115 */ 3116 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3117 /** 3118 * Definition of a DMUB_CMD__MALL command. 3119 */ 3120 struct dmub_rb_cmd_mall mall; 3121 /** 3122 * Definition of a DMUB_CMD__CAB command. 3123 */ 3124 struct dmub_rb_cmd_cab_for_ss cab; 3125 3126 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3127 3128 /** 3129 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3130 */ 3131 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3132 3133 /** 3134 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3135 */ 3136 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3137 3138 /** 3139 * Definition of DMUB_CMD__PANEL_CNTL commands. 3140 */ 3141 struct dmub_rb_cmd_panel_cntl panel_cntl; 3142 /** 3143 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3144 */ 3145 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3146 3147 /** 3148 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3149 */ 3150 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3151 3152 /** 3153 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3154 */ 3155 struct dmub_rb_cmd_abm_set_level abm_set_level; 3156 3157 /** 3158 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3159 */ 3160 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3161 3162 /** 3163 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3164 */ 3165 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3166 3167 /** 3168 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3169 */ 3170 struct dmub_rb_cmd_abm_init_config abm_init_config; 3171 3172 /** 3173 * Definition of a DMUB_CMD__ABM_PAUSE command. 3174 */ 3175 struct dmub_rb_cmd_abm_pause abm_pause; 3176 3177 /** 3178 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3179 */ 3180 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3181 3182 /** 3183 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3184 */ 3185 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3186 3187 /** 3188 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3189 */ 3190 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3191 3192 /** 3193 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3194 */ 3195 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3196 struct dmub_rb_cmd_drr_update drr_update; 3197 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3198 3199 /** 3200 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3201 */ 3202 struct dmub_rb_cmd_lvtma_control lvtma_control; 3203 /** 3204 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3205 */ 3206 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3207 /** 3208 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3209 */ 3210 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3211 /** 3212 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3213 */ 3214 struct dmub_rb_cmd_set_config_access set_config_access; 3215 /** 3216 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3217 */ 3218 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3219 /** 3220 * Definition of a DMUB_CMD__EDID_CEA command. 3221 */ 3222 struct dmub_rb_cmd_edid_cea edid_cea; 3223 /** 3224 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3225 */ 3226 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3227 3228 /** 3229 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3230 */ 3231 struct dmub_rb_cmd_query_hpd_state query_hpd; 3232 }; 3233 3234 /** 3235 * union dmub_rb_out_cmd - Outbox command 3236 */ 3237 union dmub_rb_out_cmd { 3238 /** 3239 * Parameters common to every command. 3240 */ 3241 struct dmub_rb_cmd_common cmd_common; 3242 /** 3243 * AUX reply command. 3244 */ 3245 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3246 /** 3247 * HPD notify command. 3248 */ 3249 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3250 /** 3251 * SET_CONFIG reply command. 3252 */ 3253 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3254 }; 3255 #pragma pack(pop) 3256 3257 3258 //============================================================================== 3259 //</DMUB_CMD>=================================================================== 3260 //============================================================================== 3261 //< DMUB_RB>==================================================================== 3262 //============================================================================== 3263 3264 #if defined(__cplusplus) 3265 extern "C" { 3266 #endif 3267 3268 /** 3269 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3270 */ 3271 struct dmub_rb_init_params { 3272 void *ctx; /**< Caller provided context pointer */ 3273 void *base_address; /**< CPU base address for ring's data */ 3274 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3275 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3276 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3277 }; 3278 3279 /** 3280 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3281 */ 3282 struct dmub_rb { 3283 void *base_address; /**< CPU address for the ring's data */ 3284 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3285 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3286 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3287 3288 void *ctx; /**< Caller provided context pointer */ 3289 void *dmub; /**< Pointer to the DMUB interface */ 3290 }; 3291 3292 /** 3293 * @brief Checks if the ringbuffer is empty. 3294 * 3295 * @param rb DMUB Ringbuffer 3296 * @return true if empty 3297 * @return false otherwise 3298 */ 3299 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3300 { 3301 return (rb->wrpt == rb->rptr); 3302 } 3303 3304 /** 3305 * @brief Checks if the ringbuffer is full 3306 * 3307 * @param rb DMUB Ringbuffer 3308 * @return true if full 3309 * @return false otherwise 3310 */ 3311 static inline bool dmub_rb_full(struct dmub_rb *rb) 3312 { 3313 uint32_t data_count; 3314 3315 if (rb->wrpt >= rb->rptr) 3316 data_count = rb->wrpt - rb->rptr; 3317 else 3318 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3319 3320 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3321 } 3322 3323 /** 3324 * @brief Pushes a command into the ringbuffer 3325 * 3326 * @param rb DMUB ringbuffer 3327 * @param cmd The command to push 3328 * @return true if the ringbuffer was not full 3329 * @return false otherwise 3330 */ 3331 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3332 const union dmub_rb_cmd *cmd) 3333 { 3334 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3335 const uint64_t *src = (const uint64_t *)cmd; 3336 uint8_t i; 3337 3338 if (dmub_rb_full(rb)) 3339 return false; 3340 3341 // copying data 3342 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3343 *dst++ = *src++; 3344 3345 rb->wrpt += DMUB_RB_CMD_SIZE; 3346 3347 if (rb->wrpt >= rb->capacity) 3348 rb->wrpt %= rb->capacity; 3349 3350 return true; 3351 } 3352 3353 /** 3354 * @brief Pushes a command into the DMUB outbox ringbuffer 3355 * 3356 * @param rb DMUB outbox ringbuffer 3357 * @param cmd Outbox command 3358 * @return true if not full 3359 * @return false otherwise 3360 */ 3361 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3362 const union dmub_rb_out_cmd *cmd) 3363 { 3364 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3365 const uint8_t *src = (const uint8_t *)cmd; 3366 3367 if (dmub_rb_full(rb)) 3368 return false; 3369 3370 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3371 3372 rb->wrpt += DMUB_RB_CMD_SIZE; 3373 3374 if (rb->wrpt >= rb->capacity) 3375 rb->wrpt %= rb->capacity; 3376 3377 return true; 3378 } 3379 3380 /** 3381 * @brief Returns the next unprocessed command in the ringbuffer. 3382 * 3383 * @param rb DMUB ringbuffer 3384 * @param cmd The command to return 3385 * @return true if not empty 3386 * @return false otherwise 3387 */ 3388 static inline bool dmub_rb_front(struct dmub_rb *rb, 3389 union dmub_rb_cmd **cmd) 3390 { 3391 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3392 3393 if (dmub_rb_empty(rb)) 3394 return false; 3395 3396 *cmd = (union dmub_rb_cmd *)rb_cmd; 3397 3398 return true; 3399 } 3400 3401 /** 3402 * @brief Determines the next ringbuffer offset. 3403 * 3404 * @param rb DMUB inbox ringbuffer 3405 * @param num_cmds Number of commands 3406 * @param next_rptr The next offset in the ringbuffer 3407 */ 3408 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3409 uint32_t num_cmds, 3410 uint32_t *next_rptr) 3411 { 3412 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3413 3414 if (*next_rptr >= rb->capacity) 3415 *next_rptr %= rb->capacity; 3416 } 3417 3418 /** 3419 * @brief Returns a pointer to a command in the inbox. 3420 * 3421 * @param rb DMUB inbox ringbuffer 3422 * @param cmd The inbox command to return 3423 * @param rptr The ringbuffer offset 3424 * @return true if not empty 3425 * @return false otherwise 3426 */ 3427 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3428 union dmub_rb_cmd **cmd, 3429 uint32_t rptr) 3430 { 3431 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3432 3433 if (dmub_rb_empty(rb)) 3434 return false; 3435 3436 *cmd = (union dmub_rb_cmd *)rb_cmd; 3437 3438 return true; 3439 } 3440 3441 /** 3442 * @brief Returns the next unprocessed command in the outbox. 3443 * 3444 * @param rb DMUB outbox ringbuffer 3445 * @param cmd The outbox command to return 3446 * @return true if not empty 3447 * @return false otherwise 3448 */ 3449 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3450 union dmub_rb_out_cmd *cmd) 3451 { 3452 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3453 uint64_t *dst = (uint64_t *)cmd; 3454 uint8_t i; 3455 3456 if (dmub_rb_empty(rb)) 3457 return false; 3458 3459 // copying data 3460 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3461 *dst++ = *src++; 3462 3463 return true; 3464 } 3465 3466 /** 3467 * @brief Removes the front entry in the ringbuffer. 3468 * 3469 * @param rb DMUB ringbuffer 3470 * @return true if the command was removed 3471 * @return false if there were no commands 3472 */ 3473 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3474 { 3475 if (dmub_rb_empty(rb)) 3476 return false; 3477 3478 rb->rptr += DMUB_RB_CMD_SIZE; 3479 3480 if (rb->rptr >= rb->capacity) 3481 rb->rptr %= rb->capacity; 3482 3483 return true; 3484 } 3485 3486 /** 3487 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3488 * 3489 * Avoids a race condition where DMCUB accesses memory while 3490 * there are still writes in flight to framebuffer. 3491 * 3492 * @param rb DMUB ringbuffer 3493 */ 3494 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3495 { 3496 uint32_t rptr = rb->rptr; 3497 uint32_t wptr = rb->wrpt; 3498 3499 while (rptr != wptr) { 3500 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3501 uint8_t i; 3502 3503 /* Don't remove this. 3504 * The contents need to actually be read from the ring buffer 3505 * for this function to be effective. 3506 */ 3507 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3508 (void)READ_ONCE(*data++); 3509 3510 rptr += DMUB_RB_CMD_SIZE; 3511 if (rptr >= rb->capacity) 3512 rptr %= rb->capacity; 3513 } 3514 } 3515 3516 /** 3517 * @brief Initializes a DMCUB ringbuffer 3518 * 3519 * @param rb DMUB ringbuffer 3520 * @param init_params initial configuration for the ringbuffer 3521 */ 3522 static inline void dmub_rb_init(struct dmub_rb *rb, 3523 struct dmub_rb_init_params *init_params) 3524 { 3525 rb->base_address = init_params->base_address; 3526 rb->capacity = init_params->capacity; 3527 rb->rptr = init_params->read_ptr; 3528 rb->wrpt = init_params->write_ptr; 3529 } 3530 3531 /** 3532 * @brief Copies output data from in/out commands into the given command. 3533 * 3534 * @param rb DMUB ringbuffer 3535 * @param cmd Command to copy data into 3536 */ 3537 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3538 union dmub_rb_cmd *cmd) 3539 { 3540 // Copy rb entry back into command 3541 uint8_t *rd_ptr = (rb->rptr == 0) ? 3542 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3543 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3544 3545 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3546 } 3547 3548 #if defined(__cplusplus) 3549 } 3550 #endif 3551 3552 //============================================================================== 3553 //</DMUB_RB>==================================================================== 3554 //============================================================================== 3555 3556 #endif /* _DMUB_CMD_H_ */ 3557