1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 /** 174 * union dmub_addr - DMUB physical/virtual 64-bit address. 175 */ 176 union dmub_addr { 177 struct { 178 uint32_t low_part; /**< Lower 32 bits */ 179 uint32_t high_part; /**< Upper 32 bits */ 180 } u; /*<< Low/high bit access */ 181 uint64_t quad_part; /*<< 64 bit address */ 182 }; 183 #pragma pack(pop) 184 185 /** 186 * Dirty rect definition. 187 */ 188 struct dmub_rect { 189 /** 190 * Dirty rect x offset. 191 */ 192 uint32_t x; 193 194 /** 195 * Dirty rect y offset. 196 */ 197 uint32_t y; 198 199 /** 200 * Dirty rect width. 201 */ 202 uint32_t width; 203 204 /** 205 * Dirty rect height. 206 */ 207 uint32_t height; 208 }; 209 210 /** 211 * Flags that can be set by driver to change some PSR behaviour. 212 */ 213 union dmub_psr_debug_flags { 214 /** 215 * Debug flags. 216 */ 217 struct { 218 /** 219 * Enable visual confirm in FW. 220 */ 221 uint32_t visual_confirm : 1; 222 223 /** 224 * Force all selective updates to bw full frame updates. 225 */ 226 uint32_t force_full_frame_update : 1; 227 228 /** 229 * Use HW Lock Mgr object to do HW locking in FW. 230 */ 231 uint32_t use_hw_lock_mgr : 1; 232 233 /** 234 * Use TPS3 signal when restore main link. 235 */ 236 uint32_t force_wakeup_by_tps3 : 1; 237 238 /** 239 * Back to back flip, therefore cannot power down PHY 240 */ 241 uint32_t back_to_back_flip : 1; 242 243 } bitfields; 244 245 /** 246 * Union for debug flags. 247 */ 248 uint32_t u32All; 249 }; 250 251 /** 252 * DMUB visual confirm color 253 */ 254 struct dmub_feature_caps { 255 /** 256 * Max PSR version supported by FW. 257 */ 258 uint8_t psr; 259 uint8_t fw_assisted_mclk_switch; 260 uint8_t reserved[4]; 261 uint8_t subvp_psr_support; 262 uint8_t gecc_enable; 263 }; 264 265 struct dmub_visual_confirm_color { 266 /** 267 * Maximum 10 bits color value 268 */ 269 uint16_t color_r_cr; 270 uint16_t color_g_y; 271 uint16_t color_b_cb; 272 uint16_t panel_inst; 273 }; 274 275 #if defined(__cplusplus) 276 } 277 #endif 278 279 //============================================================================== 280 //</DMUB_TYPES>================================================================= 281 //============================================================================== 282 //< DMUB_META>================================================================== 283 //============================================================================== 284 #pragma pack(push, 1) 285 286 /* Magic value for identifying dmub_fw_meta_info */ 287 #define DMUB_FW_META_MAGIC 0x444D5542 288 289 /* Offset from the end of the file to the dmub_fw_meta_info */ 290 #define DMUB_FW_META_OFFSET 0x24 291 292 /** 293 * struct dmub_fw_meta_info - metadata associated with fw binary 294 * 295 * NOTE: This should be considered a stable API. Fields should 296 * not be repurposed or reordered. New fields should be 297 * added instead to extend the structure. 298 * 299 * @magic_value: magic value identifying DMUB firmware meta info 300 * @fw_region_size: size of the firmware state region 301 * @trace_buffer_size: size of the tracebuffer region 302 * @fw_version: the firmware version information 303 * @dal_fw: 1 if the firmware is DAL 304 */ 305 struct dmub_fw_meta_info { 306 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 307 uint32_t fw_region_size; /**< size of the firmware state region */ 308 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 309 uint32_t fw_version; /**< the firmware version information */ 310 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 311 uint8_t reserved[3]; /**< padding bits */ 312 }; 313 314 /** 315 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 316 */ 317 union dmub_fw_meta { 318 struct dmub_fw_meta_info info; /**< metadata info */ 319 uint8_t reserved[64]; /**< padding bits */ 320 }; 321 322 #pragma pack(pop) 323 324 //============================================================================== 325 //< DMUB Trace Buffer>================================================================ 326 //============================================================================== 327 /** 328 * dmub_trace_code_t - firmware trace code, 32-bits 329 */ 330 typedef uint32_t dmub_trace_code_t; 331 332 /** 333 * struct dmcub_trace_buf_entry - Firmware trace entry 334 */ 335 struct dmcub_trace_buf_entry { 336 dmub_trace_code_t trace_code; /**< trace code for the event */ 337 uint32_t tick_count; /**< the tick count at time of trace */ 338 uint32_t param0; /**< trace defined parameter 0 */ 339 uint32_t param1; /**< trace defined parameter 1 */ 340 }; 341 342 //============================================================================== 343 //< DMUB_STATUS>================================================================ 344 //============================================================================== 345 346 /** 347 * DMCUB scratch registers can be used to determine firmware status. 348 * Current scratch register usage is as follows: 349 * 350 * SCRATCH0: FW Boot Status register 351 * SCRATCH5: LVTMA Status Register 352 * SCRATCH15: FW Boot Options register 353 */ 354 355 /** 356 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 357 */ 358 union dmub_fw_boot_status { 359 struct { 360 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 361 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 362 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 363 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 364 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 365 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 366 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 367 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 368 } bits; /**< status bits */ 369 uint32_t all; /**< 32-bit access to status bits */ 370 }; 371 372 /** 373 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 374 */ 375 enum dmub_fw_boot_status_bit { 376 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 377 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 378 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 379 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 380 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 381 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 382 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 383 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 384 }; 385 386 /* Register bit definition for SCRATCH5 */ 387 union dmub_lvtma_status { 388 struct { 389 uint32_t psp_ok : 1; 390 uint32_t edp_on : 1; 391 uint32_t reserved : 30; 392 } bits; 393 uint32_t all; 394 }; 395 396 enum dmub_lvtma_status_bit { 397 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 398 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 399 }; 400 401 enum dmub_ips_disable_type { 402 DMUB_IPS_DISABLE_IPS1 = 1, 403 DMUB_IPS_DISABLE_IPS2 = 2, 404 DMUB_IPS_DISABLE_IPS2_Z10 = 3, 405 }; 406 407 /** 408 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 409 */ 410 union dmub_fw_boot_options { 411 struct { 412 uint32_t pemu_env : 1; /**< 1 if PEMU */ 413 uint32_t fpga_env : 1; /**< 1 if FPGA */ 414 uint32_t optimized_init : 1; /**< 1 if optimized init */ 415 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 416 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 417 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 418 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 419 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 420 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 421 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 422 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 423 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 424 uint32_t power_optimization: 1; 425 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 426 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 427 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 428 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 429 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 430 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 431 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 432 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 433 uint32_t ips_disable: 2; /* options to disable ips support*/ 434 uint32_t reserved : 10; /**< reserved */ 435 } bits; /**< boot bits */ 436 uint32_t all; /**< 32-bit access to bits */ 437 }; 438 439 enum dmub_fw_boot_options_bit { 440 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 441 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 442 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 443 }; 444 445 //============================================================================== 446 //</DMUB_STATUS>================================================================ 447 //============================================================================== 448 //< DMUB_VBIOS>================================================================= 449 //============================================================================== 450 451 /* 452 * enum dmub_cmd_vbios_type - VBIOS commands. 453 * 454 * Command IDs should be treated as stable ABI. 455 * Do not reuse or modify IDs. 456 */ 457 enum dmub_cmd_vbios_type { 458 /** 459 * Configures the DIG encoder. 460 */ 461 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 462 /** 463 * Controls the PHY. 464 */ 465 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 466 /** 467 * Sets the pixel clock/symbol clock. 468 */ 469 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 470 /** 471 * Enables or disables power gating. 472 */ 473 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 474 /** 475 * Controls embedded panels. 476 */ 477 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 478 /** 479 * Query DP alt status on a transmitter. 480 */ 481 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 482 /** 483 * Controls domain power gating 484 */ 485 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 486 }; 487 488 //============================================================================== 489 //</DMUB_VBIOS>================================================================= 490 //============================================================================== 491 //< DMUB_GPINT>================================================================= 492 //============================================================================== 493 494 /** 495 * The shifts and masks below may alternatively be used to format and read 496 * the command register bits. 497 */ 498 499 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 500 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 501 502 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 503 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 504 505 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 506 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 507 508 /** 509 * Command responses. 510 */ 511 512 /** 513 * Return response for DMUB_GPINT__STOP_FW command. 514 */ 515 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 516 517 /** 518 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 519 */ 520 union dmub_gpint_data_register { 521 struct { 522 uint32_t param : 16; /**< 16-bit parameter */ 523 uint32_t command_code : 12; /**< GPINT command */ 524 uint32_t status : 4; /**< Command status bit */ 525 } bits; /**< GPINT bit access */ 526 uint32_t all; /**< GPINT 32-bit access */ 527 }; 528 529 /* 530 * enum dmub_gpint_command - GPINT command to DMCUB FW 531 * 532 * Command IDs should be treated as stable ABI. 533 * Do not reuse or modify IDs. 534 */ 535 enum dmub_gpint_command { 536 /** 537 * Invalid command, ignored. 538 */ 539 DMUB_GPINT__INVALID_COMMAND = 0, 540 /** 541 * DESC: Queries the firmware version. 542 * RETURN: Firmware version. 543 */ 544 DMUB_GPINT__GET_FW_VERSION = 1, 545 /** 546 * DESC: Halts the firmware. 547 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 548 */ 549 DMUB_GPINT__STOP_FW = 2, 550 /** 551 * DESC: Get PSR state from FW. 552 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 553 */ 554 DMUB_GPINT__GET_PSR_STATE = 7, 555 /** 556 * DESC: Notifies DMCUB of the currently active streams. 557 * ARGS: Stream mask, 1 bit per active stream index. 558 */ 559 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 560 /** 561 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 562 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 563 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 564 * RETURN: PSR residency in milli-percent. 565 */ 566 DMUB_GPINT__PSR_RESIDENCY = 9, 567 568 /** 569 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 570 */ 571 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 572 }; 573 574 /** 575 * INBOX0 generic command definition 576 */ 577 union dmub_inbox0_cmd_common { 578 struct { 579 uint32_t command_code: 8; /**< INBOX0 command code */ 580 uint32_t param: 24; /**< 24-bit parameter */ 581 } bits; 582 uint32_t all; 583 }; 584 585 /** 586 * INBOX0 hw_lock command definition 587 */ 588 union dmub_inbox0_cmd_lock_hw { 589 struct { 590 uint32_t command_code: 8; 591 592 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 593 uint32_t hw_lock_client: 2; 594 595 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 596 uint32_t otg_inst: 3; 597 uint32_t opp_inst: 3; 598 uint32_t dig_inst: 3; 599 600 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 601 uint32_t lock_pipe: 1; 602 uint32_t lock_cursor: 1; 603 uint32_t lock_dig: 1; 604 uint32_t triple_buffer_lock: 1; 605 606 uint32_t lock: 1; /**< Lock */ 607 uint32_t should_release: 1; /**< Release */ 608 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 609 } bits; 610 uint32_t all; 611 }; 612 613 union dmub_inbox0_data_register { 614 union dmub_inbox0_cmd_common inbox0_cmd_common; 615 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 616 }; 617 618 enum dmub_inbox0_command { 619 /** 620 * DESC: Invalid command, ignored. 621 */ 622 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 623 /** 624 * DESC: Notification to acquire/release HW lock 625 * ARGS: 626 */ 627 DMUB_INBOX0_CMD__HW_LOCK = 1, 628 }; 629 //============================================================================== 630 //</DMUB_GPINT>================================================================= 631 //============================================================================== 632 //< DMUB_CMD>=================================================================== 633 //============================================================================== 634 635 /** 636 * Size in bytes of each DMUB command. 637 */ 638 #define DMUB_RB_CMD_SIZE 64 639 640 /** 641 * Maximum number of items in the DMUB ringbuffer. 642 */ 643 #define DMUB_RB_MAX_ENTRY 128 644 645 /** 646 * Ringbuffer size in bytes. 647 */ 648 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 649 650 /** 651 * REG_SET mask for reg offload. 652 */ 653 #define REG_SET_MASK 0xFFFF 654 655 /* 656 * enum dmub_cmd_type - DMUB inbox command. 657 * 658 * Command IDs should be treated as stable ABI. 659 * Do not reuse or modify IDs. 660 */ 661 enum dmub_cmd_type { 662 /** 663 * Invalid command. 664 */ 665 DMUB_CMD__NULL = 0, 666 /** 667 * Read modify write register sequence offload. 668 */ 669 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 670 /** 671 * Field update register sequence offload. 672 */ 673 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 674 /** 675 * Burst write sequence offload. 676 */ 677 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 678 /** 679 * Reg wait sequence offload. 680 */ 681 DMUB_CMD__REG_REG_WAIT = 4, 682 /** 683 * Workaround to avoid HUBP underflow during NV12 playback. 684 */ 685 DMUB_CMD__PLAT_54186_WA = 5, 686 /** 687 * Command type used to query FW feature caps. 688 */ 689 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 690 /** 691 * Command type used to get visual confirm color. 692 */ 693 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 694 /** 695 * Command type used for all PSR commands. 696 */ 697 DMUB_CMD__PSR = 64, 698 /** 699 * Command type used for all MALL commands. 700 */ 701 DMUB_CMD__MALL = 65, 702 /** 703 * Command type used for all ABM commands. 704 */ 705 DMUB_CMD__ABM = 66, 706 /** 707 * Command type used to update dirty rects in FW. 708 */ 709 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 710 /** 711 * Command type used to update cursor info in FW. 712 */ 713 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 714 /** 715 * Command type used for HW locking in FW. 716 */ 717 DMUB_CMD__HW_LOCK = 69, 718 /** 719 * Command type used to access DP AUX. 720 */ 721 DMUB_CMD__DP_AUX_ACCESS = 70, 722 /** 723 * Command type used for OUTBOX1 notification enable 724 */ 725 DMUB_CMD__OUTBOX1_ENABLE = 71, 726 727 /** 728 * Command type used for all idle optimization commands. 729 */ 730 DMUB_CMD__IDLE_OPT = 72, 731 /** 732 * Command type used for all clock manager commands. 733 */ 734 DMUB_CMD__CLK_MGR = 73, 735 /** 736 * Command type used for all panel control commands. 737 */ 738 DMUB_CMD__PANEL_CNTL = 74, 739 /** 740 * Command type used for <TODO:description> 741 */ 742 DMUB_CMD__CAB_FOR_SS = 75, 743 744 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 745 746 /** 747 * Command type used for interfacing with DPIA. 748 */ 749 DMUB_CMD__DPIA = 77, 750 /** 751 * Command type used for EDID CEA parsing 752 */ 753 DMUB_CMD__EDID_CEA = 79, 754 /** 755 * Command type used for getting usbc cable ID 756 */ 757 DMUB_CMD_GET_USBC_CABLE_ID = 81, 758 /** 759 * Command type used to query HPD state. 760 */ 761 DMUB_CMD__QUERY_HPD_STATE = 82, 762 /** 763 * Command type used for all VBIOS interface commands. 764 */ 765 766 /** 767 * Command type used for all SECURE_DISPLAY commands. 768 */ 769 DMUB_CMD__SECURE_DISPLAY = 85, 770 771 /** 772 * Command type used to set DPIA HPD interrupt state 773 */ 774 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 775 776 DMUB_CMD__VBIOS = 128, 777 }; 778 779 /** 780 * enum dmub_out_cmd_type - DMUB outbox commands. 781 */ 782 enum dmub_out_cmd_type { 783 /** 784 * Invalid outbox command, ignored. 785 */ 786 DMUB_OUT_CMD__NULL = 0, 787 /** 788 * Command type used for DP AUX Reply data notification 789 */ 790 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 791 /** 792 * Command type used for DP HPD event notification 793 */ 794 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 795 /** 796 * Command type used for SET_CONFIG Reply notification 797 */ 798 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 799 /** 800 * Command type used for USB4 DPIA notification 801 */ 802 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 803 }; 804 805 /* DMUB_CMD__DPIA command sub-types. */ 806 enum dmub_cmd_dpia_type { 807 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 808 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 809 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 810 }; 811 812 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 813 enum dmub_cmd_dpia_notification_type { 814 DPIA_NOTIFY__BW_ALLOCATION = 0, 815 }; 816 817 #pragma pack(push, 1) 818 819 /** 820 * struct dmub_cmd_header - Common command header fields. 821 */ 822 struct dmub_cmd_header { 823 unsigned int type : 8; /**< command type */ 824 unsigned int sub_type : 8; /**< command sub type */ 825 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 826 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 827 unsigned int reserved0 : 6; /**< reserved bits */ 828 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 829 unsigned int reserved1 : 2; /**< reserved bits */ 830 }; 831 832 /* 833 * struct dmub_cmd_read_modify_write_sequence - Read modify write 834 * 835 * 60 payload bytes can hold up to 5 sets of read modify writes, 836 * each take 3 dwords. 837 * 838 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 839 * 840 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 841 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 842 */ 843 struct dmub_cmd_read_modify_write_sequence { 844 uint32_t addr; /**< register address */ 845 uint32_t modify_mask; /**< modify mask */ 846 uint32_t modify_value; /**< modify value */ 847 }; 848 849 /** 850 * Maximum number of ops in read modify write sequence. 851 */ 852 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 853 854 /** 855 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 856 */ 857 struct dmub_rb_cmd_read_modify_write { 858 struct dmub_cmd_header header; /**< command header */ 859 /** 860 * Read modify write sequence. 861 */ 862 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 863 }; 864 865 /* 866 * Update a register with specified masks and values sequeunce 867 * 868 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 869 * 870 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 871 * 872 * 873 * USE CASE: 874 * 1. auto-increment register where additional read would update pointer and produce wrong result 875 * 2. toggle a bit without read in the middle 876 */ 877 878 struct dmub_cmd_reg_field_update_sequence { 879 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 880 uint32_t modify_value; /**< value to update with */ 881 }; 882 883 /** 884 * Maximum number of ops in field update sequence. 885 */ 886 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 887 888 /** 889 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 890 */ 891 struct dmub_rb_cmd_reg_field_update_sequence { 892 struct dmub_cmd_header header; /**< command header */ 893 uint32_t addr; /**< register address */ 894 /** 895 * Field update sequence. 896 */ 897 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 898 }; 899 900 901 /** 902 * Maximum number of burst write values. 903 */ 904 #define DMUB_BURST_WRITE_VALUES__MAX 14 905 906 /* 907 * struct dmub_rb_cmd_burst_write - Burst write 908 * 909 * support use case such as writing out LUTs. 910 * 911 * 60 payload bytes can hold up to 14 values to write to given address 912 * 913 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 914 */ 915 struct dmub_rb_cmd_burst_write { 916 struct dmub_cmd_header header; /**< command header */ 917 uint32_t addr; /**< register start address */ 918 /** 919 * Burst write register values. 920 */ 921 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 922 }; 923 924 /** 925 * struct dmub_rb_cmd_common - Common command header 926 */ 927 struct dmub_rb_cmd_common { 928 struct dmub_cmd_header header; /**< command header */ 929 /** 930 * Padding to RB_CMD_SIZE 931 */ 932 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 933 }; 934 935 /** 936 * struct dmub_cmd_reg_wait_data - Register wait data 937 */ 938 struct dmub_cmd_reg_wait_data { 939 uint32_t addr; /**< Register address */ 940 uint32_t mask; /**< Mask for register bits */ 941 uint32_t condition_field_value; /**< Value to wait for */ 942 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 943 }; 944 945 /** 946 * struct dmub_rb_cmd_reg_wait - Register wait command 947 */ 948 struct dmub_rb_cmd_reg_wait { 949 struct dmub_cmd_header header; /**< Command header */ 950 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 951 }; 952 953 /** 954 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 955 * 956 * Reprograms surface parameters to avoid underflow. 957 */ 958 struct dmub_cmd_PLAT_54186_wa { 959 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 960 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 961 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 962 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 963 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 964 struct { 965 uint8_t hubp_inst : 4; /**< HUBP instance */ 966 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 967 uint8_t immediate :1; /**< Immediate flip */ 968 uint8_t vmid : 4; /**< VMID */ 969 uint8_t grph_stereo : 1; /**< 1 if stereo */ 970 uint32_t reserved : 21; /**< Reserved */ 971 } flip_params; /**< Pageflip parameters */ 972 uint32_t reserved[9]; /**< Reserved bits */ 973 }; 974 975 /** 976 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 977 */ 978 struct dmub_rb_cmd_PLAT_54186_wa { 979 struct dmub_cmd_header header; /**< Command header */ 980 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 981 }; 982 983 /** 984 * struct dmub_rb_cmd_mall - MALL command data. 985 */ 986 struct dmub_rb_cmd_mall { 987 struct dmub_cmd_header header; /**< Common command header */ 988 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 989 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 990 uint32_t tmr_delay; /**< Timer delay */ 991 uint32_t tmr_scale; /**< Timer scale */ 992 uint16_t cursor_width; /**< Cursor width in pixels */ 993 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 994 uint16_t cursor_height; /**< Cursor height in pixels */ 995 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 996 uint8_t debug_bits; /**< Debug bits */ 997 998 uint8_t reserved1; /**< Reserved bits */ 999 uint8_t reserved2; /**< Reserved bits */ 1000 }; 1001 1002 /** 1003 * enum dmub_cmd_cab_type - CAB command data. 1004 */ 1005 enum dmub_cmd_cab_type { 1006 /** 1007 * No idle optimizations (i.e. no CAB) 1008 */ 1009 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1010 /** 1011 * No DCN requests for memory 1012 */ 1013 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1014 /** 1015 * Fit surfaces in CAB (i.e. CAB enable) 1016 */ 1017 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1018 }; 1019 1020 /** 1021 * struct dmub_rb_cmd_cab - CAB command data. 1022 */ 1023 struct dmub_rb_cmd_cab_for_ss { 1024 struct dmub_cmd_header header; 1025 uint8_t cab_alloc_ways; /* total number of ways */ 1026 uint8_t debug_bits; /* debug bits */ 1027 }; 1028 1029 /** 1030 * Enum for indicating which MCLK switch mode per pipe 1031 */ 1032 enum mclk_switch_mode { 1033 NONE = 0, 1034 FPO = 1, 1035 SUBVP = 2, 1036 VBLANK = 3, 1037 }; 1038 1039 /* Per pipe struct which stores the MCLK switch mode 1040 * data to be sent to DMUB. 1041 * Named "v2" for now -- once FPO and SUBVP are fully merged 1042 * the type name can be updated 1043 */ 1044 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1045 union { 1046 struct { 1047 uint32_t pix_clk_100hz; 1048 uint16_t main_vblank_start; 1049 uint16_t main_vblank_end; 1050 uint16_t mall_region_lines; 1051 uint16_t prefetch_lines; 1052 uint16_t prefetch_to_mall_start_lines; 1053 uint16_t processing_delay_lines; 1054 uint16_t htotal; // required to calculate line time for multi-display cases 1055 uint16_t vtotal; 1056 uint8_t main_pipe_index; 1057 uint8_t phantom_pipe_index; 1058 /* Since the microschedule is calculated in terms of OTG lines, 1059 * include any scaling factors to make sure when we get accurate 1060 * conversion when programming MALL_START_LINE (which is in terms 1061 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1062 * is 1/2 (numerator = 1, denominator = 2). 1063 */ 1064 uint8_t scale_factor_numerator; 1065 uint8_t scale_factor_denominator; 1066 uint8_t is_drr; 1067 uint8_t main_split_pipe_index; 1068 uint8_t phantom_split_pipe_index; 1069 } subvp_data; 1070 1071 struct { 1072 uint32_t pix_clk_100hz; 1073 uint16_t vblank_start; 1074 uint16_t vblank_end; 1075 uint16_t vstartup_start; 1076 uint16_t vtotal; 1077 uint16_t htotal; 1078 uint8_t vblank_pipe_index; 1079 uint8_t padding[1]; 1080 struct { 1081 uint8_t drr_in_use; 1082 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1083 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1084 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1085 uint8_t use_ramping; // Use ramping or not 1086 uint8_t drr_vblank_start_margin; 1087 } drr_info; // DRR considered as part of SubVP + VBLANK case 1088 } vblank_data; 1089 } pipe_config; 1090 1091 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1092 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1093 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1094 */ 1095 uint8_t mode; // enum mclk_switch_mode 1096 }; 1097 1098 /** 1099 * Config data for Sub-VP and FPO 1100 * Named "v2" for now -- once FPO and SUBVP are fully merged 1101 * the type name can be updated 1102 */ 1103 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1104 uint16_t watermark_a_cache; 1105 uint8_t vertical_int_margin_us; 1106 uint8_t pstate_allow_width_us; 1107 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1108 }; 1109 1110 /** 1111 * DMUB rb command definition for Sub-VP and FPO 1112 * Named "v2" for now -- once FPO and SUBVP are fully merged 1113 * the type name can be updated 1114 */ 1115 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1116 struct dmub_cmd_header header; 1117 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1118 }; 1119 1120 /** 1121 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1122 */ 1123 enum dmub_cmd_idle_opt_type { 1124 /** 1125 * DCN hardware restore. 1126 */ 1127 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1128 1129 /** 1130 * DCN hardware save. 1131 */ 1132 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1133 1134 /** 1135 * DCN hardware notify idle. 1136 */ 1137 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1138 }; 1139 1140 /** 1141 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1142 */ 1143 struct dmub_rb_cmd_idle_opt_dcn_restore { 1144 struct dmub_cmd_header header; /**< header */ 1145 }; 1146 1147 /** 1148 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1149 */ 1150 struct dmub_dcn_notify_idle_cntl_data { 1151 uint8_t driver_idle; 1152 uint8_t pad[1]; 1153 }; 1154 1155 /** 1156 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1157 */ 1158 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1159 struct dmub_cmd_header header; /**< header */ 1160 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1161 }; 1162 1163 /** 1164 * struct dmub_clocks - Clock update notification. 1165 */ 1166 struct dmub_clocks { 1167 uint32_t dispclk_khz; /**< dispclk kHz */ 1168 uint32_t dppclk_khz; /**< dppclk kHz */ 1169 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1170 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1171 }; 1172 1173 /** 1174 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1175 */ 1176 enum dmub_cmd_clk_mgr_type { 1177 /** 1178 * Notify DMCUB of clock update. 1179 */ 1180 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1181 }; 1182 1183 /** 1184 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1185 */ 1186 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1187 struct dmub_cmd_header header; /**< header */ 1188 struct dmub_clocks clocks; /**< clock data */ 1189 }; 1190 1191 /** 1192 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1193 */ 1194 struct dmub_cmd_digx_encoder_control_data { 1195 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1196 }; 1197 1198 /** 1199 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1200 */ 1201 struct dmub_rb_cmd_digx_encoder_control { 1202 struct dmub_cmd_header header; /**< header */ 1203 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1204 }; 1205 1206 /** 1207 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1208 */ 1209 struct dmub_cmd_set_pixel_clock_data { 1210 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1211 }; 1212 1213 /** 1214 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1215 */ 1216 struct dmub_rb_cmd_set_pixel_clock { 1217 struct dmub_cmd_header header; /**< header */ 1218 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1219 }; 1220 1221 /** 1222 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1223 */ 1224 struct dmub_cmd_enable_disp_power_gating_data { 1225 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1226 }; 1227 1228 /** 1229 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1230 */ 1231 struct dmub_rb_cmd_enable_disp_power_gating { 1232 struct dmub_cmd_header header; /**< header */ 1233 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1234 }; 1235 1236 /** 1237 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1238 */ 1239 struct dmub_dig_transmitter_control_data_v1_7 { 1240 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1241 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1242 union { 1243 uint8_t digmode; /**< enum atom_encode_mode_def */ 1244 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1245 } mode_laneset; 1246 uint8_t lanenum; /**< Number of lanes */ 1247 union { 1248 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1249 } symclk_units; 1250 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1251 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1252 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1253 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1254 uint8_t reserved1; /**< For future use */ 1255 uint8_t reserved2[3]; /**< For future use */ 1256 uint32_t reserved3[11]; /**< For future use */ 1257 }; 1258 1259 /** 1260 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1261 */ 1262 union dmub_cmd_dig1_transmitter_control_data { 1263 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1264 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1265 }; 1266 1267 /** 1268 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1269 */ 1270 struct dmub_rb_cmd_dig1_transmitter_control { 1271 struct dmub_cmd_header header; /**< header */ 1272 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1273 }; 1274 1275 /** 1276 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1277 */ 1278 struct dmub_rb_cmd_domain_control_data { 1279 uint8_t inst : 6; /**< DOMAIN instance to control */ 1280 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1281 uint8_t reserved[3]; /**< Reserved for future use */ 1282 }; 1283 1284 /** 1285 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1286 */ 1287 struct dmub_rb_cmd_domain_control { 1288 struct dmub_cmd_header header; /**< header */ 1289 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1290 }; 1291 1292 /** 1293 * DPIA tunnel command parameters. 1294 */ 1295 struct dmub_cmd_dig_dpia_control_data { 1296 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1297 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1298 union { 1299 uint8_t digmode; /** enum atom_encode_mode_def */ 1300 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1301 } mode_laneset; 1302 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1303 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1304 uint8_t hpdsel; /** =0: HPD is not assigned */ 1305 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1306 uint8_t dpia_id; /** Index of DPIA */ 1307 uint8_t fec_rdy : 1; 1308 uint8_t reserved : 7; 1309 uint32_t reserved1; 1310 }; 1311 1312 /** 1313 * DMUB command for DPIA tunnel control. 1314 */ 1315 struct dmub_rb_cmd_dig1_dpia_control { 1316 struct dmub_cmd_header header; 1317 struct dmub_cmd_dig_dpia_control_data dpia_control; 1318 }; 1319 1320 /** 1321 * SET_CONFIG Command Payload 1322 */ 1323 struct set_config_cmd_payload { 1324 uint8_t msg_type; /* set config message type */ 1325 uint8_t msg_data; /* set config message data */ 1326 }; 1327 1328 /** 1329 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1330 */ 1331 struct dmub_cmd_set_config_control_data { 1332 struct set_config_cmd_payload cmd_pkt; 1333 uint8_t instance; /* DPIA instance */ 1334 uint8_t immed_status; /* Immediate status returned in case of error */ 1335 }; 1336 1337 /** 1338 * DMUB command structure for SET_CONFIG command. 1339 */ 1340 struct dmub_rb_cmd_set_config_access { 1341 struct dmub_cmd_header header; /* header */ 1342 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1343 }; 1344 1345 /** 1346 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1347 */ 1348 struct dmub_cmd_mst_alloc_slots_control_data { 1349 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1350 uint8_t instance; /* DPIA instance */ 1351 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1352 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1353 }; 1354 1355 /** 1356 * DMUB command structure for SET_ command. 1357 */ 1358 struct dmub_rb_cmd_set_mst_alloc_slots { 1359 struct dmub_cmd_header header; /* header */ 1360 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1361 }; 1362 1363 /** 1364 * DMUB command structure for DPIA HPD int enable control. 1365 */ 1366 struct dmub_rb_cmd_dpia_hpd_int_enable { 1367 struct dmub_cmd_header header; /* header */ 1368 uint32_t enable; /* dpia hpd interrupt enable */ 1369 }; 1370 1371 /** 1372 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1373 */ 1374 struct dmub_rb_cmd_dpphy_init { 1375 struct dmub_cmd_header header; /**< header */ 1376 uint8_t reserved[60]; /**< reserved bits */ 1377 }; 1378 1379 /** 1380 * enum dp_aux_request_action - DP AUX request command listing. 1381 * 1382 * 4 AUX request command bits are shifted to high nibble. 1383 */ 1384 enum dp_aux_request_action { 1385 /** I2C-over-AUX write request */ 1386 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1387 /** I2C-over-AUX read request */ 1388 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1389 /** I2C-over-AUX write status request */ 1390 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1391 /** I2C-over-AUX write request with MOT=1 */ 1392 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1393 /** I2C-over-AUX read request with MOT=1 */ 1394 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1395 /** I2C-over-AUX write status request with MOT=1 */ 1396 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1397 /** Native AUX write request */ 1398 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1399 /** Native AUX read request */ 1400 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1401 }; 1402 1403 /** 1404 * enum aux_return_code_type - DP AUX process return code listing. 1405 */ 1406 enum aux_return_code_type { 1407 /** AUX process succeeded */ 1408 AUX_RET_SUCCESS = 0, 1409 /** AUX process failed with unknown reason */ 1410 AUX_RET_ERROR_UNKNOWN, 1411 /** AUX process completed with invalid reply */ 1412 AUX_RET_ERROR_INVALID_REPLY, 1413 /** AUX process timed out */ 1414 AUX_RET_ERROR_TIMEOUT, 1415 /** HPD was low during AUX process */ 1416 AUX_RET_ERROR_HPD_DISCON, 1417 /** Failed to acquire AUX engine */ 1418 AUX_RET_ERROR_ENGINE_ACQUIRE, 1419 /** AUX request not supported */ 1420 AUX_RET_ERROR_INVALID_OPERATION, 1421 /** AUX process not available */ 1422 AUX_RET_ERROR_PROTOCOL_ERROR, 1423 }; 1424 1425 /** 1426 * enum aux_channel_type - DP AUX channel type listing. 1427 */ 1428 enum aux_channel_type { 1429 /** AUX thru Legacy DP AUX */ 1430 AUX_CHANNEL_LEGACY_DDC, 1431 /** AUX thru DPIA DP tunneling */ 1432 AUX_CHANNEL_DPIA 1433 }; 1434 1435 /** 1436 * struct aux_transaction_parameters - DP AUX request transaction data 1437 */ 1438 struct aux_transaction_parameters { 1439 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1440 uint8_t action; /**< enum dp_aux_request_action */ 1441 uint8_t length; /**< DP AUX request data length */ 1442 uint8_t reserved; /**< For future use */ 1443 uint32_t address; /**< DP AUX address */ 1444 uint8_t data[16]; /**< DP AUX write data */ 1445 }; 1446 1447 /** 1448 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1449 */ 1450 struct dmub_cmd_dp_aux_control_data { 1451 uint8_t instance; /**< AUX instance or DPIA instance */ 1452 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1453 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1454 uint8_t reserved0; /**< For future use */ 1455 uint16_t timeout; /**< timeout time in us */ 1456 uint16_t reserved1; /**< For future use */ 1457 enum aux_channel_type type; /**< enum aux_channel_type */ 1458 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1459 }; 1460 1461 /** 1462 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1463 */ 1464 struct dmub_rb_cmd_dp_aux_access { 1465 /** 1466 * Command header. 1467 */ 1468 struct dmub_cmd_header header; 1469 /** 1470 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1471 */ 1472 struct dmub_cmd_dp_aux_control_data aux_control; 1473 }; 1474 1475 /** 1476 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1477 */ 1478 struct dmub_rb_cmd_outbox1_enable { 1479 /** 1480 * Command header. 1481 */ 1482 struct dmub_cmd_header header; 1483 /** 1484 * enable: 0x0 -> disable outbox1 notification (default value) 1485 * 0x1 -> enable outbox1 notification 1486 */ 1487 uint32_t enable; 1488 }; 1489 1490 /* DP AUX Reply command - OutBox Cmd */ 1491 /** 1492 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1493 */ 1494 struct aux_reply_data { 1495 /** 1496 * Aux cmd 1497 */ 1498 uint8_t command; 1499 /** 1500 * Aux reply data length (max: 16 bytes) 1501 */ 1502 uint8_t length; 1503 /** 1504 * Alignment only 1505 */ 1506 uint8_t pad[2]; 1507 /** 1508 * Aux reply data 1509 */ 1510 uint8_t data[16]; 1511 }; 1512 1513 /** 1514 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1515 */ 1516 struct aux_reply_control_data { 1517 /** 1518 * Reserved for future use 1519 */ 1520 uint32_t handle; 1521 /** 1522 * Aux Instance 1523 */ 1524 uint8_t instance; 1525 /** 1526 * Aux transaction result: definition in enum aux_return_code_type 1527 */ 1528 uint8_t result; 1529 /** 1530 * Alignment only 1531 */ 1532 uint16_t pad; 1533 }; 1534 1535 /** 1536 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1537 */ 1538 struct dmub_rb_cmd_dp_aux_reply { 1539 /** 1540 * Command header. 1541 */ 1542 struct dmub_cmd_header header; 1543 /** 1544 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1545 */ 1546 struct aux_reply_control_data control; 1547 /** 1548 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1549 */ 1550 struct aux_reply_data reply_data; 1551 }; 1552 1553 /* DP HPD Notify command - OutBox Cmd */ 1554 /** 1555 * DP HPD Type 1556 */ 1557 enum dp_hpd_type { 1558 /** 1559 * Normal DP HPD 1560 */ 1561 DP_HPD = 0, 1562 /** 1563 * DP HPD short pulse 1564 */ 1565 DP_IRQ 1566 }; 1567 1568 /** 1569 * DP HPD Status 1570 */ 1571 enum dp_hpd_status { 1572 /** 1573 * DP_HPD status low 1574 */ 1575 DP_HPD_UNPLUG = 0, 1576 /** 1577 * DP_HPD status high 1578 */ 1579 DP_HPD_PLUG 1580 }; 1581 1582 /** 1583 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1584 */ 1585 struct dp_hpd_data { 1586 /** 1587 * DP HPD instance 1588 */ 1589 uint8_t instance; 1590 /** 1591 * HPD type 1592 */ 1593 uint8_t hpd_type; 1594 /** 1595 * HPD status: only for type: DP_HPD to indicate status 1596 */ 1597 uint8_t hpd_status; 1598 /** 1599 * Alignment only 1600 */ 1601 uint8_t pad; 1602 }; 1603 1604 /** 1605 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1606 */ 1607 struct dmub_rb_cmd_dp_hpd_notify { 1608 /** 1609 * Command header. 1610 */ 1611 struct dmub_cmd_header header; 1612 /** 1613 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1614 */ 1615 struct dp_hpd_data hpd_data; 1616 }; 1617 1618 /** 1619 * Definition of a SET_CONFIG reply from DPOA. 1620 */ 1621 enum set_config_status { 1622 SET_CONFIG_PENDING = 0, 1623 SET_CONFIG_ACK_RECEIVED, 1624 SET_CONFIG_RX_TIMEOUT, 1625 SET_CONFIG_UNKNOWN_ERROR, 1626 }; 1627 1628 /** 1629 * Definition of a set_config reply 1630 */ 1631 struct set_config_reply_control_data { 1632 uint8_t instance; /* DPIA Instance */ 1633 uint8_t status; /* Set Config reply */ 1634 uint16_t pad; /* Alignment */ 1635 }; 1636 1637 /** 1638 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1639 */ 1640 struct dmub_rb_cmd_dp_set_config_reply { 1641 struct dmub_cmd_header header; 1642 struct set_config_reply_control_data set_config_reply_control; 1643 }; 1644 1645 /** 1646 * Definition of a DPIA notification header 1647 */ 1648 struct dpia_notification_header { 1649 uint8_t instance; /**< DPIA Instance */ 1650 uint8_t reserved[3]; 1651 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1652 }; 1653 1654 /** 1655 * Definition of the common data struct of DPIA notification 1656 */ 1657 struct dpia_notification_common { 1658 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1659 - sizeof(struct dpia_notification_header)]; 1660 }; 1661 1662 /** 1663 * Definition of a DPIA notification data 1664 */ 1665 struct dpia_bw_allocation_notify_data { 1666 union { 1667 struct { 1668 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1669 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1670 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1671 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1672 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1673 uint16_t reserved: 11; /**< Reserved */ 1674 } bits; 1675 1676 uint16_t flags; 1677 }; 1678 1679 uint8_t cm_id; /**< CM ID */ 1680 uint8_t group_id; /**< Group ID */ 1681 uint8_t granularity; /**< BW Allocation Granularity */ 1682 uint8_t estimated_bw; /**< Estimated_BW */ 1683 uint8_t allocated_bw; /**< Allocated_BW */ 1684 uint8_t reserved; 1685 }; 1686 1687 /** 1688 * union dpia_notify_data_type - DPIA Notification in Outbox command 1689 */ 1690 union dpia_notification_data { 1691 /** 1692 * DPIA Notification for common data struct 1693 */ 1694 struct dpia_notification_common common_data; 1695 1696 /** 1697 * DPIA Notification for DP BW Allocation support 1698 */ 1699 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1700 }; 1701 1702 /** 1703 * Definition of a DPIA notification payload 1704 */ 1705 struct dpia_notification_payload { 1706 struct dpia_notification_header header; 1707 union dpia_notification_data data; /**< DPIA notification payload data */ 1708 }; 1709 1710 /** 1711 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1712 */ 1713 struct dmub_rb_cmd_dpia_notification { 1714 struct dmub_cmd_header header; /**< DPIA notification header */ 1715 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1716 }; 1717 1718 /** 1719 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1720 */ 1721 struct dmub_cmd_hpd_state_query_data { 1722 uint8_t instance; /**< HPD instance or DPIA instance */ 1723 uint8_t result; /**< For returning HPD state */ 1724 uint16_t pad; /** < Alignment */ 1725 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1726 enum aux_return_code_type status; /**< for returning the status of command */ 1727 }; 1728 1729 /** 1730 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1731 */ 1732 struct dmub_rb_cmd_query_hpd_state { 1733 /** 1734 * Command header. 1735 */ 1736 struct dmub_cmd_header header; 1737 /** 1738 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1739 */ 1740 struct dmub_cmd_hpd_state_query_data data; 1741 }; 1742 1743 /* 1744 * Command IDs should be treated as stable ABI. 1745 * Do not reuse or modify IDs. 1746 */ 1747 1748 /** 1749 * PSR command sub-types. 1750 */ 1751 enum dmub_cmd_psr_type { 1752 /** 1753 * Set PSR version support. 1754 */ 1755 DMUB_CMD__PSR_SET_VERSION = 0, 1756 /** 1757 * Copy driver-calculated parameters to PSR state. 1758 */ 1759 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1760 /** 1761 * Enable PSR. 1762 */ 1763 DMUB_CMD__PSR_ENABLE = 2, 1764 1765 /** 1766 * Disable PSR. 1767 */ 1768 DMUB_CMD__PSR_DISABLE = 3, 1769 1770 /** 1771 * Set PSR level. 1772 * PSR level is a 16-bit value dicated by driver that 1773 * will enable/disable different functionality. 1774 */ 1775 DMUB_CMD__PSR_SET_LEVEL = 4, 1776 1777 /** 1778 * Forces PSR enabled until an explicit PSR disable call. 1779 */ 1780 DMUB_CMD__PSR_FORCE_STATIC = 5, 1781 /** 1782 * Set vtotal in psr active for FreeSync PSR. 1783 */ 1784 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1785 /** 1786 * Set PSR power option 1787 */ 1788 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1789 }; 1790 1791 enum dmub_cmd_fams_type { 1792 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1793 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1794 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1795 /** 1796 * For SubVP set manual trigger in FW because it 1797 * triggers DRR_UPDATE_PENDING which SubVP relies 1798 * on (for any SubVP cases that use a DRR display) 1799 */ 1800 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1801 }; 1802 1803 /** 1804 * PSR versions. 1805 */ 1806 enum psr_version { 1807 /** 1808 * PSR version 1. 1809 */ 1810 PSR_VERSION_1 = 0, 1811 /** 1812 * Freesync PSR SU. 1813 */ 1814 PSR_VERSION_SU_1 = 1, 1815 /** 1816 * PSR not supported. 1817 */ 1818 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1819 }; 1820 1821 /** 1822 * enum dmub_cmd_mall_type - MALL commands 1823 */ 1824 enum dmub_cmd_mall_type { 1825 /** 1826 * Allows display refresh from MALL. 1827 */ 1828 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1829 /** 1830 * Disallows display refresh from MALL. 1831 */ 1832 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1833 /** 1834 * Cursor copy for MALL. 1835 */ 1836 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1837 /** 1838 * Controls DF requests. 1839 */ 1840 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1841 }; 1842 1843 /** 1844 * PHY Link rate for DP. 1845 */ 1846 enum phy_link_rate { 1847 /** 1848 * not supported. 1849 */ 1850 PHY_RATE_UNKNOWN = 0, 1851 /** 1852 * Rate_1 (RBR) - 1.62 Gbps/Lane 1853 */ 1854 PHY_RATE_162 = 1, 1855 /** 1856 * Rate_2 - 2.16 Gbps/Lane 1857 */ 1858 PHY_RATE_216 = 2, 1859 /** 1860 * Rate_3 - 2.43 Gbps/Lane 1861 */ 1862 PHY_RATE_243 = 3, 1863 /** 1864 * Rate_4 (HBR) - 2.70 Gbps/Lane 1865 */ 1866 PHY_RATE_270 = 4, 1867 /** 1868 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1869 */ 1870 PHY_RATE_324 = 5, 1871 /** 1872 * Rate_6 - 4.32 Gbps/Lane 1873 */ 1874 PHY_RATE_432 = 6, 1875 /** 1876 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1877 */ 1878 PHY_RATE_540 = 7, 1879 /** 1880 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1881 */ 1882 PHY_RATE_810 = 8, 1883 /** 1884 * UHBR10 - 10.0 Gbps/Lane 1885 */ 1886 PHY_RATE_1000 = 9, 1887 /** 1888 * UHBR13.5 - 13.5 Gbps/Lane 1889 */ 1890 PHY_RATE_1350 = 10, 1891 /** 1892 * UHBR10 - 20.0 Gbps/Lane 1893 */ 1894 PHY_RATE_2000 = 11, 1895 }; 1896 1897 /** 1898 * enum dmub_phy_fsm_state - PHY FSM states. 1899 * PHY FSM state to transit to during PSR enable/disable. 1900 */ 1901 enum dmub_phy_fsm_state { 1902 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1903 DMUB_PHY_FSM_RESET, 1904 DMUB_PHY_FSM_RESET_RELEASED, 1905 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1906 DMUB_PHY_FSM_INITIALIZED, 1907 DMUB_PHY_FSM_CALIBRATED, 1908 DMUB_PHY_FSM_CALIBRATED_LP, 1909 DMUB_PHY_FSM_CALIBRATED_PG, 1910 DMUB_PHY_FSM_POWER_DOWN, 1911 DMUB_PHY_FSM_PLL_EN, 1912 DMUB_PHY_FSM_TX_EN, 1913 DMUB_PHY_FSM_FAST_LP, 1914 }; 1915 1916 /** 1917 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1918 */ 1919 struct dmub_cmd_psr_copy_settings_data { 1920 /** 1921 * Flags that can be set by driver to change some PSR behaviour. 1922 */ 1923 union dmub_psr_debug_flags debug; 1924 /** 1925 * 16-bit value dicated by driver that will enable/disable different functionality. 1926 */ 1927 uint16_t psr_level; 1928 /** 1929 * DPP HW instance. 1930 */ 1931 uint8_t dpp_inst; 1932 /** 1933 * MPCC HW instance. 1934 * Not used in dmub fw, 1935 * dmub fw will get active opp by reading odm registers. 1936 */ 1937 uint8_t mpcc_inst; 1938 /** 1939 * OPP HW instance. 1940 * Not used in dmub fw, 1941 * dmub fw will get active opp by reading odm registers. 1942 */ 1943 uint8_t opp_inst; 1944 /** 1945 * OTG HW instance. 1946 */ 1947 uint8_t otg_inst; 1948 /** 1949 * DIG FE HW instance. 1950 */ 1951 uint8_t digfe_inst; 1952 /** 1953 * DIG BE HW instance. 1954 */ 1955 uint8_t digbe_inst; 1956 /** 1957 * DP PHY HW instance. 1958 */ 1959 uint8_t dpphy_inst; 1960 /** 1961 * AUX HW instance. 1962 */ 1963 uint8_t aux_inst; 1964 /** 1965 * Determines if SMU optimzations are enabled/disabled. 1966 */ 1967 uint8_t smu_optimizations_en; 1968 /** 1969 * Unused. 1970 * TODO: Remove. 1971 */ 1972 uint8_t frame_delay; 1973 /** 1974 * If RFB setup time is greater than the total VBLANK time, 1975 * it is not possible for the sink to capture the video frame 1976 * in the same frame the SDP is sent. In this case, 1977 * the frame capture indication bit should be set and an extra 1978 * static frame should be transmitted to the sink. 1979 */ 1980 uint8_t frame_cap_ind; 1981 /** 1982 * Granularity of Y offset supported by sink. 1983 */ 1984 uint8_t su_y_granularity; 1985 /** 1986 * Indicates whether sink should start capturing 1987 * immediately following active scan line, 1988 * or starting with the 2nd active scan line. 1989 */ 1990 uint8_t line_capture_indication; 1991 /** 1992 * Multi-display optimizations are implemented on certain ASICs. 1993 */ 1994 uint8_t multi_disp_optimizations_en; 1995 /** 1996 * The last possible line SDP may be transmitted without violating 1997 * the RFB setup time or entering the active video frame. 1998 */ 1999 uint16_t init_sdp_deadline; 2000 /** 2001 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2002 */ 2003 uint8_t rate_control_caps ; 2004 /* 2005 * Force PSRSU always doing full frame update 2006 */ 2007 uint8_t force_ffu_mode; 2008 /** 2009 * Length of each horizontal line in us. 2010 */ 2011 uint32_t line_time_in_us; 2012 /** 2013 * FEC enable status in driver 2014 */ 2015 uint8_t fec_enable_status; 2016 /** 2017 * FEC re-enable delay when PSR exit. 2018 * unit is 100us, range form 0~255(0xFF). 2019 */ 2020 uint8_t fec_enable_delay_in100us; 2021 /** 2022 * PSR control version. 2023 */ 2024 uint8_t cmd_version; 2025 /** 2026 * Panel Instance. 2027 * Panel instance to identify which psr_state to use 2028 * Currently the support is only for 0 or 1 2029 */ 2030 uint8_t panel_inst; 2031 /* 2032 * DSC enable status in driver 2033 */ 2034 uint8_t dsc_enable_status; 2035 /* 2036 * Use FSM state for PSR power up/down 2037 */ 2038 uint8_t use_phy_fsm; 2039 /** 2040 * frame delay for frame re-lock 2041 */ 2042 uint8_t relock_delay_frame_cnt; 2043 /** 2044 * Explicit padding to 2 byte boundary. 2045 */ 2046 uint8_t pad3; 2047 /** 2048 * DSC Slice height. 2049 */ 2050 uint16_t dsc_slice_height; 2051 /** 2052 * Explicit padding to 4 byte boundary. 2053 */ 2054 uint16_t pad; 2055 }; 2056 2057 /** 2058 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2059 */ 2060 struct dmub_rb_cmd_psr_copy_settings { 2061 /** 2062 * Command header. 2063 */ 2064 struct dmub_cmd_header header; 2065 /** 2066 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2067 */ 2068 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2069 }; 2070 2071 /** 2072 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2073 */ 2074 struct dmub_cmd_psr_set_level_data { 2075 /** 2076 * 16-bit value dicated by driver that will enable/disable different functionality. 2077 */ 2078 uint16_t psr_level; 2079 /** 2080 * PSR control version. 2081 */ 2082 uint8_t cmd_version; 2083 /** 2084 * Panel Instance. 2085 * Panel instance to identify which psr_state to use 2086 * Currently the support is only for 0 or 1 2087 */ 2088 uint8_t panel_inst; 2089 }; 2090 2091 /** 2092 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2093 */ 2094 struct dmub_rb_cmd_psr_set_level { 2095 /** 2096 * Command header. 2097 */ 2098 struct dmub_cmd_header header; 2099 /** 2100 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2101 */ 2102 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2103 }; 2104 2105 struct dmub_rb_cmd_psr_enable_data { 2106 /** 2107 * PSR control version. 2108 */ 2109 uint8_t cmd_version; 2110 /** 2111 * Panel Instance. 2112 * Panel instance to identify which psr_state to use 2113 * Currently the support is only for 0 or 1 2114 */ 2115 uint8_t panel_inst; 2116 /** 2117 * Phy state to enter. 2118 * Values to use are defined in dmub_phy_fsm_state 2119 */ 2120 uint8_t phy_fsm_state; 2121 /** 2122 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2123 * Set this using enum phy_link_rate. 2124 * This does not support HDMI/DP2 for now. 2125 */ 2126 uint8_t phy_rate; 2127 }; 2128 2129 /** 2130 * Definition of a DMUB_CMD__PSR_ENABLE command. 2131 * PSR enable/disable is controlled using the sub_type. 2132 */ 2133 struct dmub_rb_cmd_psr_enable { 2134 /** 2135 * Command header. 2136 */ 2137 struct dmub_cmd_header header; 2138 2139 struct dmub_rb_cmd_psr_enable_data data; 2140 }; 2141 2142 /** 2143 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2144 */ 2145 struct dmub_cmd_psr_set_version_data { 2146 /** 2147 * PSR version that FW should implement. 2148 */ 2149 enum psr_version version; 2150 /** 2151 * PSR control version. 2152 */ 2153 uint8_t cmd_version; 2154 /** 2155 * Panel Instance. 2156 * Panel instance to identify which psr_state to use 2157 * Currently the support is only for 0 or 1 2158 */ 2159 uint8_t panel_inst; 2160 /** 2161 * Explicit padding to 4 byte boundary. 2162 */ 2163 uint8_t pad[2]; 2164 }; 2165 2166 /** 2167 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2168 */ 2169 struct dmub_rb_cmd_psr_set_version { 2170 /** 2171 * Command header. 2172 */ 2173 struct dmub_cmd_header header; 2174 /** 2175 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2176 */ 2177 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2178 }; 2179 2180 struct dmub_cmd_psr_force_static_data { 2181 /** 2182 * PSR control version. 2183 */ 2184 uint8_t cmd_version; 2185 /** 2186 * Panel Instance. 2187 * Panel instance to identify which psr_state to use 2188 * Currently the support is only for 0 or 1 2189 */ 2190 uint8_t panel_inst; 2191 /** 2192 * Explicit padding to 4 byte boundary. 2193 */ 2194 uint8_t pad[2]; 2195 }; 2196 2197 /** 2198 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2199 */ 2200 struct dmub_rb_cmd_psr_force_static { 2201 /** 2202 * Command header. 2203 */ 2204 struct dmub_cmd_header header; 2205 /** 2206 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2207 */ 2208 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2209 }; 2210 2211 /** 2212 * PSR SU debug flags. 2213 */ 2214 union dmub_psr_su_debug_flags { 2215 /** 2216 * PSR SU debug flags. 2217 */ 2218 struct { 2219 /** 2220 * Update dirty rect in SW only. 2221 */ 2222 uint8_t update_dirty_rect_only : 1; 2223 /** 2224 * Reset the cursor/plane state before processing the call. 2225 */ 2226 uint8_t reset_state : 1; 2227 } bitfields; 2228 2229 /** 2230 * Union for debug flags. 2231 */ 2232 uint32_t u32All; 2233 }; 2234 2235 /** 2236 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2237 * This triggers a selective update for PSR SU. 2238 */ 2239 struct dmub_cmd_update_dirty_rect_data { 2240 /** 2241 * Dirty rects from OS. 2242 */ 2243 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2244 /** 2245 * PSR SU debug flags. 2246 */ 2247 union dmub_psr_su_debug_flags debug_flags; 2248 /** 2249 * OTG HW instance. 2250 */ 2251 uint8_t pipe_idx; 2252 /** 2253 * Number of dirty rects. 2254 */ 2255 uint8_t dirty_rect_count; 2256 /** 2257 * PSR control version. 2258 */ 2259 uint8_t cmd_version; 2260 /** 2261 * Panel Instance. 2262 * Panel instance to identify which psr_state to use 2263 * Currently the support is only for 0 or 1 2264 */ 2265 uint8_t panel_inst; 2266 }; 2267 2268 /** 2269 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2270 */ 2271 struct dmub_rb_cmd_update_dirty_rect { 2272 /** 2273 * Command header. 2274 */ 2275 struct dmub_cmd_header header; 2276 /** 2277 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2278 */ 2279 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2280 }; 2281 2282 /** 2283 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2284 */ 2285 union dmub_reg_cursor_control_cfg { 2286 struct { 2287 uint32_t cur_enable: 1; 2288 uint32_t reser0: 3; 2289 uint32_t cur_2x_magnify: 1; 2290 uint32_t reser1: 3; 2291 uint32_t mode: 3; 2292 uint32_t reser2: 5; 2293 uint32_t pitch: 2; 2294 uint32_t reser3: 6; 2295 uint32_t line_per_chunk: 5; 2296 uint32_t reser4: 3; 2297 } bits; 2298 uint32_t raw; 2299 }; 2300 struct dmub_cursor_position_cache_hubp { 2301 union dmub_reg_cursor_control_cfg cur_ctl; 2302 union dmub_reg_position_cfg { 2303 struct { 2304 uint32_t cur_x_pos: 16; 2305 uint32_t cur_y_pos: 16; 2306 } bits; 2307 uint32_t raw; 2308 } position; 2309 union dmub_reg_hot_spot_cfg { 2310 struct { 2311 uint32_t hot_x: 16; 2312 uint32_t hot_y: 16; 2313 } bits; 2314 uint32_t raw; 2315 } hot_spot; 2316 union dmub_reg_dst_offset_cfg { 2317 struct { 2318 uint32_t dst_x_offset: 13; 2319 uint32_t reserved: 19; 2320 } bits; 2321 uint32_t raw; 2322 } dst_offset; 2323 }; 2324 2325 union dmub_reg_cur0_control_cfg { 2326 struct { 2327 uint32_t cur0_enable: 1; 2328 uint32_t expansion_mode: 1; 2329 uint32_t reser0: 1; 2330 uint32_t cur0_rom_en: 1; 2331 uint32_t mode: 3; 2332 uint32_t reserved: 25; 2333 } bits; 2334 uint32_t raw; 2335 }; 2336 struct dmub_cursor_position_cache_dpp { 2337 union dmub_reg_cur0_control_cfg cur0_ctl; 2338 }; 2339 struct dmub_cursor_position_cfg { 2340 struct dmub_cursor_position_cache_hubp pHubp; 2341 struct dmub_cursor_position_cache_dpp pDpp; 2342 uint8_t pipe_idx; 2343 /* 2344 * Padding is required. To be 4 Bytes Aligned. 2345 */ 2346 uint8_t padding[3]; 2347 }; 2348 2349 struct dmub_cursor_attribute_cache_hubp { 2350 uint32_t SURFACE_ADDR_HIGH; 2351 uint32_t SURFACE_ADDR; 2352 union dmub_reg_cursor_control_cfg cur_ctl; 2353 union dmub_reg_cursor_size_cfg { 2354 struct { 2355 uint32_t width: 16; 2356 uint32_t height: 16; 2357 } bits; 2358 uint32_t raw; 2359 } size; 2360 union dmub_reg_cursor_settings_cfg { 2361 struct { 2362 uint32_t dst_y_offset: 8; 2363 uint32_t chunk_hdl_adjust: 2; 2364 uint32_t reserved: 22; 2365 } bits; 2366 uint32_t raw; 2367 } settings; 2368 }; 2369 struct dmub_cursor_attribute_cache_dpp { 2370 union dmub_reg_cur0_control_cfg cur0_ctl; 2371 }; 2372 struct dmub_cursor_attributes_cfg { 2373 struct dmub_cursor_attribute_cache_hubp aHubp; 2374 struct dmub_cursor_attribute_cache_dpp aDpp; 2375 }; 2376 2377 struct dmub_cmd_update_cursor_payload0 { 2378 /** 2379 * Cursor dirty rects. 2380 */ 2381 struct dmub_rect cursor_rect; 2382 /** 2383 * PSR SU debug flags. 2384 */ 2385 union dmub_psr_su_debug_flags debug_flags; 2386 /** 2387 * Cursor enable/disable. 2388 */ 2389 uint8_t enable; 2390 /** 2391 * OTG HW instance. 2392 */ 2393 uint8_t pipe_idx; 2394 /** 2395 * PSR control version. 2396 */ 2397 uint8_t cmd_version; 2398 /** 2399 * Panel Instance. 2400 * Panel instance to identify which psr_state to use 2401 * Currently the support is only for 0 or 1 2402 */ 2403 uint8_t panel_inst; 2404 /** 2405 * Cursor Position Register. 2406 * Registers contains Hubp & Dpp modules 2407 */ 2408 struct dmub_cursor_position_cfg position_cfg; 2409 }; 2410 2411 struct dmub_cmd_update_cursor_payload1 { 2412 struct dmub_cursor_attributes_cfg attribute_cfg; 2413 }; 2414 2415 union dmub_cmd_update_cursor_info_data { 2416 struct dmub_cmd_update_cursor_payload0 payload0; 2417 struct dmub_cmd_update_cursor_payload1 payload1; 2418 }; 2419 /** 2420 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2421 */ 2422 struct dmub_rb_cmd_update_cursor_info { 2423 /** 2424 * Command header. 2425 */ 2426 struct dmub_cmd_header header; 2427 /** 2428 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2429 */ 2430 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2431 }; 2432 2433 /** 2434 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2435 */ 2436 struct dmub_cmd_psr_set_vtotal_data { 2437 /** 2438 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2439 */ 2440 uint16_t psr_vtotal_idle; 2441 /** 2442 * PSR control version. 2443 */ 2444 uint8_t cmd_version; 2445 /** 2446 * Panel Instance. 2447 * Panel instance to identify which psr_state to use 2448 * Currently the support is only for 0 or 1 2449 */ 2450 uint8_t panel_inst; 2451 /* 2452 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2453 */ 2454 uint16_t psr_vtotal_su; 2455 /** 2456 * Explicit padding to 4 byte boundary. 2457 */ 2458 uint8_t pad2[2]; 2459 }; 2460 2461 /** 2462 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2463 */ 2464 struct dmub_rb_cmd_psr_set_vtotal { 2465 /** 2466 * Command header. 2467 */ 2468 struct dmub_cmd_header header; 2469 /** 2470 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2471 */ 2472 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2473 }; 2474 2475 /** 2476 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2477 */ 2478 struct dmub_cmd_psr_set_power_opt_data { 2479 /** 2480 * PSR control version. 2481 */ 2482 uint8_t cmd_version; 2483 /** 2484 * Panel Instance. 2485 * Panel instance to identify which psr_state to use 2486 * Currently the support is only for 0 or 1 2487 */ 2488 uint8_t panel_inst; 2489 /** 2490 * Explicit padding to 4 byte boundary. 2491 */ 2492 uint8_t pad[2]; 2493 /** 2494 * PSR power option 2495 */ 2496 uint32_t power_opt; 2497 }; 2498 2499 /** 2500 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2501 */ 2502 struct dmub_rb_cmd_psr_set_power_opt { 2503 /** 2504 * Command header. 2505 */ 2506 struct dmub_cmd_header header; 2507 /** 2508 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2509 */ 2510 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2511 }; 2512 2513 /** 2514 * Set of HW components that can be locked. 2515 * 2516 * Note: If updating with more HW components, fields 2517 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2518 */ 2519 union dmub_hw_lock_flags { 2520 /** 2521 * Set of HW components that can be locked. 2522 */ 2523 struct { 2524 /** 2525 * Lock/unlock OTG master update lock. 2526 */ 2527 uint8_t lock_pipe : 1; 2528 /** 2529 * Lock/unlock cursor. 2530 */ 2531 uint8_t lock_cursor : 1; 2532 /** 2533 * Lock/unlock global update lock. 2534 */ 2535 uint8_t lock_dig : 1; 2536 /** 2537 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2538 */ 2539 uint8_t triple_buffer_lock : 1; 2540 } bits; 2541 2542 /** 2543 * Union for HW Lock flags. 2544 */ 2545 uint8_t u8All; 2546 }; 2547 2548 /** 2549 * Instances of HW to be locked. 2550 * 2551 * Note: If updating with more HW components, fields 2552 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2553 */ 2554 struct dmub_hw_lock_inst_flags { 2555 /** 2556 * OTG HW instance for OTG master update lock. 2557 */ 2558 uint8_t otg_inst; 2559 /** 2560 * OPP instance for cursor lock. 2561 */ 2562 uint8_t opp_inst; 2563 /** 2564 * OTG HW instance for global update lock. 2565 * TODO: Remove, and re-use otg_inst. 2566 */ 2567 uint8_t dig_inst; 2568 /** 2569 * Explicit pad to 4 byte boundary. 2570 */ 2571 uint8_t pad; 2572 }; 2573 2574 /** 2575 * Clients that can acquire the HW Lock Manager. 2576 * 2577 * Note: If updating with more clients, fields in 2578 * dmub_inbox0_cmd_lock_hw must be updated to match. 2579 */ 2580 enum hw_lock_client { 2581 /** 2582 * Driver is the client of HW Lock Manager. 2583 */ 2584 HW_LOCK_CLIENT_DRIVER = 0, 2585 /** 2586 * PSR SU is the client of HW Lock Manager. 2587 */ 2588 HW_LOCK_CLIENT_PSR_SU = 1, 2589 /** 2590 * Invalid client. 2591 */ 2592 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2593 }; 2594 2595 /** 2596 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2597 */ 2598 struct dmub_cmd_lock_hw_data { 2599 /** 2600 * Specifies the client accessing HW Lock Manager. 2601 */ 2602 enum hw_lock_client client; 2603 /** 2604 * HW instances to be locked. 2605 */ 2606 struct dmub_hw_lock_inst_flags inst_flags; 2607 /** 2608 * Which components to be locked. 2609 */ 2610 union dmub_hw_lock_flags hw_locks; 2611 /** 2612 * Specifies lock/unlock. 2613 */ 2614 uint8_t lock; 2615 /** 2616 * HW can be unlocked separately from releasing the HW Lock Mgr. 2617 * This flag is set if the client wishes to release the object. 2618 */ 2619 uint8_t should_release; 2620 /** 2621 * Explicit padding to 4 byte boundary. 2622 */ 2623 uint8_t pad; 2624 }; 2625 2626 /** 2627 * Definition of a DMUB_CMD__HW_LOCK command. 2628 * Command is used by driver and FW. 2629 */ 2630 struct dmub_rb_cmd_lock_hw { 2631 /** 2632 * Command header. 2633 */ 2634 struct dmub_cmd_header header; 2635 /** 2636 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2637 */ 2638 struct dmub_cmd_lock_hw_data lock_hw_data; 2639 }; 2640 2641 /** 2642 * ABM command sub-types. 2643 */ 2644 enum dmub_cmd_abm_type { 2645 /** 2646 * Initialize parameters for ABM algorithm. 2647 * Data is passed through an indirect buffer. 2648 */ 2649 DMUB_CMD__ABM_INIT_CONFIG = 0, 2650 /** 2651 * Set OTG and panel HW instance. 2652 */ 2653 DMUB_CMD__ABM_SET_PIPE = 1, 2654 /** 2655 * Set user requested backklight level. 2656 */ 2657 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2658 /** 2659 * Set ABM operating/aggression level. 2660 */ 2661 DMUB_CMD__ABM_SET_LEVEL = 3, 2662 /** 2663 * Set ambient light level. 2664 */ 2665 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2666 /** 2667 * Enable/disable fractional duty cycle for backlight PWM. 2668 */ 2669 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2670 2671 /** 2672 * unregister vertical interrupt after steady state is reached 2673 */ 2674 DMUB_CMD__ABM_PAUSE = 6, 2675 }; 2676 2677 /** 2678 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2679 * Requirements: 2680 * - Padded explicitly to 32-bit boundary. 2681 * - Must ensure this structure matches the one on driver-side, 2682 * otherwise it won't be aligned. 2683 */ 2684 struct abm_config_table { 2685 /** 2686 * Gamma curve thresholds, used for crgb conversion. 2687 */ 2688 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2689 /** 2690 * Gamma curve offsets, used for crgb conversion. 2691 */ 2692 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2693 /** 2694 * Gamma curve slopes, used for crgb conversion. 2695 */ 2696 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2697 /** 2698 * Custom backlight curve thresholds. 2699 */ 2700 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2701 /** 2702 * Custom backlight curve offsets. 2703 */ 2704 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2705 /** 2706 * Ambient light thresholds. 2707 */ 2708 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2709 /** 2710 * Minimum programmable backlight. 2711 */ 2712 uint16_t min_abm_backlight; // 122B 2713 /** 2714 * Minimum reduction values. 2715 */ 2716 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2717 /** 2718 * Maximum reduction values. 2719 */ 2720 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2721 /** 2722 * Bright positive gain. 2723 */ 2724 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2725 /** 2726 * Dark negative gain. 2727 */ 2728 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2729 /** 2730 * Hybrid factor. 2731 */ 2732 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2733 /** 2734 * Contrast factor. 2735 */ 2736 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2737 /** 2738 * Deviation gain. 2739 */ 2740 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2741 /** 2742 * Minimum knee. 2743 */ 2744 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2745 /** 2746 * Maximum knee. 2747 */ 2748 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2749 /** 2750 * Unused. 2751 */ 2752 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2753 /** 2754 * Explicit padding to 4 byte boundary. 2755 */ 2756 uint8_t pad3[3]; // 229B 2757 /** 2758 * Backlight ramp reduction. 2759 */ 2760 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2761 /** 2762 * Backlight ramp start. 2763 */ 2764 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2765 }; 2766 2767 /** 2768 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2769 */ 2770 struct dmub_cmd_abm_set_pipe_data { 2771 /** 2772 * OTG HW instance. 2773 */ 2774 uint8_t otg_inst; 2775 2776 /** 2777 * Panel Control HW instance. 2778 */ 2779 uint8_t panel_inst; 2780 2781 /** 2782 * Controls how ABM will interpret a set pipe or set level command. 2783 */ 2784 uint8_t set_pipe_option; 2785 2786 /** 2787 * Unused. 2788 * TODO: Remove. 2789 */ 2790 uint8_t ramping_boundary; 2791 }; 2792 2793 /** 2794 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2795 */ 2796 struct dmub_rb_cmd_abm_set_pipe { 2797 /** 2798 * Command header. 2799 */ 2800 struct dmub_cmd_header header; 2801 2802 /** 2803 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2804 */ 2805 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2806 }; 2807 2808 /** 2809 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2810 */ 2811 struct dmub_cmd_abm_set_backlight_data { 2812 /** 2813 * Number of frames to ramp to backlight user level. 2814 */ 2815 uint32_t frame_ramp; 2816 2817 /** 2818 * Requested backlight level from user. 2819 */ 2820 uint32_t backlight_user_level; 2821 2822 /** 2823 * ABM control version. 2824 */ 2825 uint8_t version; 2826 2827 /** 2828 * Panel Control HW instance mask. 2829 * Bit 0 is Panel Control HW instance 0. 2830 * Bit 1 is Panel Control HW instance 1. 2831 */ 2832 uint8_t panel_mask; 2833 2834 /** 2835 * Explicit padding to 4 byte boundary. 2836 */ 2837 uint8_t pad[2]; 2838 }; 2839 2840 /** 2841 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2842 */ 2843 struct dmub_rb_cmd_abm_set_backlight { 2844 /** 2845 * Command header. 2846 */ 2847 struct dmub_cmd_header header; 2848 2849 /** 2850 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2851 */ 2852 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2853 }; 2854 2855 /** 2856 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2857 */ 2858 struct dmub_cmd_abm_set_level_data { 2859 /** 2860 * Set current ABM operating/aggression level. 2861 */ 2862 uint32_t level; 2863 2864 /** 2865 * ABM control version. 2866 */ 2867 uint8_t version; 2868 2869 /** 2870 * Panel Control HW instance mask. 2871 * Bit 0 is Panel Control HW instance 0. 2872 * Bit 1 is Panel Control HW instance 1. 2873 */ 2874 uint8_t panel_mask; 2875 2876 /** 2877 * Explicit padding to 4 byte boundary. 2878 */ 2879 uint8_t pad[2]; 2880 }; 2881 2882 /** 2883 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2884 */ 2885 struct dmub_rb_cmd_abm_set_level { 2886 /** 2887 * Command header. 2888 */ 2889 struct dmub_cmd_header header; 2890 2891 /** 2892 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2893 */ 2894 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2895 }; 2896 2897 /** 2898 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2899 */ 2900 struct dmub_cmd_abm_set_ambient_level_data { 2901 /** 2902 * Ambient light sensor reading from OS. 2903 */ 2904 uint32_t ambient_lux; 2905 2906 /** 2907 * ABM control version. 2908 */ 2909 uint8_t version; 2910 2911 /** 2912 * Panel Control HW instance mask. 2913 * Bit 0 is Panel Control HW instance 0. 2914 * Bit 1 is Panel Control HW instance 1. 2915 */ 2916 uint8_t panel_mask; 2917 2918 /** 2919 * Explicit padding to 4 byte boundary. 2920 */ 2921 uint8_t pad[2]; 2922 }; 2923 2924 /** 2925 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2926 */ 2927 struct dmub_rb_cmd_abm_set_ambient_level { 2928 /** 2929 * Command header. 2930 */ 2931 struct dmub_cmd_header header; 2932 2933 /** 2934 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2935 */ 2936 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2937 }; 2938 2939 /** 2940 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2941 */ 2942 struct dmub_cmd_abm_set_pwm_frac_data { 2943 /** 2944 * Enable/disable fractional duty cycle for backlight PWM. 2945 * TODO: Convert to uint8_t. 2946 */ 2947 uint32_t fractional_pwm; 2948 2949 /** 2950 * ABM control version. 2951 */ 2952 uint8_t version; 2953 2954 /** 2955 * Panel Control HW instance mask. 2956 * Bit 0 is Panel Control HW instance 0. 2957 * Bit 1 is Panel Control HW instance 1. 2958 */ 2959 uint8_t panel_mask; 2960 2961 /** 2962 * Explicit padding to 4 byte boundary. 2963 */ 2964 uint8_t pad[2]; 2965 }; 2966 2967 /** 2968 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2969 */ 2970 struct dmub_rb_cmd_abm_set_pwm_frac { 2971 /** 2972 * Command header. 2973 */ 2974 struct dmub_cmd_header header; 2975 2976 /** 2977 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2978 */ 2979 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2980 }; 2981 2982 /** 2983 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2984 */ 2985 struct dmub_cmd_abm_init_config_data { 2986 /** 2987 * Location of indirect buffer used to pass init data to ABM. 2988 */ 2989 union dmub_addr src; 2990 2991 /** 2992 * Indirect buffer length. 2993 */ 2994 uint16_t bytes; 2995 2996 2997 /** 2998 * ABM control version. 2999 */ 3000 uint8_t version; 3001 3002 /** 3003 * Panel Control HW instance mask. 3004 * Bit 0 is Panel Control HW instance 0. 3005 * Bit 1 is Panel Control HW instance 1. 3006 */ 3007 uint8_t panel_mask; 3008 3009 /** 3010 * Explicit padding to 4 byte boundary. 3011 */ 3012 uint8_t pad[2]; 3013 }; 3014 3015 /** 3016 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3017 */ 3018 struct dmub_rb_cmd_abm_init_config { 3019 /** 3020 * Command header. 3021 */ 3022 struct dmub_cmd_header header; 3023 3024 /** 3025 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3026 */ 3027 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3028 }; 3029 3030 /** 3031 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3032 */ 3033 3034 struct dmub_cmd_abm_pause_data { 3035 3036 /** 3037 * Panel Control HW instance mask. 3038 * Bit 0 is Panel Control HW instance 0. 3039 * Bit 1 is Panel Control HW instance 1. 3040 */ 3041 uint8_t panel_mask; 3042 3043 /** 3044 * OTG hw instance 3045 */ 3046 uint8_t otg_inst; 3047 3048 /** 3049 * Enable or disable ABM pause 3050 */ 3051 uint8_t enable; 3052 3053 /** 3054 * Explicit padding to 4 byte boundary. 3055 */ 3056 uint8_t pad[1]; 3057 }; 3058 3059 /** 3060 * Definition of a DMUB_CMD__ABM_PAUSE command. 3061 */ 3062 struct dmub_rb_cmd_abm_pause { 3063 /** 3064 * Command header. 3065 */ 3066 struct dmub_cmd_header header; 3067 3068 /** 3069 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3070 */ 3071 struct dmub_cmd_abm_pause_data abm_pause_data; 3072 }; 3073 3074 /** 3075 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3076 */ 3077 struct dmub_cmd_query_feature_caps_data { 3078 /** 3079 * DMUB feature capabilities. 3080 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3081 */ 3082 struct dmub_feature_caps feature_caps; 3083 }; 3084 3085 /** 3086 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3087 */ 3088 struct dmub_rb_cmd_query_feature_caps { 3089 /** 3090 * Command header. 3091 */ 3092 struct dmub_cmd_header header; 3093 /** 3094 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3095 */ 3096 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3097 }; 3098 3099 /** 3100 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3101 */ 3102 struct dmub_cmd_visual_confirm_color_data { 3103 /** 3104 * DMUB feature capabilities. 3105 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3106 */ 3107 struct dmub_visual_confirm_color visual_confirm_color; 3108 }; 3109 3110 /** 3111 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3112 */ 3113 struct dmub_rb_cmd_get_visual_confirm_color { 3114 /** 3115 * Command header. 3116 */ 3117 struct dmub_cmd_header header; 3118 /** 3119 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3120 */ 3121 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3122 }; 3123 3124 struct dmub_optc_state { 3125 uint32_t v_total_max; 3126 uint32_t v_total_min; 3127 uint32_t tg_inst; 3128 }; 3129 3130 struct dmub_rb_cmd_drr_update { 3131 struct dmub_cmd_header header; 3132 struct dmub_optc_state dmub_optc_state_req; 3133 }; 3134 3135 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3136 uint32_t pix_clk_100hz; 3137 uint8_t max_ramp_step; 3138 uint8_t pipes; 3139 uint8_t min_refresh_in_hz; 3140 uint8_t pipe_count; 3141 uint8_t pipe_index[4]; 3142 }; 3143 3144 struct dmub_cmd_fw_assisted_mclk_switch_config { 3145 uint8_t fams_enabled; 3146 uint8_t visual_confirm_enabled; 3147 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3148 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3149 }; 3150 3151 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3152 struct dmub_cmd_header header; 3153 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3154 }; 3155 3156 /** 3157 * enum dmub_cmd_panel_cntl_type - Panel control command. 3158 */ 3159 enum dmub_cmd_panel_cntl_type { 3160 /** 3161 * Initializes embedded panel hardware blocks. 3162 */ 3163 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3164 /** 3165 * Queries backlight info for the embedded panel. 3166 */ 3167 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3168 }; 3169 3170 /** 3171 * struct dmub_cmd_panel_cntl_data - Panel control data. 3172 */ 3173 struct dmub_cmd_panel_cntl_data { 3174 uint32_t inst; /**< panel instance */ 3175 uint32_t current_backlight; /* in/out */ 3176 uint32_t bl_pwm_cntl; /* in/out */ 3177 uint32_t bl_pwm_period_cntl; /* in/out */ 3178 uint32_t bl_pwm_ref_div1; /* in/out */ 3179 uint8_t is_backlight_on : 1; /* in/out */ 3180 uint8_t is_powered_on : 1; /* in/out */ 3181 uint8_t padding[3]; 3182 uint32_t bl_pwm_ref_div2; /* in/out */ 3183 uint8_t reserved[4]; 3184 }; 3185 3186 /** 3187 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3188 */ 3189 struct dmub_rb_cmd_panel_cntl { 3190 struct dmub_cmd_header header; /**< header */ 3191 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3192 }; 3193 3194 /** 3195 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3196 */ 3197 struct dmub_cmd_lvtma_control_data { 3198 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3199 uint8_t bypass_panel_control_wait; 3200 uint8_t reserved_0[2]; /**< For future use */ 3201 uint8_t panel_inst; /**< LVTMA control instance */ 3202 uint8_t reserved_1[3]; /**< For future use */ 3203 }; 3204 3205 /** 3206 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3207 */ 3208 struct dmub_rb_cmd_lvtma_control { 3209 /** 3210 * Command header. 3211 */ 3212 struct dmub_cmd_header header; 3213 /** 3214 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3215 */ 3216 struct dmub_cmd_lvtma_control_data data; 3217 }; 3218 3219 /** 3220 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3221 */ 3222 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3223 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3224 uint8_t is_usb; /**< is phy is usb */ 3225 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3226 uint8_t is_dp4; /**< is dp in 4 lane */ 3227 }; 3228 3229 /** 3230 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3231 */ 3232 struct dmub_rb_cmd_transmitter_query_dp_alt { 3233 struct dmub_cmd_header header; /**< header */ 3234 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3235 }; 3236 3237 /** 3238 * Maximum number of bytes a chunk sent to DMUB for parsing 3239 */ 3240 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3241 3242 /** 3243 * Represent a chunk of CEA blocks sent to DMUB for parsing 3244 */ 3245 struct dmub_cmd_send_edid_cea { 3246 uint16_t offset; /**< offset into the CEA block */ 3247 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3248 uint16_t cea_total_length; /**< total length of the CEA block */ 3249 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3250 uint8_t pad[3]; /**< padding and for future expansion */ 3251 }; 3252 3253 /** 3254 * Result of VSDB parsing from CEA block 3255 */ 3256 struct dmub_cmd_edid_cea_amd_vsdb { 3257 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3258 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3259 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3260 uint16_t min_frame_rate; /**< Maximum frame rate */ 3261 uint16_t max_frame_rate; /**< Minimum frame rate */ 3262 }; 3263 3264 /** 3265 * Result of sending a CEA chunk 3266 */ 3267 struct dmub_cmd_edid_cea_ack { 3268 uint16_t offset; /**< offset of the chunk into the CEA block */ 3269 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3270 uint8_t pad; /**< padding and for future expansion */ 3271 }; 3272 3273 /** 3274 * Specify whether the result is an ACK/NACK or the parsing has finished 3275 */ 3276 enum dmub_cmd_edid_cea_reply_type { 3277 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3278 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3279 }; 3280 3281 /** 3282 * Definition of a DMUB_CMD__EDID_CEA command. 3283 */ 3284 struct dmub_rb_cmd_edid_cea { 3285 struct dmub_cmd_header header; /**< Command header */ 3286 union dmub_cmd_edid_cea_data { 3287 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3288 struct dmub_cmd_edid_cea_output { /**< output with results */ 3289 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3290 union { 3291 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3292 struct dmub_cmd_edid_cea_ack ack; 3293 }; 3294 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3295 } data; /**< Command data */ 3296 3297 }; 3298 3299 /** 3300 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3301 */ 3302 struct dmub_cmd_cable_id_input { 3303 uint8_t phy_inst; /**< phy inst for cable id data */ 3304 }; 3305 3306 /** 3307 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3308 */ 3309 struct dmub_cmd_cable_id_output { 3310 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3311 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3312 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3313 uint8_t RESERVED :2; /**< reserved means not defined */ 3314 }; 3315 3316 /** 3317 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3318 */ 3319 struct dmub_rb_cmd_get_usbc_cable_id { 3320 struct dmub_cmd_header header; /**< Command header */ 3321 /** 3322 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3323 */ 3324 union dmub_cmd_cable_id_data { 3325 struct dmub_cmd_cable_id_input input; /**< Input */ 3326 struct dmub_cmd_cable_id_output output; /**< Output */ 3327 uint8_t output_raw; /**< Raw data output */ 3328 } data; 3329 }; 3330 3331 /** 3332 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3333 */ 3334 enum dmub_cmd_secure_display_type { 3335 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3336 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3337 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3338 }; 3339 3340 /** 3341 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3342 */ 3343 struct dmub_rb_cmd_secure_display { 3344 struct dmub_cmd_header header; 3345 /** 3346 * Data passed from driver to dmub firmware. 3347 */ 3348 struct dmub_cmd_roi_info { 3349 uint16_t x_start; 3350 uint16_t x_end; 3351 uint16_t y_start; 3352 uint16_t y_end; 3353 uint8_t otg_id; 3354 uint8_t phy_id; 3355 } roi_info; 3356 }; 3357 3358 /** 3359 * union dmub_rb_cmd - DMUB inbox command. 3360 */ 3361 union dmub_rb_cmd { 3362 /** 3363 * Elements shared with all commands. 3364 */ 3365 struct dmub_rb_cmd_common cmd_common; 3366 /** 3367 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3368 */ 3369 struct dmub_rb_cmd_read_modify_write read_modify_write; 3370 /** 3371 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3372 */ 3373 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3374 /** 3375 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3376 */ 3377 struct dmub_rb_cmd_burst_write burst_write; 3378 /** 3379 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3380 */ 3381 struct dmub_rb_cmd_reg_wait reg_wait; 3382 /** 3383 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3384 */ 3385 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3386 /** 3387 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3388 */ 3389 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3390 /** 3391 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3392 */ 3393 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3394 /** 3395 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3396 */ 3397 struct dmub_rb_cmd_dpphy_init dpphy_init; 3398 /** 3399 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3400 */ 3401 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3402 /** 3403 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3404 */ 3405 struct dmub_rb_cmd_domain_control domain_control; 3406 /** 3407 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3408 */ 3409 struct dmub_rb_cmd_psr_set_version psr_set_version; 3410 /** 3411 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3412 */ 3413 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3414 /** 3415 * Definition of a DMUB_CMD__PSR_ENABLE command. 3416 */ 3417 struct dmub_rb_cmd_psr_enable psr_enable; 3418 /** 3419 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3420 */ 3421 struct dmub_rb_cmd_psr_set_level psr_set_level; 3422 /** 3423 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3424 */ 3425 struct dmub_rb_cmd_psr_force_static psr_force_static; 3426 /** 3427 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3428 */ 3429 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3430 /** 3431 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3432 */ 3433 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3434 /** 3435 * Definition of a DMUB_CMD__HW_LOCK command. 3436 * Command is used by driver and FW. 3437 */ 3438 struct dmub_rb_cmd_lock_hw lock_hw; 3439 /** 3440 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3441 */ 3442 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3443 /** 3444 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3445 */ 3446 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3447 /** 3448 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3449 */ 3450 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3451 /** 3452 * Definition of a DMUB_CMD__MALL command. 3453 */ 3454 struct dmub_rb_cmd_mall mall; 3455 /** 3456 * Definition of a DMUB_CMD__CAB command. 3457 */ 3458 struct dmub_rb_cmd_cab_for_ss cab; 3459 3460 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3461 3462 /** 3463 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3464 */ 3465 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3466 3467 /** 3468 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3469 */ 3470 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3471 3472 /** 3473 * Definition of DMUB_CMD__PANEL_CNTL commands. 3474 */ 3475 struct dmub_rb_cmd_panel_cntl panel_cntl; 3476 /** 3477 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3478 */ 3479 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3480 3481 /** 3482 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3483 */ 3484 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3485 3486 /** 3487 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3488 */ 3489 struct dmub_rb_cmd_abm_set_level abm_set_level; 3490 3491 /** 3492 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3493 */ 3494 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3495 3496 /** 3497 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3498 */ 3499 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3500 3501 /** 3502 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3503 */ 3504 struct dmub_rb_cmd_abm_init_config abm_init_config; 3505 3506 /** 3507 * Definition of a DMUB_CMD__ABM_PAUSE command. 3508 */ 3509 struct dmub_rb_cmd_abm_pause abm_pause; 3510 3511 /** 3512 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3513 */ 3514 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3515 3516 /** 3517 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3518 */ 3519 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3520 3521 /** 3522 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3523 */ 3524 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3525 3526 /** 3527 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3528 */ 3529 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3530 struct dmub_rb_cmd_drr_update drr_update; 3531 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3532 3533 /** 3534 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3535 */ 3536 struct dmub_rb_cmd_lvtma_control lvtma_control; 3537 /** 3538 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3539 */ 3540 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3541 /** 3542 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3543 */ 3544 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3545 /** 3546 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3547 */ 3548 struct dmub_rb_cmd_set_config_access set_config_access; 3549 /** 3550 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3551 */ 3552 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3553 /** 3554 * Definition of a DMUB_CMD__EDID_CEA command. 3555 */ 3556 struct dmub_rb_cmd_edid_cea edid_cea; 3557 /** 3558 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3559 */ 3560 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3561 3562 /** 3563 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3564 */ 3565 struct dmub_rb_cmd_query_hpd_state query_hpd; 3566 /** 3567 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3568 */ 3569 struct dmub_rb_cmd_secure_display secure_display; 3570 3571 /** 3572 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3573 */ 3574 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3575 /** 3576 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 3577 */ 3578 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 3579 }; 3580 3581 /** 3582 * union dmub_rb_out_cmd - Outbox command 3583 */ 3584 union dmub_rb_out_cmd { 3585 /** 3586 * Parameters common to every command. 3587 */ 3588 struct dmub_rb_cmd_common cmd_common; 3589 /** 3590 * AUX reply command. 3591 */ 3592 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3593 /** 3594 * HPD notify command. 3595 */ 3596 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3597 /** 3598 * SET_CONFIG reply command. 3599 */ 3600 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3601 /** 3602 * DPIA notification command. 3603 */ 3604 struct dmub_rb_cmd_dpia_notification dpia_notification; 3605 }; 3606 #pragma pack(pop) 3607 3608 3609 //============================================================================== 3610 //</DMUB_CMD>=================================================================== 3611 //============================================================================== 3612 //< DMUB_RB>==================================================================== 3613 //============================================================================== 3614 3615 #if defined(__cplusplus) 3616 extern "C" { 3617 #endif 3618 3619 /** 3620 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3621 */ 3622 struct dmub_rb_init_params { 3623 void *ctx; /**< Caller provided context pointer */ 3624 void *base_address; /**< CPU base address for ring's data */ 3625 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3626 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3627 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3628 }; 3629 3630 /** 3631 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3632 */ 3633 struct dmub_rb { 3634 void *base_address; /**< CPU address for the ring's data */ 3635 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3636 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3637 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3638 3639 void *ctx; /**< Caller provided context pointer */ 3640 void *dmub; /**< Pointer to the DMUB interface */ 3641 }; 3642 3643 /** 3644 * @brief Checks if the ringbuffer is empty. 3645 * 3646 * @param rb DMUB Ringbuffer 3647 * @return true if empty 3648 * @return false otherwise 3649 */ 3650 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3651 { 3652 return (rb->wrpt == rb->rptr); 3653 } 3654 3655 /** 3656 * @brief Checks if the ringbuffer is full 3657 * 3658 * @param rb DMUB Ringbuffer 3659 * @return true if full 3660 * @return false otherwise 3661 */ 3662 static inline bool dmub_rb_full(struct dmub_rb *rb) 3663 { 3664 uint32_t data_count; 3665 3666 if (rb->wrpt >= rb->rptr) 3667 data_count = rb->wrpt - rb->rptr; 3668 else 3669 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3670 3671 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3672 } 3673 3674 /** 3675 * @brief Pushes a command into the ringbuffer 3676 * 3677 * @param rb DMUB ringbuffer 3678 * @param cmd The command to push 3679 * @return true if the ringbuffer was not full 3680 * @return false otherwise 3681 */ 3682 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3683 const union dmub_rb_cmd *cmd) 3684 { 3685 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3686 const uint64_t *src = (const uint64_t *)cmd; 3687 uint8_t i; 3688 3689 if (dmub_rb_full(rb)) 3690 return false; 3691 3692 // copying data 3693 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3694 *dst++ = *src++; 3695 3696 rb->wrpt += DMUB_RB_CMD_SIZE; 3697 3698 if (rb->wrpt >= rb->capacity) 3699 rb->wrpt %= rb->capacity; 3700 3701 return true; 3702 } 3703 3704 /** 3705 * @brief Pushes a command into the DMUB outbox ringbuffer 3706 * 3707 * @param rb DMUB outbox ringbuffer 3708 * @param cmd Outbox command 3709 * @return true if not full 3710 * @return false otherwise 3711 */ 3712 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3713 const union dmub_rb_out_cmd *cmd) 3714 { 3715 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3716 const uint8_t *src = (const uint8_t *)cmd; 3717 3718 if (dmub_rb_full(rb)) 3719 return false; 3720 3721 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3722 3723 rb->wrpt += DMUB_RB_CMD_SIZE; 3724 3725 if (rb->wrpt >= rb->capacity) 3726 rb->wrpt %= rb->capacity; 3727 3728 return true; 3729 } 3730 3731 /** 3732 * @brief Returns the next unprocessed command in the ringbuffer. 3733 * 3734 * @param rb DMUB ringbuffer 3735 * @param cmd The command to return 3736 * @return true if not empty 3737 * @return false otherwise 3738 */ 3739 static inline bool dmub_rb_front(struct dmub_rb *rb, 3740 union dmub_rb_cmd **cmd) 3741 { 3742 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3743 3744 if (dmub_rb_empty(rb)) 3745 return false; 3746 3747 *cmd = (union dmub_rb_cmd *)rb_cmd; 3748 3749 return true; 3750 } 3751 3752 /** 3753 * @brief Determines the next ringbuffer offset. 3754 * 3755 * @param rb DMUB inbox ringbuffer 3756 * @param num_cmds Number of commands 3757 * @param next_rptr The next offset in the ringbuffer 3758 */ 3759 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3760 uint32_t num_cmds, 3761 uint32_t *next_rptr) 3762 { 3763 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3764 3765 if (*next_rptr >= rb->capacity) 3766 *next_rptr %= rb->capacity; 3767 } 3768 3769 /** 3770 * @brief Returns a pointer to a command in the inbox. 3771 * 3772 * @param rb DMUB inbox ringbuffer 3773 * @param cmd The inbox command to return 3774 * @param rptr The ringbuffer offset 3775 * @return true if not empty 3776 * @return false otherwise 3777 */ 3778 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3779 union dmub_rb_cmd **cmd, 3780 uint32_t rptr) 3781 { 3782 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3783 3784 if (dmub_rb_empty(rb)) 3785 return false; 3786 3787 *cmd = (union dmub_rb_cmd *)rb_cmd; 3788 3789 return true; 3790 } 3791 3792 /** 3793 * @brief Returns the next unprocessed command in the outbox. 3794 * 3795 * @param rb DMUB outbox ringbuffer 3796 * @param cmd The outbox command to return 3797 * @return true if not empty 3798 * @return false otherwise 3799 */ 3800 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3801 union dmub_rb_out_cmd *cmd) 3802 { 3803 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3804 uint64_t *dst = (uint64_t *)cmd; 3805 uint8_t i; 3806 3807 if (dmub_rb_empty(rb)) 3808 return false; 3809 3810 // copying data 3811 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3812 *dst++ = *src++; 3813 3814 return true; 3815 } 3816 3817 /** 3818 * @brief Removes the front entry in the ringbuffer. 3819 * 3820 * @param rb DMUB ringbuffer 3821 * @return true if the command was removed 3822 * @return false if there were no commands 3823 */ 3824 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3825 { 3826 if (dmub_rb_empty(rb)) 3827 return false; 3828 3829 rb->rptr += DMUB_RB_CMD_SIZE; 3830 3831 if (rb->rptr >= rb->capacity) 3832 rb->rptr %= rb->capacity; 3833 3834 return true; 3835 } 3836 3837 /** 3838 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3839 * 3840 * Avoids a race condition where DMCUB accesses memory while 3841 * there are still writes in flight to framebuffer. 3842 * 3843 * @param rb DMUB ringbuffer 3844 */ 3845 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3846 { 3847 uint32_t rptr = rb->rptr; 3848 uint32_t wptr = rb->wrpt; 3849 3850 while (rptr != wptr) { 3851 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3852 uint8_t i; 3853 3854 /* Don't remove this. 3855 * The contents need to actually be read from the ring buffer 3856 * for this function to be effective. 3857 */ 3858 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3859 (void)READ_ONCE(*data++); 3860 3861 rptr += DMUB_RB_CMD_SIZE; 3862 if (rptr >= rb->capacity) 3863 rptr %= rb->capacity; 3864 } 3865 } 3866 3867 /** 3868 * @brief Initializes a DMCUB ringbuffer 3869 * 3870 * @param rb DMUB ringbuffer 3871 * @param init_params initial configuration for the ringbuffer 3872 */ 3873 static inline void dmub_rb_init(struct dmub_rb *rb, 3874 struct dmub_rb_init_params *init_params) 3875 { 3876 rb->base_address = init_params->base_address; 3877 rb->capacity = init_params->capacity; 3878 rb->rptr = init_params->read_ptr; 3879 rb->wrpt = init_params->write_ptr; 3880 } 3881 3882 /** 3883 * @brief Copies output data from in/out commands into the given command. 3884 * 3885 * @param rb DMUB ringbuffer 3886 * @param cmd Command to copy data into 3887 */ 3888 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3889 union dmub_rb_cmd *cmd) 3890 { 3891 // Copy rb entry back into command 3892 uint8_t *rd_ptr = (rb->rptr == 0) ? 3893 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3894 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3895 3896 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3897 } 3898 3899 #if defined(__cplusplus) 3900 } 3901 #endif 3902 3903 //============================================================================== 3904 //</DMUB_RB>==================================================================== 3905 //============================================================================== 3906 3907 #endif /* _DMUB_CMD_H_ */ 3908