1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 229 /** 230 * Back to back flip, therefore cannot power down PHY 231 */ 232 uint32_t back_to_back_flip : 1; 233 234 } bitfields; 235 236 /** 237 * Union for debug flags. 238 */ 239 uint32_t u32All; 240 }; 241 242 /** 243 * DMUB visual confirm color 244 */ 245 struct dmub_feature_caps { 246 /** 247 * Max PSR version supported by FW. 248 */ 249 uint8_t psr; 250 uint8_t fw_assisted_mclk_switch; 251 uint8_t reserved[6]; 252 }; 253 254 struct dmub_visual_confirm_color { 255 /** 256 * Maximum 10 bits color value 257 */ 258 uint16_t color_r_cr; 259 uint16_t color_g_y; 260 uint16_t color_b_cb; 261 uint16_t panel_inst; 262 }; 263 264 #if defined(__cplusplus) 265 } 266 #endif 267 268 //============================================================================== 269 //</DMUB_TYPES>================================================================= 270 //============================================================================== 271 //< DMUB_META>================================================================== 272 //============================================================================== 273 #pragma pack(push, 1) 274 275 /* Magic value for identifying dmub_fw_meta_info */ 276 #define DMUB_FW_META_MAGIC 0x444D5542 277 278 /* Offset from the end of the file to the dmub_fw_meta_info */ 279 #define DMUB_FW_META_OFFSET 0x24 280 281 /** 282 * struct dmub_fw_meta_info - metadata associated with fw binary 283 * 284 * NOTE: This should be considered a stable API. Fields should 285 * not be repurposed or reordered. New fields should be 286 * added instead to extend the structure. 287 * 288 * @magic_value: magic value identifying DMUB firmware meta info 289 * @fw_region_size: size of the firmware state region 290 * @trace_buffer_size: size of the tracebuffer region 291 * @fw_version: the firmware version information 292 * @dal_fw: 1 if the firmware is DAL 293 */ 294 struct dmub_fw_meta_info { 295 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296 uint32_t fw_region_size; /**< size of the firmware state region */ 297 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298 uint32_t fw_version; /**< the firmware version information */ 299 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300 uint8_t reserved[3]; /**< padding bits */ 301 }; 302 303 /** 304 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305 */ 306 union dmub_fw_meta { 307 struct dmub_fw_meta_info info; /**< metadata info */ 308 uint8_t reserved[64]; /**< padding bits */ 309 }; 310 311 #pragma pack(pop) 312 313 //============================================================================== 314 //< DMUB Trace Buffer>================================================================ 315 //============================================================================== 316 /** 317 * dmub_trace_code_t - firmware trace code, 32-bits 318 */ 319 typedef uint32_t dmub_trace_code_t; 320 321 /** 322 * struct dmcub_trace_buf_entry - Firmware trace entry 323 */ 324 struct dmcub_trace_buf_entry { 325 dmub_trace_code_t trace_code; /**< trace code for the event */ 326 uint32_t tick_count; /**< the tick count at time of trace */ 327 uint32_t param0; /**< trace defined parameter 0 */ 328 uint32_t param1; /**< trace defined parameter 1 */ 329 }; 330 331 //============================================================================== 332 //< DMUB_STATUS>================================================================ 333 //============================================================================== 334 335 /** 336 * DMCUB scratch registers can be used to determine firmware status. 337 * Current scratch register usage is as follows: 338 * 339 * SCRATCH0: FW Boot Status register 340 * SCRATCH5: LVTMA Status Register 341 * SCRATCH15: FW Boot Options register 342 */ 343 344 /** 345 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346 */ 347 union dmub_fw_boot_status { 348 struct { 349 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 353 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 354 uint32_t reserved : 1; 355 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 356 357 } bits; /**< status bits */ 358 uint32_t all; /**< 32-bit access to status bits */ 359 }; 360 361 /** 362 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363 */ 364 enum dmub_fw_boot_status_bit { 365 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 369 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 370 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371 }; 372 373 /* Register bit definition for SCRATCH5 */ 374 union dmub_lvtma_status { 375 struct { 376 uint32_t psp_ok : 1; 377 uint32_t edp_on : 1; 378 uint32_t reserved : 30; 379 } bits; 380 uint32_t all; 381 }; 382 383 enum dmub_lvtma_status_bit { 384 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386 }; 387 388 /** 389 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390 */ 391 union dmub_fw_boot_options { 392 struct { 393 uint32_t pemu_env : 1; /**< 1 if PEMU */ 394 uint32_t fpga_env : 1; /**< 1 if FPGA */ 395 uint32_t optimized_init : 1; /**< 1 if optimized init */ 396 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 401 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 402 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 403 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 404 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 405 uint32_t power_optimization: 1; 406 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 407 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 409 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 410 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 411 412 uint32_t reserved : 15; /**< reserved */ 413 } bits; /**< boot bits */ 414 uint32_t all; /**< 32-bit access to bits */ 415 }; 416 417 enum dmub_fw_boot_options_bit { 418 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 419 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 420 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 421 }; 422 423 //============================================================================== 424 //</DMUB_STATUS>================================================================ 425 //============================================================================== 426 //< DMUB_VBIOS>================================================================= 427 //============================================================================== 428 429 /* 430 * enum dmub_cmd_vbios_type - VBIOS commands. 431 * 432 * Command IDs should be treated as stable ABI. 433 * Do not reuse or modify IDs. 434 */ 435 enum dmub_cmd_vbios_type { 436 /** 437 * Configures the DIG encoder. 438 */ 439 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 440 /** 441 * Controls the PHY. 442 */ 443 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 444 /** 445 * Sets the pixel clock/symbol clock. 446 */ 447 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 448 /** 449 * Enables or disables power gating. 450 */ 451 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 452 /** 453 * Controls embedded panels. 454 */ 455 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 456 /** 457 * Query DP alt status on a transmitter. 458 */ 459 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 460 }; 461 462 //============================================================================== 463 //</DMUB_VBIOS>================================================================= 464 //============================================================================== 465 //< DMUB_GPINT>================================================================= 466 //============================================================================== 467 468 /** 469 * The shifts and masks below may alternatively be used to format and read 470 * the command register bits. 471 */ 472 473 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 474 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 475 476 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 477 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 478 479 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 480 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 481 482 /** 483 * Command responses. 484 */ 485 486 /** 487 * Return response for DMUB_GPINT__STOP_FW command. 488 */ 489 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 490 491 /** 492 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 493 */ 494 union dmub_gpint_data_register { 495 struct { 496 uint32_t param : 16; /**< 16-bit parameter */ 497 uint32_t command_code : 12; /**< GPINT command */ 498 uint32_t status : 4; /**< Command status bit */ 499 } bits; /**< GPINT bit access */ 500 uint32_t all; /**< GPINT 32-bit access */ 501 }; 502 503 /* 504 * enum dmub_gpint_command - GPINT command to DMCUB FW 505 * 506 * Command IDs should be treated as stable ABI. 507 * Do not reuse or modify IDs. 508 */ 509 enum dmub_gpint_command { 510 /** 511 * Invalid command, ignored. 512 */ 513 DMUB_GPINT__INVALID_COMMAND = 0, 514 /** 515 * DESC: Queries the firmware version. 516 * RETURN: Firmware version. 517 */ 518 DMUB_GPINT__GET_FW_VERSION = 1, 519 /** 520 * DESC: Halts the firmware. 521 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 522 */ 523 DMUB_GPINT__STOP_FW = 2, 524 /** 525 * DESC: Get PSR state from FW. 526 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 527 */ 528 DMUB_GPINT__GET_PSR_STATE = 7, 529 /** 530 * DESC: Notifies DMCUB of the currently active streams. 531 * ARGS: Stream mask, 1 bit per active stream index. 532 */ 533 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 534 /** 535 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 536 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 537 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 538 * RETURN: PSR residency in milli-percent. 539 */ 540 DMUB_GPINT__PSR_RESIDENCY = 9, 541 542 /** 543 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 544 */ 545 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 546 }; 547 548 /** 549 * INBOX0 generic command definition 550 */ 551 union dmub_inbox0_cmd_common { 552 struct { 553 uint32_t command_code: 8; /**< INBOX0 command code */ 554 uint32_t param: 24; /**< 24-bit parameter */ 555 } bits; 556 uint32_t all; 557 }; 558 559 /** 560 * INBOX0 hw_lock command definition 561 */ 562 union dmub_inbox0_cmd_lock_hw { 563 struct { 564 uint32_t command_code: 8; 565 566 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 567 uint32_t hw_lock_client: 2; 568 569 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 570 uint32_t otg_inst: 3; 571 uint32_t opp_inst: 3; 572 uint32_t dig_inst: 3; 573 574 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 575 uint32_t lock_pipe: 1; 576 uint32_t lock_cursor: 1; 577 uint32_t lock_dig: 1; 578 uint32_t triple_buffer_lock: 1; 579 580 uint32_t lock: 1; /**< Lock */ 581 uint32_t should_release: 1; /**< Release */ 582 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 583 } bits; 584 uint32_t all; 585 }; 586 587 union dmub_inbox0_data_register { 588 union dmub_inbox0_cmd_common inbox0_cmd_common; 589 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 590 }; 591 592 enum dmub_inbox0_command { 593 /** 594 * DESC: Invalid command, ignored. 595 */ 596 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 597 /** 598 * DESC: Notification to acquire/release HW lock 599 * ARGS: 600 */ 601 DMUB_INBOX0_CMD__HW_LOCK = 1, 602 }; 603 //============================================================================== 604 //</DMUB_GPINT>================================================================= 605 //============================================================================== 606 //< DMUB_CMD>=================================================================== 607 //============================================================================== 608 609 /** 610 * Size in bytes of each DMUB command. 611 */ 612 #define DMUB_RB_CMD_SIZE 64 613 614 /** 615 * Maximum number of items in the DMUB ringbuffer. 616 */ 617 #define DMUB_RB_MAX_ENTRY 128 618 619 /** 620 * Ringbuffer size in bytes. 621 */ 622 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 623 624 /** 625 * REG_SET mask for reg offload. 626 */ 627 #define REG_SET_MASK 0xFFFF 628 629 /* 630 * enum dmub_cmd_type - DMUB inbox command. 631 * 632 * Command IDs should be treated as stable ABI. 633 * Do not reuse or modify IDs. 634 */ 635 enum dmub_cmd_type { 636 /** 637 * Invalid command. 638 */ 639 DMUB_CMD__NULL = 0, 640 /** 641 * Read modify write register sequence offload. 642 */ 643 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 644 /** 645 * Field update register sequence offload. 646 */ 647 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 648 /** 649 * Burst write sequence offload. 650 */ 651 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 652 /** 653 * Reg wait sequence offload. 654 */ 655 DMUB_CMD__REG_REG_WAIT = 4, 656 /** 657 * Workaround to avoid HUBP underflow during NV12 playback. 658 */ 659 DMUB_CMD__PLAT_54186_WA = 5, 660 /** 661 * Command type used to query FW feature caps. 662 */ 663 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 664 /** 665 * Command type used to get visual confirm color. 666 */ 667 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 668 /** 669 * Command type used for all PSR commands. 670 */ 671 DMUB_CMD__PSR = 64, 672 /** 673 * Command type used for all MALL commands. 674 */ 675 DMUB_CMD__MALL = 65, 676 /** 677 * Command type used for all ABM commands. 678 */ 679 DMUB_CMD__ABM = 66, 680 /** 681 * Command type used to update dirty rects in FW. 682 */ 683 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 684 /** 685 * Command type used to update cursor info in FW. 686 */ 687 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 688 /** 689 * Command type used for HW locking in FW. 690 */ 691 DMUB_CMD__HW_LOCK = 69, 692 /** 693 * Command type used to access DP AUX. 694 */ 695 DMUB_CMD__DP_AUX_ACCESS = 70, 696 /** 697 * Command type used for OUTBOX1 notification enable 698 */ 699 DMUB_CMD__OUTBOX1_ENABLE = 71, 700 701 /** 702 * Command type used for all idle optimization commands. 703 */ 704 DMUB_CMD__IDLE_OPT = 72, 705 /** 706 * Command type used for all clock manager commands. 707 */ 708 DMUB_CMD__CLK_MGR = 73, 709 /** 710 * Command type used for all panel control commands. 711 */ 712 DMUB_CMD__PANEL_CNTL = 74, 713 /** 714 * Command type used for <TODO:description> 715 */ 716 DMUB_CMD__CAB_FOR_SS = 75, 717 718 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 719 720 /** 721 * Command type used for interfacing with DPIA. 722 */ 723 DMUB_CMD__DPIA = 77, 724 /** 725 * Command type used for EDID CEA parsing 726 */ 727 DMUB_CMD__EDID_CEA = 79, 728 /** 729 * Command type used for getting usbc cable ID 730 */ 731 DMUB_CMD_GET_USBC_CABLE_ID = 81, 732 /** 733 * Command type used to query HPD state. 734 */ 735 DMUB_CMD__QUERY_HPD_STATE = 82, 736 /** 737 * Command type used for all VBIOS interface commands. 738 */ 739 740 /** 741 * Command type used for all SECURE_DISPLAY commands. 742 */ 743 DMUB_CMD__SECURE_DISPLAY = 85, 744 745 /** 746 * Command type used to set DPIA HPD interrupt state 747 */ 748 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 749 750 DMUB_CMD__VBIOS = 128, 751 }; 752 753 /** 754 * enum dmub_out_cmd_type - DMUB outbox commands. 755 */ 756 enum dmub_out_cmd_type { 757 /** 758 * Invalid outbox command, ignored. 759 */ 760 DMUB_OUT_CMD__NULL = 0, 761 /** 762 * Command type used for DP AUX Reply data notification 763 */ 764 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 765 /** 766 * Command type used for DP HPD event notification 767 */ 768 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 769 /** 770 * Command type used for SET_CONFIG Reply notification 771 */ 772 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 773 }; 774 775 /* DMUB_CMD__DPIA command sub-types. */ 776 enum dmub_cmd_dpia_type { 777 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 778 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 779 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 780 }; 781 782 #pragma pack(push, 1) 783 784 /** 785 * struct dmub_cmd_header - Common command header fields. 786 */ 787 struct dmub_cmd_header { 788 unsigned int type : 8; /**< command type */ 789 unsigned int sub_type : 8; /**< command sub type */ 790 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 791 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 792 unsigned int reserved0 : 6; /**< reserved bits */ 793 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 794 unsigned int reserved1 : 2; /**< reserved bits */ 795 }; 796 797 /* 798 * struct dmub_cmd_read_modify_write_sequence - Read modify write 799 * 800 * 60 payload bytes can hold up to 5 sets of read modify writes, 801 * each take 3 dwords. 802 * 803 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 804 * 805 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 806 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 807 */ 808 struct dmub_cmd_read_modify_write_sequence { 809 uint32_t addr; /**< register address */ 810 uint32_t modify_mask; /**< modify mask */ 811 uint32_t modify_value; /**< modify value */ 812 }; 813 814 /** 815 * Maximum number of ops in read modify write sequence. 816 */ 817 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 818 819 /** 820 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 821 */ 822 struct dmub_rb_cmd_read_modify_write { 823 struct dmub_cmd_header header; /**< command header */ 824 /** 825 * Read modify write sequence. 826 */ 827 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 828 }; 829 830 /* 831 * Update a register with specified masks and values sequeunce 832 * 833 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 834 * 835 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 836 * 837 * 838 * USE CASE: 839 * 1. auto-increment register where additional read would update pointer and produce wrong result 840 * 2. toggle a bit without read in the middle 841 */ 842 843 struct dmub_cmd_reg_field_update_sequence { 844 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 845 uint32_t modify_value; /**< value to update with */ 846 }; 847 848 /** 849 * Maximum number of ops in field update sequence. 850 */ 851 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 852 853 /** 854 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 855 */ 856 struct dmub_rb_cmd_reg_field_update_sequence { 857 struct dmub_cmd_header header; /**< command header */ 858 uint32_t addr; /**< register address */ 859 /** 860 * Field update sequence. 861 */ 862 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 863 }; 864 865 866 /** 867 * Maximum number of burst write values. 868 */ 869 #define DMUB_BURST_WRITE_VALUES__MAX 14 870 871 /* 872 * struct dmub_rb_cmd_burst_write - Burst write 873 * 874 * support use case such as writing out LUTs. 875 * 876 * 60 payload bytes can hold up to 14 values to write to given address 877 * 878 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 879 */ 880 struct dmub_rb_cmd_burst_write { 881 struct dmub_cmd_header header; /**< command header */ 882 uint32_t addr; /**< register start address */ 883 /** 884 * Burst write register values. 885 */ 886 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 887 }; 888 889 /** 890 * struct dmub_rb_cmd_common - Common command header 891 */ 892 struct dmub_rb_cmd_common { 893 struct dmub_cmd_header header; /**< command header */ 894 /** 895 * Padding to RB_CMD_SIZE 896 */ 897 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 898 }; 899 900 /** 901 * struct dmub_cmd_reg_wait_data - Register wait data 902 */ 903 struct dmub_cmd_reg_wait_data { 904 uint32_t addr; /**< Register address */ 905 uint32_t mask; /**< Mask for register bits */ 906 uint32_t condition_field_value; /**< Value to wait for */ 907 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 908 }; 909 910 /** 911 * struct dmub_rb_cmd_reg_wait - Register wait command 912 */ 913 struct dmub_rb_cmd_reg_wait { 914 struct dmub_cmd_header header; /**< Command header */ 915 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 916 }; 917 918 /** 919 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 920 * 921 * Reprograms surface parameters to avoid underflow. 922 */ 923 struct dmub_cmd_PLAT_54186_wa { 924 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 925 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 926 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 927 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 928 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 929 struct { 930 uint8_t hubp_inst : 4; /**< HUBP instance */ 931 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 932 uint8_t immediate :1; /**< Immediate flip */ 933 uint8_t vmid : 4; /**< VMID */ 934 uint8_t grph_stereo : 1; /**< 1 if stereo */ 935 uint32_t reserved : 21; /**< Reserved */ 936 } flip_params; /**< Pageflip parameters */ 937 uint32_t reserved[9]; /**< Reserved bits */ 938 }; 939 940 /** 941 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 942 */ 943 struct dmub_rb_cmd_PLAT_54186_wa { 944 struct dmub_cmd_header header; /**< Command header */ 945 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 946 }; 947 948 /** 949 * struct dmub_rb_cmd_mall - MALL command data. 950 */ 951 struct dmub_rb_cmd_mall { 952 struct dmub_cmd_header header; /**< Common command header */ 953 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 954 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 955 uint32_t tmr_delay; /**< Timer delay */ 956 uint32_t tmr_scale; /**< Timer scale */ 957 uint16_t cursor_width; /**< Cursor width in pixels */ 958 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 959 uint16_t cursor_height; /**< Cursor height in pixels */ 960 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 961 uint8_t debug_bits; /**< Debug bits */ 962 963 uint8_t reserved1; /**< Reserved bits */ 964 uint8_t reserved2; /**< Reserved bits */ 965 }; 966 967 /** 968 * enum dmub_cmd_cab_type - TODO: 969 */ 970 enum dmub_cmd_cab_type { 971 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 972 DMUB_CMD__CAB_NO_DCN_REQ = 1, 973 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 974 }; 975 976 /** 977 * struct dmub_rb_cmd_cab_for_ss - TODO: 978 */ 979 struct dmub_rb_cmd_cab_for_ss { 980 struct dmub_cmd_header header; 981 uint8_t cab_alloc_ways; /* total number of ways */ 982 uint8_t debug_bits; /* debug bits */ 983 }; 984 985 enum mclk_switch_mode { 986 NONE = 0, 987 FPO = 1, 988 SUBVP = 2, 989 VBLANK = 3, 990 }; 991 992 /* Per pipe struct which stores the MCLK switch mode 993 * data to be sent to DMUB. 994 * Named "v2" for now -- once FPO and SUBVP are fully merged 995 * the type name can be updated 996 */ 997 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 998 union { 999 struct { 1000 uint32_t pix_clk_100hz; 1001 uint16_t main_vblank_start; 1002 uint16_t main_vblank_end; 1003 uint16_t mall_region_lines; 1004 uint16_t prefetch_lines; 1005 uint16_t prefetch_to_mall_start_lines; 1006 uint16_t processing_delay_lines; 1007 uint16_t htotal; // required to calculate line time for multi-display cases 1008 uint16_t vtotal; 1009 uint8_t main_pipe_index; 1010 uint8_t phantom_pipe_index; 1011 /* Since the microschedule is calculated in terms of OTG lines, 1012 * include any scaling factors to make sure when we get accurate 1013 * conversion when programming MALL_START_LINE (which is in terms 1014 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1015 * is 1/2 (numerator = 1, denominator = 2). 1016 */ 1017 uint8_t scale_factor_numerator; 1018 uint8_t scale_factor_denominator; 1019 uint8_t is_drr; 1020 uint8_t main_split_pipe_index; 1021 uint8_t phantom_split_pipe_index; 1022 } subvp_data; 1023 1024 struct { 1025 uint32_t pix_clk_100hz; 1026 uint16_t vblank_start; 1027 uint16_t vblank_end; 1028 uint16_t vstartup_start; 1029 uint16_t vtotal; 1030 uint16_t htotal; 1031 uint8_t vblank_pipe_index; 1032 uint8_t padding[1]; 1033 struct { 1034 uint8_t drr_in_use; 1035 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1036 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1037 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1038 uint8_t use_ramping; // Use ramping or not 1039 uint8_t drr_vblank_start_margin; 1040 } drr_info; // DRR considered as part of SubVP + VBLANK case 1041 } vblank_data; 1042 } pipe_config; 1043 1044 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1045 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1046 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1047 */ 1048 uint8_t mode; // enum mclk_switch_mode 1049 }; 1050 1051 /** 1052 * Config data for Sub-VP and FPO 1053 * Named "v2" for now -- once FPO and SUBVP are fully merged 1054 * the type name can be updated 1055 */ 1056 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1057 uint16_t watermark_a_cache; 1058 uint8_t vertical_int_margin_us; 1059 uint8_t pstate_allow_width_us; 1060 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1061 }; 1062 1063 /** 1064 * DMUB rb command definition for Sub-VP and FPO 1065 * Named "v2" for now -- once FPO and SUBVP are fully merged 1066 * the type name can be updated 1067 */ 1068 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1069 struct dmub_cmd_header header; 1070 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1071 }; 1072 1073 /** 1074 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1075 */ 1076 enum dmub_cmd_idle_opt_type { 1077 /** 1078 * DCN hardware restore. 1079 */ 1080 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1081 1082 /** 1083 * DCN hardware save. 1084 */ 1085 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1086 }; 1087 1088 /** 1089 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1090 */ 1091 struct dmub_rb_cmd_idle_opt_dcn_restore { 1092 struct dmub_cmd_header header; /**< header */ 1093 }; 1094 1095 /** 1096 * struct dmub_clocks - Clock update notification. 1097 */ 1098 struct dmub_clocks { 1099 uint32_t dispclk_khz; /**< dispclk kHz */ 1100 uint32_t dppclk_khz; /**< dppclk kHz */ 1101 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1102 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1103 }; 1104 1105 /** 1106 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1107 */ 1108 enum dmub_cmd_clk_mgr_type { 1109 /** 1110 * Notify DMCUB of clock update. 1111 */ 1112 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1113 }; 1114 1115 /** 1116 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1117 */ 1118 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1119 struct dmub_cmd_header header; /**< header */ 1120 struct dmub_clocks clocks; /**< clock data */ 1121 }; 1122 1123 /** 1124 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1125 */ 1126 struct dmub_cmd_digx_encoder_control_data { 1127 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1128 }; 1129 1130 /** 1131 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1132 */ 1133 struct dmub_rb_cmd_digx_encoder_control { 1134 struct dmub_cmd_header header; /**< header */ 1135 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1136 }; 1137 1138 /** 1139 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1140 */ 1141 struct dmub_cmd_set_pixel_clock_data { 1142 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1143 }; 1144 1145 /** 1146 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1147 */ 1148 struct dmub_rb_cmd_set_pixel_clock { 1149 struct dmub_cmd_header header; /**< header */ 1150 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1151 }; 1152 1153 /** 1154 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1155 */ 1156 struct dmub_cmd_enable_disp_power_gating_data { 1157 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1158 }; 1159 1160 /** 1161 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1162 */ 1163 struct dmub_rb_cmd_enable_disp_power_gating { 1164 struct dmub_cmd_header header; /**< header */ 1165 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1166 }; 1167 1168 /** 1169 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1170 */ 1171 struct dmub_dig_transmitter_control_data_v1_7 { 1172 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1173 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1174 union { 1175 uint8_t digmode; /**< enum atom_encode_mode_def */ 1176 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1177 } mode_laneset; 1178 uint8_t lanenum; /**< Number of lanes */ 1179 union { 1180 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1181 } symclk_units; 1182 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1183 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1184 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1185 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1186 uint8_t reserved1; /**< For future use */ 1187 uint8_t reserved2[3]; /**< For future use */ 1188 uint32_t reserved3[11]; /**< For future use */ 1189 }; 1190 1191 /** 1192 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1193 */ 1194 union dmub_cmd_dig1_transmitter_control_data { 1195 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1196 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1197 }; 1198 1199 /** 1200 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1201 */ 1202 struct dmub_rb_cmd_dig1_transmitter_control { 1203 struct dmub_cmd_header header; /**< header */ 1204 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1205 }; 1206 1207 /** 1208 * DPIA tunnel command parameters. 1209 */ 1210 struct dmub_cmd_dig_dpia_control_data { 1211 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1212 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1213 union { 1214 uint8_t digmode; /** enum atom_encode_mode_def */ 1215 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1216 } mode_laneset; 1217 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1218 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1219 uint8_t hpdsel; /** =0: HPD is not assigned */ 1220 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1221 uint8_t dpia_id; /** Index of DPIA */ 1222 uint8_t fec_rdy : 1; 1223 uint8_t reserved : 7; 1224 uint32_t reserved1; 1225 }; 1226 1227 /** 1228 * DMUB command for DPIA tunnel control. 1229 */ 1230 struct dmub_rb_cmd_dig1_dpia_control { 1231 struct dmub_cmd_header header; 1232 struct dmub_cmd_dig_dpia_control_data dpia_control; 1233 }; 1234 1235 /** 1236 * SET_CONFIG Command Payload 1237 */ 1238 struct set_config_cmd_payload { 1239 uint8_t msg_type; /* set config message type */ 1240 uint8_t msg_data; /* set config message data */ 1241 }; 1242 1243 /** 1244 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1245 */ 1246 struct dmub_cmd_set_config_control_data { 1247 struct set_config_cmd_payload cmd_pkt; 1248 uint8_t instance; /* DPIA instance */ 1249 uint8_t immed_status; /* Immediate status returned in case of error */ 1250 }; 1251 1252 /** 1253 * DMUB command structure for SET_CONFIG command. 1254 */ 1255 struct dmub_rb_cmd_set_config_access { 1256 struct dmub_cmd_header header; /* header */ 1257 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1258 }; 1259 1260 /** 1261 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1262 */ 1263 struct dmub_cmd_mst_alloc_slots_control_data { 1264 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1265 uint8_t instance; /* DPIA instance */ 1266 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1267 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1268 }; 1269 1270 /** 1271 * DMUB command structure for SET_ command. 1272 */ 1273 struct dmub_rb_cmd_set_mst_alloc_slots { 1274 struct dmub_cmd_header header; /* header */ 1275 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1276 }; 1277 1278 /** 1279 * DMUB command structure for DPIA HPD int enable control. 1280 */ 1281 struct dmub_rb_cmd_dpia_hpd_int_enable { 1282 struct dmub_cmd_header header; /* header */ 1283 uint32_t enable; /* dpia hpd interrupt enable */ 1284 }; 1285 1286 /** 1287 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1288 */ 1289 struct dmub_rb_cmd_dpphy_init { 1290 struct dmub_cmd_header header; /**< header */ 1291 uint8_t reserved[60]; /**< reserved bits */ 1292 }; 1293 1294 /** 1295 * enum dp_aux_request_action - DP AUX request command listing. 1296 * 1297 * 4 AUX request command bits are shifted to high nibble. 1298 */ 1299 enum dp_aux_request_action { 1300 /** I2C-over-AUX write request */ 1301 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1302 /** I2C-over-AUX read request */ 1303 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1304 /** I2C-over-AUX write status request */ 1305 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1306 /** I2C-over-AUX write request with MOT=1 */ 1307 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1308 /** I2C-over-AUX read request with MOT=1 */ 1309 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1310 /** I2C-over-AUX write status request with MOT=1 */ 1311 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1312 /** Native AUX write request */ 1313 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1314 /** Native AUX read request */ 1315 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1316 }; 1317 1318 /** 1319 * enum aux_return_code_type - DP AUX process return code listing. 1320 */ 1321 enum aux_return_code_type { 1322 /** AUX process succeeded */ 1323 AUX_RET_SUCCESS = 0, 1324 /** AUX process failed with unknown reason */ 1325 AUX_RET_ERROR_UNKNOWN, 1326 /** AUX process completed with invalid reply */ 1327 AUX_RET_ERROR_INVALID_REPLY, 1328 /** AUX process timed out */ 1329 AUX_RET_ERROR_TIMEOUT, 1330 /** HPD was low during AUX process */ 1331 AUX_RET_ERROR_HPD_DISCON, 1332 /** Failed to acquire AUX engine */ 1333 AUX_RET_ERROR_ENGINE_ACQUIRE, 1334 /** AUX request not supported */ 1335 AUX_RET_ERROR_INVALID_OPERATION, 1336 /** AUX process not available */ 1337 AUX_RET_ERROR_PROTOCOL_ERROR, 1338 }; 1339 1340 /** 1341 * enum aux_channel_type - DP AUX channel type listing. 1342 */ 1343 enum aux_channel_type { 1344 /** AUX thru Legacy DP AUX */ 1345 AUX_CHANNEL_LEGACY_DDC, 1346 /** AUX thru DPIA DP tunneling */ 1347 AUX_CHANNEL_DPIA 1348 }; 1349 1350 /** 1351 * struct aux_transaction_parameters - DP AUX request transaction data 1352 */ 1353 struct aux_transaction_parameters { 1354 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1355 uint8_t action; /**< enum dp_aux_request_action */ 1356 uint8_t length; /**< DP AUX request data length */ 1357 uint8_t reserved; /**< For future use */ 1358 uint32_t address; /**< DP AUX address */ 1359 uint8_t data[16]; /**< DP AUX write data */ 1360 }; 1361 1362 /** 1363 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1364 */ 1365 struct dmub_cmd_dp_aux_control_data { 1366 uint8_t instance; /**< AUX instance or DPIA instance */ 1367 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1368 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1369 uint8_t reserved0; /**< For future use */ 1370 uint16_t timeout; /**< timeout time in us */ 1371 uint16_t reserved1; /**< For future use */ 1372 enum aux_channel_type type; /**< enum aux_channel_type */ 1373 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1374 }; 1375 1376 /** 1377 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1378 */ 1379 struct dmub_rb_cmd_dp_aux_access { 1380 /** 1381 * Command header. 1382 */ 1383 struct dmub_cmd_header header; 1384 /** 1385 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1386 */ 1387 struct dmub_cmd_dp_aux_control_data aux_control; 1388 }; 1389 1390 /** 1391 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1392 */ 1393 struct dmub_rb_cmd_outbox1_enable { 1394 /** 1395 * Command header. 1396 */ 1397 struct dmub_cmd_header header; 1398 /** 1399 * enable: 0x0 -> disable outbox1 notification (default value) 1400 * 0x1 -> enable outbox1 notification 1401 */ 1402 uint32_t enable; 1403 }; 1404 1405 /* DP AUX Reply command - OutBox Cmd */ 1406 /** 1407 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1408 */ 1409 struct aux_reply_data { 1410 /** 1411 * Aux cmd 1412 */ 1413 uint8_t command; 1414 /** 1415 * Aux reply data length (max: 16 bytes) 1416 */ 1417 uint8_t length; 1418 /** 1419 * Alignment only 1420 */ 1421 uint8_t pad[2]; 1422 /** 1423 * Aux reply data 1424 */ 1425 uint8_t data[16]; 1426 }; 1427 1428 /** 1429 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1430 */ 1431 struct aux_reply_control_data { 1432 /** 1433 * Reserved for future use 1434 */ 1435 uint32_t handle; 1436 /** 1437 * Aux Instance 1438 */ 1439 uint8_t instance; 1440 /** 1441 * Aux transaction result: definition in enum aux_return_code_type 1442 */ 1443 uint8_t result; 1444 /** 1445 * Alignment only 1446 */ 1447 uint16_t pad; 1448 }; 1449 1450 /** 1451 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1452 */ 1453 struct dmub_rb_cmd_dp_aux_reply { 1454 /** 1455 * Command header. 1456 */ 1457 struct dmub_cmd_header header; 1458 /** 1459 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1460 */ 1461 struct aux_reply_control_data control; 1462 /** 1463 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1464 */ 1465 struct aux_reply_data reply_data; 1466 }; 1467 1468 /* DP HPD Notify command - OutBox Cmd */ 1469 /** 1470 * DP HPD Type 1471 */ 1472 enum dp_hpd_type { 1473 /** 1474 * Normal DP HPD 1475 */ 1476 DP_HPD = 0, 1477 /** 1478 * DP HPD short pulse 1479 */ 1480 DP_IRQ 1481 }; 1482 1483 /** 1484 * DP HPD Status 1485 */ 1486 enum dp_hpd_status { 1487 /** 1488 * DP_HPD status low 1489 */ 1490 DP_HPD_UNPLUG = 0, 1491 /** 1492 * DP_HPD status high 1493 */ 1494 DP_HPD_PLUG 1495 }; 1496 1497 /** 1498 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1499 */ 1500 struct dp_hpd_data { 1501 /** 1502 * DP HPD instance 1503 */ 1504 uint8_t instance; 1505 /** 1506 * HPD type 1507 */ 1508 uint8_t hpd_type; 1509 /** 1510 * HPD status: only for type: DP_HPD to indicate status 1511 */ 1512 uint8_t hpd_status; 1513 /** 1514 * Alignment only 1515 */ 1516 uint8_t pad; 1517 }; 1518 1519 /** 1520 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1521 */ 1522 struct dmub_rb_cmd_dp_hpd_notify { 1523 /** 1524 * Command header. 1525 */ 1526 struct dmub_cmd_header header; 1527 /** 1528 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1529 */ 1530 struct dp_hpd_data hpd_data; 1531 }; 1532 1533 /** 1534 * Definition of a SET_CONFIG reply from DPOA. 1535 */ 1536 enum set_config_status { 1537 SET_CONFIG_PENDING = 0, 1538 SET_CONFIG_ACK_RECEIVED, 1539 SET_CONFIG_RX_TIMEOUT, 1540 SET_CONFIG_UNKNOWN_ERROR, 1541 }; 1542 1543 /** 1544 * Definition of a set_config reply 1545 */ 1546 struct set_config_reply_control_data { 1547 uint8_t instance; /* DPIA Instance */ 1548 uint8_t status; /* Set Config reply */ 1549 uint16_t pad; /* Alignment */ 1550 }; 1551 1552 /** 1553 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1554 */ 1555 struct dmub_rb_cmd_dp_set_config_reply { 1556 struct dmub_cmd_header header; 1557 struct set_config_reply_control_data set_config_reply_control; 1558 }; 1559 1560 /** 1561 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1562 */ 1563 struct dmub_cmd_hpd_state_query_data { 1564 uint8_t instance; /**< HPD instance or DPIA instance */ 1565 uint8_t result; /**< For returning HPD state */ 1566 uint16_t pad; /** < Alignment */ 1567 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1568 enum aux_return_code_type status; /**< for returning the status of command */ 1569 }; 1570 1571 /** 1572 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1573 */ 1574 struct dmub_rb_cmd_query_hpd_state { 1575 /** 1576 * Command header. 1577 */ 1578 struct dmub_cmd_header header; 1579 /** 1580 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1581 */ 1582 struct dmub_cmd_hpd_state_query_data data; 1583 }; 1584 1585 /* 1586 * Command IDs should be treated as stable ABI. 1587 * Do not reuse or modify IDs. 1588 */ 1589 1590 /** 1591 * PSR command sub-types. 1592 */ 1593 enum dmub_cmd_psr_type { 1594 /** 1595 * Set PSR version support. 1596 */ 1597 DMUB_CMD__PSR_SET_VERSION = 0, 1598 /** 1599 * Copy driver-calculated parameters to PSR state. 1600 */ 1601 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1602 /** 1603 * Enable PSR. 1604 */ 1605 DMUB_CMD__PSR_ENABLE = 2, 1606 1607 /** 1608 * Disable PSR. 1609 */ 1610 DMUB_CMD__PSR_DISABLE = 3, 1611 1612 /** 1613 * Set PSR level. 1614 * PSR level is a 16-bit value dicated by driver that 1615 * will enable/disable different functionality. 1616 */ 1617 DMUB_CMD__PSR_SET_LEVEL = 4, 1618 1619 /** 1620 * Forces PSR enabled until an explicit PSR disable call. 1621 */ 1622 DMUB_CMD__PSR_FORCE_STATIC = 5, 1623 /** 1624 * Set vtotal in psr active for FreeSync PSR. 1625 */ 1626 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1627 /** 1628 * Set PSR power option 1629 */ 1630 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1631 }; 1632 1633 enum dmub_cmd_fams_type { 1634 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1635 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1636 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1637 /** 1638 * For SubVP set manual trigger in FW because it 1639 * triggers DRR_UPDATE_PENDING which SubVP relies 1640 * on (for any SubVP cases that use a DRR display) 1641 */ 1642 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1643 }; 1644 1645 /** 1646 * PSR versions. 1647 */ 1648 enum psr_version { 1649 /** 1650 * PSR version 1. 1651 */ 1652 PSR_VERSION_1 = 0, 1653 /** 1654 * Freesync PSR SU. 1655 */ 1656 PSR_VERSION_SU_1 = 1, 1657 /** 1658 * PSR not supported. 1659 */ 1660 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1661 }; 1662 1663 /** 1664 * enum dmub_cmd_mall_type - MALL commands 1665 */ 1666 enum dmub_cmd_mall_type { 1667 /** 1668 * Allows display refresh from MALL. 1669 */ 1670 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1671 /** 1672 * Disallows display refresh from MALL. 1673 */ 1674 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1675 /** 1676 * Cursor copy for MALL. 1677 */ 1678 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1679 /** 1680 * Controls DF requests. 1681 */ 1682 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1683 }; 1684 1685 /** 1686 * PHY Link rate for DP. 1687 */ 1688 enum phy_link_rate { 1689 /** 1690 * not supported. 1691 */ 1692 PHY_RATE_UNKNOWN = 0, 1693 /** 1694 * Rate_1 (RBR) - 1.62 Gbps/Lane 1695 */ 1696 PHY_RATE_162 = 1, 1697 /** 1698 * Rate_2 - 2.16 Gbps/Lane 1699 */ 1700 PHY_RATE_216 = 2, 1701 /** 1702 * Rate_3 - 2.43 Gbps/Lane 1703 */ 1704 PHY_RATE_243 = 3, 1705 /** 1706 * Rate_4 (HBR) - 2.70 Gbps/Lane 1707 */ 1708 PHY_RATE_270 = 4, 1709 /** 1710 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1711 */ 1712 PHY_RATE_324 = 5, 1713 /** 1714 * Rate_6 - 4.32 Gbps/Lane 1715 */ 1716 PHY_RATE_432 = 6, 1717 /** 1718 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1719 */ 1720 PHY_RATE_540 = 7, 1721 /** 1722 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1723 */ 1724 PHY_RATE_810 = 8, 1725 /** 1726 * UHBR10 - 10.0 Gbps/Lane 1727 */ 1728 PHY_RATE_1000 = 9, 1729 /** 1730 * UHBR13.5 - 13.5 Gbps/Lane 1731 */ 1732 PHY_RATE_1350 = 10, 1733 /** 1734 * UHBR10 - 20.0 Gbps/Lane 1735 */ 1736 PHY_RATE_2000 = 11, 1737 }; 1738 1739 /** 1740 * enum dmub_phy_fsm_state - PHY FSM states. 1741 * PHY FSM state to transit to during PSR enable/disable. 1742 */ 1743 enum dmub_phy_fsm_state { 1744 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1745 DMUB_PHY_FSM_RESET, 1746 DMUB_PHY_FSM_RESET_RELEASED, 1747 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1748 DMUB_PHY_FSM_INITIALIZED, 1749 DMUB_PHY_FSM_CALIBRATED, 1750 DMUB_PHY_FSM_CALIBRATED_LP, 1751 DMUB_PHY_FSM_CALIBRATED_PG, 1752 DMUB_PHY_FSM_POWER_DOWN, 1753 DMUB_PHY_FSM_PLL_EN, 1754 DMUB_PHY_FSM_TX_EN, 1755 DMUB_PHY_FSM_FAST_LP, 1756 }; 1757 1758 /** 1759 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1760 */ 1761 struct dmub_cmd_psr_copy_settings_data { 1762 /** 1763 * Flags that can be set by driver to change some PSR behaviour. 1764 */ 1765 union dmub_psr_debug_flags debug; 1766 /** 1767 * 16-bit value dicated by driver that will enable/disable different functionality. 1768 */ 1769 uint16_t psr_level; 1770 /** 1771 * DPP HW instance. 1772 */ 1773 uint8_t dpp_inst; 1774 /** 1775 * MPCC HW instance. 1776 * Not used in dmub fw, 1777 * dmub fw will get active opp by reading odm registers. 1778 */ 1779 uint8_t mpcc_inst; 1780 /** 1781 * OPP HW instance. 1782 * Not used in dmub fw, 1783 * dmub fw will get active opp by reading odm registers. 1784 */ 1785 uint8_t opp_inst; 1786 /** 1787 * OTG HW instance. 1788 */ 1789 uint8_t otg_inst; 1790 /** 1791 * DIG FE HW instance. 1792 */ 1793 uint8_t digfe_inst; 1794 /** 1795 * DIG BE HW instance. 1796 */ 1797 uint8_t digbe_inst; 1798 /** 1799 * DP PHY HW instance. 1800 */ 1801 uint8_t dpphy_inst; 1802 /** 1803 * AUX HW instance. 1804 */ 1805 uint8_t aux_inst; 1806 /** 1807 * Determines if SMU optimzations are enabled/disabled. 1808 */ 1809 uint8_t smu_optimizations_en; 1810 /** 1811 * Unused. 1812 * TODO: Remove. 1813 */ 1814 uint8_t frame_delay; 1815 /** 1816 * If RFB setup time is greater than the total VBLANK time, 1817 * it is not possible for the sink to capture the video frame 1818 * in the same frame the SDP is sent. In this case, 1819 * the frame capture indication bit should be set and an extra 1820 * static frame should be transmitted to the sink. 1821 */ 1822 uint8_t frame_cap_ind; 1823 /** 1824 * Granularity of Y offset supported by sink. 1825 */ 1826 uint8_t su_y_granularity; 1827 /** 1828 * Indicates whether sink should start capturing 1829 * immediately following active scan line, 1830 * or starting with the 2nd active scan line. 1831 */ 1832 uint8_t line_capture_indication; 1833 /** 1834 * Multi-display optimizations are implemented on certain ASICs. 1835 */ 1836 uint8_t multi_disp_optimizations_en; 1837 /** 1838 * The last possible line SDP may be transmitted without violating 1839 * the RFB setup time or entering the active video frame. 1840 */ 1841 uint16_t init_sdp_deadline; 1842 /** 1843 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1844 */ 1845 uint8_t rate_control_caps ; 1846 /* 1847 * Force PSRSU always doing full frame update 1848 */ 1849 uint8_t force_ffu_mode; 1850 /** 1851 * Length of each horizontal line in us. 1852 */ 1853 uint32_t line_time_in_us; 1854 /** 1855 * FEC enable status in driver 1856 */ 1857 uint8_t fec_enable_status; 1858 /** 1859 * FEC re-enable delay when PSR exit. 1860 * unit is 100us, range form 0~255(0xFF). 1861 */ 1862 uint8_t fec_enable_delay_in100us; 1863 /** 1864 * PSR control version. 1865 */ 1866 uint8_t cmd_version; 1867 /** 1868 * Panel Instance. 1869 * Panel isntance to identify which psr_state to use 1870 * Currently the support is only for 0 or 1 1871 */ 1872 uint8_t panel_inst; 1873 /* 1874 * DSC enable status in driver 1875 */ 1876 uint8_t dsc_enable_status; 1877 /* 1878 * Use FSM state for PSR power up/down 1879 */ 1880 uint8_t use_phy_fsm; 1881 /** 1882 * frame delay for frame re-lock 1883 */ 1884 uint8_t relock_delay_frame_cnt; 1885 /** 1886 * Explicit padding to 2 byte boundary. 1887 */ 1888 uint8_t pad3; 1889 }; 1890 1891 /** 1892 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1893 */ 1894 struct dmub_rb_cmd_psr_copy_settings { 1895 /** 1896 * Command header. 1897 */ 1898 struct dmub_cmd_header header; 1899 /** 1900 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1901 */ 1902 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1903 }; 1904 1905 /** 1906 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1907 */ 1908 struct dmub_cmd_psr_set_level_data { 1909 /** 1910 * 16-bit value dicated by driver that will enable/disable different functionality. 1911 */ 1912 uint16_t psr_level; 1913 /** 1914 * PSR control version. 1915 */ 1916 uint8_t cmd_version; 1917 /** 1918 * Panel Instance. 1919 * Panel isntance to identify which psr_state to use 1920 * Currently the support is only for 0 or 1 1921 */ 1922 uint8_t panel_inst; 1923 }; 1924 1925 /** 1926 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1927 */ 1928 struct dmub_rb_cmd_psr_set_level { 1929 /** 1930 * Command header. 1931 */ 1932 struct dmub_cmd_header header; 1933 /** 1934 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1935 */ 1936 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1937 }; 1938 1939 struct dmub_rb_cmd_psr_enable_data { 1940 /** 1941 * PSR control version. 1942 */ 1943 uint8_t cmd_version; 1944 /** 1945 * Panel Instance. 1946 * Panel isntance to identify which psr_state to use 1947 * Currently the support is only for 0 or 1 1948 */ 1949 uint8_t panel_inst; 1950 /** 1951 * Phy state to enter. 1952 * Values to use are defined in dmub_phy_fsm_state 1953 */ 1954 uint8_t phy_fsm_state; 1955 /** 1956 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1957 * Set this using enum phy_link_rate. 1958 * This does not support HDMI/DP2 for now. 1959 */ 1960 uint8_t phy_rate; 1961 }; 1962 1963 /** 1964 * Definition of a DMUB_CMD__PSR_ENABLE command. 1965 * PSR enable/disable is controlled using the sub_type. 1966 */ 1967 struct dmub_rb_cmd_psr_enable { 1968 /** 1969 * Command header. 1970 */ 1971 struct dmub_cmd_header header; 1972 1973 struct dmub_rb_cmd_psr_enable_data data; 1974 }; 1975 1976 /** 1977 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1978 */ 1979 struct dmub_cmd_psr_set_version_data { 1980 /** 1981 * PSR version that FW should implement. 1982 */ 1983 enum psr_version version; 1984 /** 1985 * PSR control version. 1986 */ 1987 uint8_t cmd_version; 1988 /** 1989 * Panel Instance. 1990 * Panel isntance to identify which psr_state to use 1991 * Currently the support is only for 0 or 1 1992 */ 1993 uint8_t panel_inst; 1994 /** 1995 * Explicit padding to 4 byte boundary. 1996 */ 1997 uint8_t pad[2]; 1998 }; 1999 2000 /** 2001 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2002 */ 2003 struct dmub_rb_cmd_psr_set_version { 2004 /** 2005 * Command header. 2006 */ 2007 struct dmub_cmd_header header; 2008 /** 2009 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2010 */ 2011 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2012 }; 2013 2014 struct dmub_cmd_psr_force_static_data { 2015 /** 2016 * PSR control version. 2017 */ 2018 uint8_t cmd_version; 2019 /** 2020 * Panel Instance. 2021 * Panel isntance to identify which psr_state to use 2022 * Currently the support is only for 0 or 1 2023 */ 2024 uint8_t panel_inst; 2025 /** 2026 * Explicit padding to 4 byte boundary. 2027 */ 2028 uint8_t pad[2]; 2029 }; 2030 2031 /** 2032 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2033 */ 2034 struct dmub_rb_cmd_psr_force_static { 2035 /** 2036 * Command header. 2037 */ 2038 struct dmub_cmd_header header; 2039 /** 2040 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2041 */ 2042 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2043 }; 2044 2045 /** 2046 * PSR SU debug flags. 2047 */ 2048 union dmub_psr_su_debug_flags { 2049 /** 2050 * PSR SU debug flags. 2051 */ 2052 struct { 2053 /** 2054 * Update dirty rect in SW only. 2055 */ 2056 uint8_t update_dirty_rect_only : 1; 2057 /** 2058 * Reset the cursor/plane state before processing the call. 2059 */ 2060 uint8_t reset_state : 1; 2061 } bitfields; 2062 2063 /** 2064 * Union for debug flags. 2065 */ 2066 uint32_t u32All; 2067 }; 2068 2069 /** 2070 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2071 * This triggers a selective update for PSR SU. 2072 */ 2073 struct dmub_cmd_update_dirty_rect_data { 2074 /** 2075 * Dirty rects from OS. 2076 */ 2077 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2078 /** 2079 * PSR SU debug flags. 2080 */ 2081 union dmub_psr_su_debug_flags debug_flags; 2082 /** 2083 * OTG HW instance. 2084 */ 2085 uint8_t pipe_idx; 2086 /** 2087 * Number of dirty rects. 2088 */ 2089 uint8_t dirty_rect_count; 2090 /** 2091 * PSR control version. 2092 */ 2093 uint8_t cmd_version; 2094 /** 2095 * Panel Instance. 2096 * Panel isntance to identify which psr_state to use 2097 * Currently the support is only for 0 or 1 2098 */ 2099 uint8_t panel_inst; 2100 }; 2101 2102 /** 2103 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2104 */ 2105 struct dmub_rb_cmd_update_dirty_rect { 2106 /** 2107 * Command header. 2108 */ 2109 struct dmub_cmd_header header; 2110 /** 2111 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2112 */ 2113 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2114 }; 2115 2116 /** 2117 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2118 */ 2119 union dmub_reg_cursor_control_cfg { 2120 struct { 2121 uint32_t cur_enable: 1; 2122 uint32_t reser0: 3; 2123 uint32_t cur_2x_magnify: 1; 2124 uint32_t reser1: 3; 2125 uint32_t mode: 3; 2126 uint32_t reser2: 5; 2127 uint32_t pitch: 2; 2128 uint32_t reser3: 6; 2129 uint32_t line_per_chunk: 5; 2130 uint32_t reser4: 3; 2131 } bits; 2132 uint32_t raw; 2133 }; 2134 struct dmub_cursor_position_cache_hubp { 2135 union dmub_reg_cursor_control_cfg cur_ctl; 2136 union dmub_reg_position_cfg { 2137 struct { 2138 uint32_t cur_x_pos: 16; 2139 uint32_t cur_y_pos: 16; 2140 } bits; 2141 uint32_t raw; 2142 } position; 2143 union dmub_reg_hot_spot_cfg { 2144 struct { 2145 uint32_t hot_x: 16; 2146 uint32_t hot_y: 16; 2147 } bits; 2148 uint32_t raw; 2149 } hot_spot; 2150 union dmub_reg_dst_offset_cfg { 2151 struct { 2152 uint32_t dst_x_offset: 13; 2153 uint32_t reserved: 19; 2154 } bits; 2155 uint32_t raw; 2156 } dst_offset; 2157 }; 2158 2159 union dmub_reg_cur0_control_cfg { 2160 struct { 2161 uint32_t cur0_enable: 1; 2162 uint32_t expansion_mode: 1; 2163 uint32_t reser0: 1; 2164 uint32_t cur0_rom_en: 1; 2165 uint32_t mode: 3; 2166 uint32_t reserved: 25; 2167 } bits; 2168 uint32_t raw; 2169 }; 2170 struct dmub_cursor_position_cache_dpp { 2171 union dmub_reg_cur0_control_cfg cur0_ctl; 2172 }; 2173 struct dmub_cursor_position_cfg { 2174 struct dmub_cursor_position_cache_hubp pHubp; 2175 struct dmub_cursor_position_cache_dpp pDpp; 2176 uint8_t pipe_idx; 2177 /* 2178 * Padding is required. To be 4 Bytes Aligned. 2179 */ 2180 uint8_t padding[3]; 2181 }; 2182 2183 struct dmub_cursor_attribute_cache_hubp { 2184 uint32_t SURFACE_ADDR_HIGH; 2185 uint32_t SURFACE_ADDR; 2186 union dmub_reg_cursor_control_cfg cur_ctl; 2187 union dmub_reg_cursor_size_cfg { 2188 struct { 2189 uint32_t width: 16; 2190 uint32_t height: 16; 2191 } bits; 2192 uint32_t raw; 2193 } size; 2194 union dmub_reg_cursor_settings_cfg { 2195 struct { 2196 uint32_t dst_y_offset: 8; 2197 uint32_t chunk_hdl_adjust: 2; 2198 uint32_t reserved: 22; 2199 } bits; 2200 uint32_t raw; 2201 } settings; 2202 }; 2203 struct dmub_cursor_attribute_cache_dpp { 2204 union dmub_reg_cur0_control_cfg cur0_ctl; 2205 }; 2206 struct dmub_cursor_attributes_cfg { 2207 struct dmub_cursor_attribute_cache_hubp aHubp; 2208 struct dmub_cursor_attribute_cache_dpp aDpp; 2209 }; 2210 2211 struct dmub_cmd_update_cursor_payload0 { 2212 /** 2213 * Cursor dirty rects. 2214 */ 2215 struct dmub_rect cursor_rect; 2216 /** 2217 * PSR SU debug flags. 2218 */ 2219 union dmub_psr_su_debug_flags debug_flags; 2220 /** 2221 * Cursor enable/disable. 2222 */ 2223 uint8_t enable; 2224 /** 2225 * OTG HW instance. 2226 */ 2227 uint8_t pipe_idx; 2228 /** 2229 * PSR control version. 2230 */ 2231 uint8_t cmd_version; 2232 /** 2233 * Panel Instance. 2234 * Panel isntance to identify which psr_state to use 2235 * Currently the support is only for 0 or 1 2236 */ 2237 uint8_t panel_inst; 2238 /** 2239 * Cursor Position Register. 2240 * Registers contains Hubp & Dpp modules 2241 */ 2242 struct dmub_cursor_position_cfg position_cfg; 2243 }; 2244 2245 struct dmub_cmd_update_cursor_payload1 { 2246 struct dmub_cursor_attributes_cfg attribute_cfg; 2247 }; 2248 2249 union dmub_cmd_update_cursor_info_data { 2250 struct dmub_cmd_update_cursor_payload0 payload0; 2251 struct dmub_cmd_update_cursor_payload1 payload1; 2252 }; 2253 /** 2254 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2255 */ 2256 struct dmub_rb_cmd_update_cursor_info { 2257 /** 2258 * Command header. 2259 */ 2260 struct dmub_cmd_header header; 2261 /** 2262 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2263 */ 2264 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2265 }; 2266 2267 /** 2268 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2269 */ 2270 struct dmub_cmd_psr_set_vtotal_data { 2271 /** 2272 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2273 */ 2274 uint16_t psr_vtotal_idle; 2275 /** 2276 * PSR control version. 2277 */ 2278 uint8_t cmd_version; 2279 /** 2280 * Panel Instance. 2281 * Panel isntance to identify which psr_state to use 2282 * Currently the support is only for 0 or 1 2283 */ 2284 uint8_t panel_inst; 2285 /* 2286 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2287 */ 2288 uint16_t psr_vtotal_su; 2289 /** 2290 * Explicit padding to 4 byte boundary. 2291 */ 2292 uint8_t pad2[2]; 2293 }; 2294 2295 /** 2296 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2297 */ 2298 struct dmub_rb_cmd_psr_set_vtotal { 2299 /** 2300 * Command header. 2301 */ 2302 struct dmub_cmd_header header; 2303 /** 2304 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2305 */ 2306 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2307 }; 2308 2309 /** 2310 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2311 */ 2312 struct dmub_cmd_psr_set_power_opt_data { 2313 /** 2314 * PSR control version. 2315 */ 2316 uint8_t cmd_version; 2317 /** 2318 * Panel Instance. 2319 * Panel isntance to identify which psr_state to use 2320 * Currently the support is only for 0 or 1 2321 */ 2322 uint8_t panel_inst; 2323 /** 2324 * Explicit padding to 4 byte boundary. 2325 */ 2326 uint8_t pad[2]; 2327 /** 2328 * PSR power option 2329 */ 2330 uint32_t power_opt; 2331 }; 2332 2333 /** 2334 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2335 */ 2336 struct dmub_rb_cmd_psr_set_power_opt { 2337 /** 2338 * Command header. 2339 */ 2340 struct dmub_cmd_header header; 2341 /** 2342 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2343 */ 2344 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2345 }; 2346 2347 /** 2348 * Set of HW components that can be locked. 2349 * 2350 * Note: If updating with more HW components, fields 2351 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2352 */ 2353 union dmub_hw_lock_flags { 2354 /** 2355 * Set of HW components that can be locked. 2356 */ 2357 struct { 2358 /** 2359 * Lock/unlock OTG master update lock. 2360 */ 2361 uint8_t lock_pipe : 1; 2362 /** 2363 * Lock/unlock cursor. 2364 */ 2365 uint8_t lock_cursor : 1; 2366 /** 2367 * Lock/unlock global update lock. 2368 */ 2369 uint8_t lock_dig : 1; 2370 /** 2371 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2372 */ 2373 uint8_t triple_buffer_lock : 1; 2374 } bits; 2375 2376 /** 2377 * Union for HW Lock flags. 2378 */ 2379 uint8_t u8All; 2380 }; 2381 2382 /** 2383 * Instances of HW to be locked. 2384 * 2385 * Note: If updating with more HW components, fields 2386 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2387 */ 2388 struct dmub_hw_lock_inst_flags { 2389 /** 2390 * OTG HW instance for OTG master update lock. 2391 */ 2392 uint8_t otg_inst; 2393 /** 2394 * OPP instance for cursor lock. 2395 */ 2396 uint8_t opp_inst; 2397 /** 2398 * OTG HW instance for global update lock. 2399 * TODO: Remove, and re-use otg_inst. 2400 */ 2401 uint8_t dig_inst; 2402 /** 2403 * Explicit pad to 4 byte boundary. 2404 */ 2405 uint8_t pad; 2406 }; 2407 2408 /** 2409 * Clients that can acquire the HW Lock Manager. 2410 * 2411 * Note: If updating with more clients, fields in 2412 * dmub_inbox0_cmd_lock_hw must be updated to match. 2413 */ 2414 enum hw_lock_client { 2415 /** 2416 * Driver is the client of HW Lock Manager. 2417 */ 2418 HW_LOCK_CLIENT_DRIVER = 0, 2419 /** 2420 * PSR SU is the client of HW Lock Manager. 2421 */ 2422 HW_LOCK_CLIENT_PSR_SU = 1, 2423 /** 2424 * Invalid client. 2425 */ 2426 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2427 }; 2428 2429 /** 2430 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2431 */ 2432 struct dmub_cmd_lock_hw_data { 2433 /** 2434 * Specifies the client accessing HW Lock Manager. 2435 */ 2436 enum hw_lock_client client; 2437 /** 2438 * HW instances to be locked. 2439 */ 2440 struct dmub_hw_lock_inst_flags inst_flags; 2441 /** 2442 * Which components to be locked. 2443 */ 2444 union dmub_hw_lock_flags hw_locks; 2445 /** 2446 * Specifies lock/unlock. 2447 */ 2448 uint8_t lock; 2449 /** 2450 * HW can be unlocked separately from releasing the HW Lock Mgr. 2451 * This flag is set if the client wishes to release the object. 2452 */ 2453 uint8_t should_release; 2454 /** 2455 * Explicit padding to 4 byte boundary. 2456 */ 2457 uint8_t pad; 2458 }; 2459 2460 /** 2461 * Definition of a DMUB_CMD__HW_LOCK command. 2462 * Command is used by driver and FW. 2463 */ 2464 struct dmub_rb_cmd_lock_hw { 2465 /** 2466 * Command header. 2467 */ 2468 struct dmub_cmd_header header; 2469 /** 2470 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2471 */ 2472 struct dmub_cmd_lock_hw_data lock_hw_data; 2473 }; 2474 2475 /** 2476 * ABM command sub-types. 2477 */ 2478 enum dmub_cmd_abm_type { 2479 /** 2480 * Initialize parameters for ABM algorithm. 2481 * Data is passed through an indirect buffer. 2482 */ 2483 DMUB_CMD__ABM_INIT_CONFIG = 0, 2484 /** 2485 * Set OTG and panel HW instance. 2486 */ 2487 DMUB_CMD__ABM_SET_PIPE = 1, 2488 /** 2489 * Set user requested backklight level. 2490 */ 2491 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2492 /** 2493 * Set ABM operating/aggression level. 2494 */ 2495 DMUB_CMD__ABM_SET_LEVEL = 3, 2496 /** 2497 * Set ambient light level. 2498 */ 2499 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2500 /** 2501 * Enable/disable fractional duty cycle for backlight PWM. 2502 */ 2503 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2504 2505 /** 2506 * unregister vertical interrupt after steady state is reached 2507 */ 2508 DMUB_CMD__ABM_PAUSE = 6, 2509 }; 2510 2511 /** 2512 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2513 * Requirements: 2514 * - Padded explicitly to 32-bit boundary. 2515 * - Must ensure this structure matches the one on driver-side, 2516 * otherwise it won't be aligned. 2517 */ 2518 struct abm_config_table { 2519 /** 2520 * Gamma curve thresholds, used for crgb conversion. 2521 */ 2522 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2523 /** 2524 * Gamma curve offsets, used for crgb conversion. 2525 */ 2526 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2527 /** 2528 * Gamma curve slopes, used for crgb conversion. 2529 */ 2530 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2531 /** 2532 * Custom backlight curve thresholds. 2533 */ 2534 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2535 /** 2536 * Custom backlight curve offsets. 2537 */ 2538 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2539 /** 2540 * Ambient light thresholds. 2541 */ 2542 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2543 /** 2544 * Minimum programmable backlight. 2545 */ 2546 uint16_t min_abm_backlight; // 122B 2547 /** 2548 * Minimum reduction values. 2549 */ 2550 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2551 /** 2552 * Maximum reduction values. 2553 */ 2554 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2555 /** 2556 * Bright positive gain. 2557 */ 2558 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2559 /** 2560 * Dark negative gain. 2561 */ 2562 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2563 /** 2564 * Hybrid factor. 2565 */ 2566 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2567 /** 2568 * Contrast factor. 2569 */ 2570 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2571 /** 2572 * Deviation gain. 2573 */ 2574 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2575 /** 2576 * Minimum knee. 2577 */ 2578 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2579 /** 2580 * Maximum knee. 2581 */ 2582 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2583 /** 2584 * Unused. 2585 */ 2586 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2587 /** 2588 * Explicit padding to 4 byte boundary. 2589 */ 2590 uint8_t pad3[3]; // 229B 2591 /** 2592 * Backlight ramp reduction. 2593 */ 2594 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2595 /** 2596 * Backlight ramp start. 2597 */ 2598 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2599 }; 2600 2601 /** 2602 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2603 */ 2604 struct dmub_cmd_abm_set_pipe_data { 2605 /** 2606 * OTG HW instance. 2607 */ 2608 uint8_t otg_inst; 2609 2610 /** 2611 * Panel Control HW instance. 2612 */ 2613 uint8_t panel_inst; 2614 2615 /** 2616 * Controls how ABM will interpret a set pipe or set level command. 2617 */ 2618 uint8_t set_pipe_option; 2619 2620 /** 2621 * Unused. 2622 * TODO: Remove. 2623 */ 2624 uint8_t ramping_boundary; 2625 }; 2626 2627 /** 2628 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2629 */ 2630 struct dmub_rb_cmd_abm_set_pipe { 2631 /** 2632 * Command header. 2633 */ 2634 struct dmub_cmd_header header; 2635 2636 /** 2637 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2638 */ 2639 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2640 }; 2641 2642 /** 2643 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2644 */ 2645 struct dmub_cmd_abm_set_backlight_data { 2646 /** 2647 * Number of frames to ramp to backlight user level. 2648 */ 2649 uint32_t frame_ramp; 2650 2651 /** 2652 * Requested backlight level from user. 2653 */ 2654 uint32_t backlight_user_level; 2655 2656 /** 2657 * ABM control version. 2658 */ 2659 uint8_t version; 2660 2661 /** 2662 * Panel Control HW instance mask. 2663 * Bit 0 is Panel Control HW instance 0. 2664 * Bit 1 is Panel Control HW instance 1. 2665 */ 2666 uint8_t panel_mask; 2667 2668 /** 2669 * Explicit padding to 4 byte boundary. 2670 */ 2671 uint8_t pad[2]; 2672 }; 2673 2674 /** 2675 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2676 */ 2677 struct dmub_rb_cmd_abm_set_backlight { 2678 /** 2679 * Command header. 2680 */ 2681 struct dmub_cmd_header header; 2682 2683 /** 2684 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2685 */ 2686 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2687 }; 2688 2689 /** 2690 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2691 */ 2692 struct dmub_cmd_abm_set_level_data { 2693 /** 2694 * Set current ABM operating/aggression level. 2695 */ 2696 uint32_t level; 2697 2698 /** 2699 * ABM control version. 2700 */ 2701 uint8_t version; 2702 2703 /** 2704 * Panel Control HW instance mask. 2705 * Bit 0 is Panel Control HW instance 0. 2706 * Bit 1 is Panel Control HW instance 1. 2707 */ 2708 uint8_t panel_mask; 2709 2710 /** 2711 * Explicit padding to 4 byte boundary. 2712 */ 2713 uint8_t pad[2]; 2714 }; 2715 2716 /** 2717 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2718 */ 2719 struct dmub_rb_cmd_abm_set_level { 2720 /** 2721 * Command header. 2722 */ 2723 struct dmub_cmd_header header; 2724 2725 /** 2726 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2727 */ 2728 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2729 }; 2730 2731 /** 2732 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2733 */ 2734 struct dmub_cmd_abm_set_ambient_level_data { 2735 /** 2736 * Ambient light sensor reading from OS. 2737 */ 2738 uint32_t ambient_lux; 2739 2740 /** 2741 * ABM control version. 2742 */ 2743 uint8_t version; 2744 2745 /** 2746 * Panel Control HW instance mask. 2747 * Bit 0 is Panel Control HW instance 0. 2748 * Bit 1 is Panel Control HW instance 1. 2749 */ 2750 uint8_t panel_mask; 2751 2752 /** 2753 * Explicit padding to 4 byte boundary. 2754 */ 2755 uint8_t pad[2]; 2756 }; 2757 2758 /** 2759 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2760 */ 2761 struct dmub_rb_cmd_abm_set_ambient_level { 2762 /** 2763 * Command header. 2764 */ 2765 struct dmub_cmd_header header; 2766 2767 /** 2768 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2769 */ 2770 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2771 }; 2772 2773 /** 2774 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2775 */ 2776 struct dmub_cmd_abm_set_pwm_frac_data { 2777 /** 2778 * Enable/disable fractional duty cycle for backlight PWM. 2779 * TODO: Convert to uint8_t. 2780 */ 2781 uint32_t fractional_pwm; 2782 2783 /** 2784 * ABM control version. 2785 */ 2786 uint8_t version; 2787 2788 /** 2789 * Panel Control HW instance mask. 2790 * Bit 0 is Panel Control HW instance 0. 2791 * Bit 1 is Panel Control HW instance 1. 2792 */ 2793 uint8_t panel_mask; 2794 2795 /** 2796 * Explicit padding to 4 byte boundary. 2797 */ 2798 uint8_t pad[2]; 2799 }; 2800 2801 /** 2802 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2803 */ 2804 struct dmub_rb_cmd_abm_set_pwm_frac { 2805 /** 2806 * Command header. 2807 */ 2808 struct dmub_cmd_header header; 2809 2810 /** 2811 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2812 */ 2813 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2814 }; 2815 2816 /** 2817 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2818 */ 2819 struct dmub_cmd_abm_init_config_data { 2820 /** 2821 * Location of indirect buffer used to pass init data to ABM. 2822 */ 2823 union dmub_addr src; 2824 2825 /** 2826 * Indirect buffer length. 2827 */ 2828 uint16_t bytes; 2829 2830 2831 /** 2832 * ABM control version. 2833 */ 2834 uint8_t version; 2835 2836 /** 2837 * Panel Control HW instance mask. 2838 * Bit 0 is Panel Control HW instance 0. 2839 * Bit 1 is Panel Control HW instance 1. 2840 */ 2841 uint8_t panel_mask; 2842 2843 /** 2844 * Explicit padding to 4 byte boundary. 2845 */ 2846 uint8_t pad[2]; 2847 }; 2848 2849 /** 2850 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2851 */ 2852 struct dmub_rb_cmd_abm_init_config { 2853 /** 2854 * Command header. 2855 */ 2856 struct dmub_cmd_header header; 2857 2858 /** 2859 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2860 */ 2861 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2862 }; 2863 2864 /** 2865 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2866 */ 2867 2868 struct dmub_cmd_abm_pause_data { 2869 2870 /** 2871 * Panel Control HW instance mask. 2872 * Bit 0 is Panel Control HW instance 0. 2873 * Bit 1 is Panel Control HW instance 1. 2874 */ 2875 uint8_t panel_mask; 2876 2877 /** 2878 * OTG hw instance 2879 */ 2880 uint8_t otg_inst; 2881 2882 /** 2883 * Enable or disable ABM pause 2884 */ 2885 uint8_t enable; 2886 2887 /** 2888 * Explicit padding to 4 byte boundary. 2889 */ 2890 uint8_t pad[1]; 2891 }; 2892 2893 /** 2894 * Definition of a DMUB_CMD__ABM_PAUSE command. 2895 */ 2896 struct dmub_rb_cmd_abm_pause { 2897 /** 2898 * Command header. 2899 */ 2900 struct dmub_cmd_header header; 2901 2902 /** 2903 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2904 */ 2905 struct dmub_cmd_abm_pause_data abm_pause_data; 2906 }; 2907 2908 /** 2909 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2910 */ 2911 struct dmub_cmd_query_feature_caps_data { 2912 /** 2913 * DMUB feature capabilities. 2914 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2915 */ 2916 struct dmub_feature_caps feature_caps; 2917 }; 2918 2919 /** 2920 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2921 */ 2922 struct dmub_rb_cmd_query_feature_caps { 2923 /** 2924 * Command header. 2925 */ 2926 struct dmub_cmd_header header; 2927 /** 2928 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2929 */ 2930 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2931 }; 2932 2933 /** 2934 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2935 */ 2936 struct dmub_cmd_visual_confirm_color_data { 2937 /** 2938 * DMUB feature capabilities. 2939 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2940 */ 2941 struct dmub_visual_confirm_color visual_confirm_color; 2942 }; 2943 2944 /** 2945 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2946 */ 2947 struct dmub_rb_cmd_get_visual_confirm_color { 2948 /** 2949 * Command header. 2950 */ 2951 struct dmub_cmd_header header; 2952 /** 2953 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2954 */ 2955 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2956 }; 2957 2958 struct dmub_optc_state { 2959 uint32_t v_total_max; 2960 uint32_t v_total_min; 2961 uint32_t tg_inst; 2962 }; 2963 2964 struct dmub_rb_cmd_drr_update { 2965 struct dmub_cmd_header header; 2966 struct dmub_optc_state dmub_optc_state_req; 2967 }; 2968 2969 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2970 uint32_t pix_clk_100hz; 2971 uint8_t max_ramp_step; 2972 uint8_t pipes; 2973 uint8_t min_refresh_in_hz; 2974 uint8_t padding[1]; 2975 }; 2976 2977 struct dmub_cmd_fw_assisted_mclk_switch_config { 2978 uint8_t fams_enabled; 2979 uint8_t visual_confirm_enabled; 2980 uint8_t padding[2]; 2981 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2982 }; 2983 2984 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2985 struct dmub_cmd_header header; 2986 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2987 }; 2988 2989 /** 2990 * enum dmub_cmd_panel_cntl_type - Panel control command. 2991 */ 2992 enum dmub_cmd_panel_cntl_type { 2993 /** 2994 * Initializes embedded panel hardware blocks. 2995 */ 2996 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2997 /** 2998 * Queries backlight info for the embedded panel. 2999 */ 3000 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3001 }; 3002 3003 /** 3004 * struct dmub_cmd_panel_cntl_data - Panel control data. 3005 */ 3006 struct dmub_cmd_panel_cntl_data { 3007 uint32_t inst; /**< panel instance */ 3008 uint32_t current_backlight; /* in/out */ 3009 uint32_t bl_pwm_cntl; /* in/out */ 3010 uint32_t bl_pwm_period_cntl; /* in/out */ 3011 uint32_t bl_pwm_ref_div1; /* in/out */ 3012 uint8_t is_backlight_on : 1; /* in/out */ 3013 uint8_t is_powered_on : 1; /* in/out */ 3014 uint8_t padding[3]; 3015 uint32_t bl_pwm_ref_div2; /* in/out */ 3016 uint8_t reserved[4]; 3017 }; 3018 3019 /** 3020 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3021 */ 3022 struct dmub_rb_cmd_panel_cntl { 3023 struct dmub_cmd_header header; /**< header */ 3024 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3025 }; 3026 3027 /** 3028 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3029 */ 3030 struct dmub_cmd_lvtma_control_data { 3031 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3032 uint8_t reserved_0[3]; /**< For future use */ 3033 uint8_t panel_inst; /**< LVTMA control instance */ 3034 uint8_t reserved_1[3]; /**< For future use */ 3035 }; 3036 3037 /** 3038 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3039 */ 3040 struct dmub_rb_cmd_lvtma_control { 3041 /** 3042 * Command header. 3043 */ 3044 struct dmub_cmd_header header; 3045 /** 3046 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3047 */ 3048 struct dmub_cmd_lvtma_control_data data; 3049 }; 3050 3051 /** 3052 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3053 */ 3054 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3055 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3056 uint8_t is_usb; /**< is phy is usb */ 3057 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3058 uint8_t is_dp4; /**< is dp in 4 lane */ 3059 }; 3060 3061 /** 3062 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3063 */ 3064 struct dmub_rb_cmd_transmitter_query_dp_alt { 3065 struct dmub_cmd_header header; /**< header */ 3066 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3067 }; 3068 3069 /** 3070 * Maximum number of bytes a chunk sent to DMUB for parsing 3071 */ 3072 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3073 3074 /** 3075 * Represent a chunk of CEA blocks sent to DMUB for parsing 3076 */ 3077 struct dmub_cmd_send_edid_cea { 3078 uint16_t offset; /**< offset into the CEA block */ 3079 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3080 uint16_t cea_total_length; /**< total length of the CEA block */ 3081 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3082 uint8_t pad[3]; /**< padding and for future expansion */ 3083 }; 3084 3085 /** 3086 * Result of VSDB parsing from CEA block 3087 */ 3088 struct dmub_cmd_edid_cea_amd_vsdb { 3089 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3090 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3091 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3092 uint16_t min_frame_rate; /**< Maximum frame rate */ 3093 uint16_t max_frame_rate; /**< Minimum frame rate */ 3094 }; 3095 3096 /** 3097 * Result of sending a CEA chunk 3098 */ 3099 struct dmub_cmd_edid_cea_ack { 3100 uint16_t offset; /**< offset of the chunk into the CEA block */ 3101 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3102 uint8_t pad; /**< padding and for future expansion */ 3103 }; 3104 3105 /** 3106 * Specify whether the result is an ACK/NACK or the parsing has finished 3107 */ 3108 enum dmub_cmd_edid_cea_reply_type { 3109 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3110 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3111 }; 3112 3113 /** 3114 * Definition of a DMUB_CMD__EDID_CEA command. 3115 */ 3116 struct dmub_rb_cmd_edid_cea { 3117 struct dmub_cmd_header header; /**< Command header */ 3118 union dmub_cmd_edid_cea_data { 3119 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3120 struct dmub_cmd_edid_cea_output { /**< output with results */ 3121 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3122 union { 3123 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3124 struct dmub_cmd_edid_cea_ack ack; 3125 }; 3126 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3127 } data; /**< Command data */ 3128 3129 }; 3130 3131 /** 3132 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3133 */ 3134 struct dmub_cmd_cable_id_input { 3135 uint8_t phy_inst; /**< phy inst for cable id data */ 3136 }; 3137 3138 /** 3139 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3140 */ 3141 struct dmub_cmd_cable_id_output { 3142 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3143 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3144 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3145 uint8_t RESERVED :2; /**< reserved means not defined */ 3146 }; 3147 3148 /** 3149 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3150 */ 3151 struct dmub_rb_cmd_get_usbc_cable_id { 3152 struct dmub_cmd_header header; /**< Command header */ 3153 /** 3154 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3155 */ 3156 union dmub_cmd_cable_id_data { 3157 struct dmub_cmd_cable_id_input input; /**< Input */ 3158 struct dmub_cmd_cable_id_output output; /**< Output */ 3159 uint8_t output_raw; /**< Raw data output */ 3160 } data; 3161 }; 3162 3163 /** 3164 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3165 */ 3166 enum dmub_cmd_secure_display_type { 3167 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3168 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3169 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3170 }; 3171 3172 /** 3173 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3174 */ 3175 struct dmub_rb_cmd_secure_display { 3176 struct dmub_cmd_header header; 3177 /** 3178 * Data passed from driver to dmub firmware. 3179 */ 3180 struct dmub_cmd_roi_info { 3181 uint16_t x_start; 3182 uint16_t x_end; 3183 uint16_t y_start; 3184 uint16_t y_end; 3185 uint8_t otg_id; 3186 uint8_t phy_id; 3187 } roi_info; 3188 }; 3189 3190 /** 3191 * union dmub_rb_cmd - DMUB inbox command. 3192 */ 3193 union dmub_rb_cmd { 3194 /** 3195 * Elements shared with all commands. 3196 */ 3197 struct dmub_rb_cmd_common cmd_common; 3198 /** 3199 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3200 */ 3201 struct dmub_rb_cmd_read_modify_write read_modify_write; 3202 /** 3203 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3204 */ 3205 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3206 /** 3207 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3208 */ 3209 struct dmub_rb_cmd_burst_write burst_write; 3210 /** 3211 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3212 */ 3213 struct dmub_rb_cmd_reg_wait reg_wait; 3214 /** 3215 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3216 */ 3217 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3218 /** 3219 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3220 */ 3221 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3222 /** 3223 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3224 */ 3225 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3226 /** 3227 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3228 */ 3229 struct dmub_rb_cmd_dpphy_init dpphy_init; 3230 /** 3231 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3232 */ 3233 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3234 /** 3235 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3236 */ 3237 struct dmub_rb_cmd_psr_set_version psr_set_version; 3238 /** 3239 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3240 */ 3241 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3242 /** 3243 * Definition of a DMUB_CMD__PSR_ENABLE command. 3244 */ 3245 struct dmub_rb_cmd_psr_enable psr_enable; 3246 /** 3247 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3248 */ 3249 struct dmub_rb_cmd_psr_set_level psr_set_level; 3250 /** 3251 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3252 */ 3253 struct dmub_rb_cmd_psr_force_static psr_force_static; 3254 /** 3255 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3256 */ 3257 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3258 /** 3259 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3260 */ 3261 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3262 /** 3263 * Definition of a DMUB_CMD__HW_LOCK command. 3264 * Command is used by driver and FW. 3265 */ 3266 struct dmub_rb_cmd_lock_hw lock_hw; 3267 /** 3268 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3269 */ 3270 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3271 /** 3272 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3273 */ 3274 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3275 /** 3276 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3277 */ 3278 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3279 /** 3280 * Definition of a DMUB_CMD__MALL command. 3281 */ 3282 struct dmub_rb_cmd_mall mall; 3283 /** 3284 * Definition of a DMUB_CMD__CAB command. 3285 */ 3286 struct dmub_rb_cmd_cab_for_ss cab; 3287 3288 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3289 3290 /** 3291 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3292 */ 3293 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3294 3295 /** 3296 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3297 */ 3298 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3299 3300 /** 3301 * Definition of DMUB_CMD__PANEL_CNTL commands. 3302 */ 3303 struct dmub_rb_cmd_panel_cntl panel_cntl; 3304 /** 3305 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3306 */ 3307 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3308 3309 /** 3310 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3311 */ 3312 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3313 3314 /** 3315 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3316 */ 3317 struct dmub_rb_cmd_abm_set_level abm_set_level; 3318 3319 /** 3320 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3321 */ 3322 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3323 3324 /** 3325 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3326 */ 3327 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3328 3329 /** 3330 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3331 */ 3332 struct dmub_rb_cmd_abm_init_config abm_init_config; 3333 3334 /** 3335 * Definition of a DMUB_CMD__ABM_PAUSE command. 3336 */ 3337 struct dmub_rb_cmd_abm_pause abm_pause; 3338 3339 /** 3340 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3341 */ 3342 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3343 3344 /** 3345 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3346 */ 3347 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3348 3349 /** 3350 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3351 */ 3352 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3353 3354 /** 3355 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3356 */ 3357 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3358 struct dmub_rb_cmd_drr_update drr_update; 3359 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3360 3361 /** 3362 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3363 */ 3364 struct dmub_rb_cmd_lvtma_control lvtma_control; 3365 /** 3366 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3367 */ 3368 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3369 /** 3370 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3371 */ 3372 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3373 /** 3374 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3375 */ 3376 struct dmub_rb_cmd_set_config_access set_config_access; 3377 /** 3378 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3379 */ 3380 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3381 /** 3382 * Definition of a DMUB_CMD__EDID_CEA command. 3383 */ 3384 struct dmub_rb_cmd_edid_cea edid_cea; 3385 /** 3386 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3387 */ 3388 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3389 3390 /** 3391 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3392 */ 3393 struct dmub_rb_cmd_query_hpd_state query_hpd; 3394 /** 3395 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3396 */ 3397 struct dmub_rb_cmd_secure_display secure_display; 3398 3399 /** 3400 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3401 */ 3402 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3403 }; 3404 3405 /** 3406 * union dmub_rb_out_cmd - Outbox command 3407 */ 3408 union dmub_rb_out_cmd { 3409 /** 3410 * Parameters common to every command. 3411 */ 3412 struct dmub_rb_cmd_common cmd_common; 3413 /** 3414 * AUX reply command. 3415 */ 3416 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3417 /** 3418 * HPD notify command. 3419 */ 3420 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3421 /** 3422 * SET_CONFIG reply command. 3423 */ 3424 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3425 }; 3426 #pragma pack(pop) 3427 3428 3429 //============================================================================== 3430 //</DMUB_CMD>=================================================================== 3431 //============================================================================== 3432 //< DMUB_RB>==================================================================== 3433 //============================================================================== 3434 3435 #if defined(__cplusplus) 3436 extern "C" { 3437 #endif 3438 3439 /** 3440 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3441 */ 3442 struct dmub_rb_init_params { 3443 void *ctx; /**< Caller provided context pointer */ 3444 void *base_address; /**< CPU base address for ring's data */ 3445 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3446 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3447 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3448 }; 3449 3450 /** 3451 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3452 */ 3453 struct dmub_rb { 3454 void *base_address; /**< CPU address for the ring's data */ 3455 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3456 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3457 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3458 3459 void *ctx; /**< Caller provided context pointer */ 3460 void *dmub; /**< Pointer to the DMUB interface */ 3461 }; 3462 3463 /** 3464 * @brief Checks if the ringbuffer is empty. 3465 * 3466 * @param rb DMUB Ringbuffer 3467 * @return true if empty 3468 * @return false otherwise 3469 */ 3470 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3471 { 3472 return (rb->wrpt == rb->rptr); 3473 } 3474 3475 /** 3476 * @brief Checks if the ringbuffer is full 3477 * 3478 * @param rb DMUB Ringbuffer 3479 * @return true if full 3480 * @return false otherwise 3481 */ 3482 static inline bool dmub_rb_full(struct dmub_rb *rb) 3483 { 3484 uint32_t data_count; 3485 3486 if (rb->wrpt >= rb->rptr) 3487 data_count = rb->wrpt - rb->rptr; 3488 else 3489 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3490 3491 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3492 } 3493 3494 /** 3495 * @brief Pushes a command into the ringbuffer 3496 * 3497 * @param rb DMUB ringbuffer 3498 * @param cmd The command to push 3499 * @return true if the ringbuffer was not full 3500 * @return false otherwise 3501 */ 3502 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3503 const union dmub_rb_cmd *cmd) 3504 { 3505 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3506 const uint64_t *src = (const uint64_t *)cmd; 3507 uint8_t i; 3508 3509 if (dmub_rb_full(rb)) 3510 return false; 3511 3512 // copying data 3513 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3514 *dst++ = *src++; 3515 3516 rb->wrpt += DMUB_RB_CMD_SIZE; 3517 3518 if (rb->wrpt >= rb->capacity) 3519 rb->wrpt %= rb->capacity; 3520 3521 return true; 3522 } 3523 3524 /** 3525 * @brief Pushes a command into the DMUB outbox ringbuffer 3526 * 3527 * @param rb DMUB outbox ringbuffer 3528 * @param cmd Outbox command 3529 * @return true if not full 3530 * @return false otherwise 3531 */ 3532 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3533 const union dmub_rb_out_cmd *cmd) 3534 { 3535 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3536 const uint8_t *src = (const uint8_t *)cmd; 3537 3538 if (dmub_rb_full(rb)) 3539 return false; 3540 3541 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3542 3543 rb->wrpt += DMUB_RB_CMD_SIZE; 3544 3545 if (rb->wrpt >= rb->capacity) 3546 rb->wrpt %= rb->capacity; 3547 3548 return true; 3549 } 3550 3551 /** 3552 * @brief Returns the next unprocessed command in the ringbuffer. 3553 * 3554 * @param rb DMUB ringbuffer 3555 * @param cmd The command to return 3556 * @return true if not empty 3557 * @return false otherwise 3558 */ 3559 static inline bool dmub_rb_front(struct dmub_rb *rb, 3560 union dmub_rb_cmd **cmd) 3561 { 3562 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3563 3564 if (dmub_rb_empty(rb)) 3565 return false; 3566 3567 *cmd = (union dmub_rb_cmd *)rb_cmd; 3568 3569 return true; 3570 } 3571 3572 /** 3573 * @brief Determines the next ringbuffer offset. 3574 * 3575 * @param rb DMUB inbox ringbuffer 3576 * @param num_cmds Number of commands 3577 * @param next_rptr The next offset in the ringbuffer 3578 */ 3579 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3580 uint32_t num_cmds, 3581 uint32_t *next_rptr) 3582 { 3583 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3584 3585 if (*next_rptr >= rb->capacity) 3586 *next_rptr %= rb->capacity; 3587 } 3588 3589 /** 3590 * @brief Returns a pointer to a command in the inbox. 3591 * 3592 * @param rb DMUB inbox ringbuffer 3593 * @param cmd The inbox command to return 3594 * @param rptr The ringbuffer offset 3595 * @return true if not empty 3596 * @return false otherwise 3597 */ 3598 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3599 union dmub_rb_cmd **cmd, 3600 uint32_t rptr) 3601 { 3602 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3603 3604 if (dmub_rb_empty(rb)) 3605 return false; 3606 3607 *cmd = (union dmub_rb_cmd *)rb_cmd; 3608 3609 return true; 3610 } 3611 3612 /** 3613 * @brief Returns the next unprocessed command in the outbox. 3614 * 3615 * @param rb DMUB outbox ringbuffer 3616 * @param cmd The outbox command to return 3617 * @return true if not empty 3618 * @return false otherwise 3619 */ 3620 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3621 union dmub_rb_out_cmd *cmd) 3622 { 3623 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3624 uint64_t *dst = (uint64_t *)cmd; 3625 uint8_t i; 3626 3627 if (dmub_rb_empty(rb)) 3628 return false; 3629 3630 // copying data 3631 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3632 *dst++ = *src++; 3633 3634 return true; 3635 } 3636 3637 /** 3638 * @brief Removes the front entry in the ringbuffer. 3639 * 3640 * @param rb DMUB ringbuffer 3641 * @return true if the command was removed 3642 * @return false if there were no commands 3643 */ 3644 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3645 { 3646 if (dmub_rb_empty(rb)) 3647 return false; 3648 3649 rb->rptr += DMUB_RB_CMD_SIZE; 3650 3651 if (rb->rptr >= rb->capacity) 3652 rb->rptr %= rb->capacity; 3653 3654 return true; 3655 } 3656 3657 /** 3658 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3659 * 3660 * Avoids a race condition where DMCUB accesses memory while 3661 * there are still writes in flight to framebuffer. 3662 * 3663 * @param rb DMUB ringbuffer 3664 */ 3665 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3666 { 3667 uint32_t rptr = rb->rptr; 3668 uint32_t wptr = rb->wrpt; 3669 3670 while (rptr != wptr) { 3671 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3672 uint8_t i; 3673 3674 /* Don't remove this. 3675 * The contents need to actually be read from the ring buffer 3676 * for this function to be effective. 3677 */ 3678 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3679 (void)READ_ONCE(*data++); 3680 3681 rptr += DMUB_RB_CMD_SIZE; 3682 if (rptr >= rb->capacity) 3683 rptr %= rb->capacity; 3684 } 3685 } 3686 3687 /** 3688 * @brief Initializes a DMCUB ringbuffer 3689 * 3690 * @param rb DMUB ringbuffer 3691 * @param init_params initial configuration for the ringbuffer 3692 */ 3693 static inline void dmub_rb_init(struct dmub_rb *rb, 3694 struct dmub_rb_init_params *init_params) 3695 { 3696 rb->base_address = init_params->base_address; 3697 rb->capacity = init_params->capacity; 3698 rb->rptr = init_params->read_ptr; 3699 rb->wrpt = init_params->write_ptr; 3700 } 3701 3702 /** 3703 * @brief Copies output data from in/out commands into the given command. 3704 * 3705 * @param rb DMUB ringbuffer 3706 * @param cmd Command to copy data into 3707 */ 3708 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3709 union dmub_rb_cmd *cmd) 3710 { 3711 // Copy rb entry back into command 3712 uint8_t *rd_ptr = (rb->rptr == 0) ? 3713 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3714 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3715 3716 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3717 } 3718 3719 #if defined(__cplusplus) 3720 } 3721 #endif 3722 3723 //============================================================================== 3724 //</DMUB_RB>==================================================================== 3725 //============================================================================== 3726 3727 #endif /* _DMUB_CMD_H_ */ 3728