1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0x9cf8f05fe 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 35 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 #define SET_ABM_PIPE_NORMAL 1 62 63 /* Maximum number of streams on any ASIC. */ 64 #define DMUB_MAX_STREAMS 6 65 66 /* Maximum number of planes on any ASIC. */ 67 #define DMUB_MAX_PLANES 6 68 69 #ifndef PHYSICAL_ADDRESS_LOC 70 #define PHYSICAL_ADDRESS_LOC union large_integer 71 #endif 72 73 #ifndef dmub_memcpy 74 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 75 #endif 76 77 #ifndef dmub_memset 78 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 79 #endif 80 81 #if defined(__cplusplus) 82 extern "C" { 83 #endif 84 85 #ifndef dmub_udelay 86 #define dmub_udelay(microseconds) udelay(microseconds) 87 #endif 88 89 union dmub_addr { 90 struct { 91 uint32_t low_part; 92 uint32_t high_part; 93 } u; 94 uint64_t quad_part; 95 }; 96 97 union dmub_psr_debug_flags { 98 struct { 99 uint32_t visual_confirm : 1; 100 uint32_t use_hw_lock_mgr : 1; 101 uint32_t log_line_nums : 1; 102 } bitfields; 103 104 uint32_t u32All; 105 }; 106 107 #if defined(__cplusplus) 108 } 109 #endif 110 111 112 113 //============================================================================== 114 //</DMUB_TYPES>================================================================= 115 //============================================================================== 116 //< DMUB_META>================================================================== 117 //============================================================================== 118 #pragma pack(push, 1) 119 120 /* Magic value for identifying dmub_fw_meta_info */ 121 #define DMUB_FW_META_MAGIC 0x444D5542 122 123 /* Offset from the end of the file to the dmub_fw_meta_info */ 124 #define DMUB_FW_META_OFFSET 0x24 125 126 /** 127 * struct dmub_fw_meta_info - metadata associated with fw binary 128 * 129 * NOTE: This should be considered a stable API. Fields should 130 * not be repurposed or reordered. New fields should be 131 * added instead to extend the structure. 132 * 133 * @magic_value: magic value identifying DMUB firmware meta info 134 * @fw_region_size: size of the firmware state region 135 * @trace_buffer_size: size of the tracebuffer region 136 * @fw_version: the firmware version information 137 * @dal_fw: 1 if the firmware is DAL 138 */ 139 struct dmub_fw_meta_info { 140 uint32_t magic_value; 141 uint32_t fw_region_size; 142 uint32_t trace_buffer_size; 143 uint32_t fw_version; 144 uint8_t dal_fw; 145 uint8_t reserved[3]; 146 }; 147 148 /* Ensure that the structure remains 64 bytes. */ 149 union dmub_fw_meta { 150 struct dmub_fw_meta_info info; 151 uint8_t reserved[64]; 152 }; 153 154 #pragma pack(pop) 155 156 //============================================================================== 157 //< DMUB_STATUS>================================================================ 158 //============================================================================== 159 160 /** 161 * DMCUB scratch registers can be used to determine firmware status. 162 * Current scratch register usage is as follows: 163 * 164 * SCRATCH0: FW Boot Status register 165 * SCRATCH15: FW Boot Options register 166 */ 167 168 /* Register bit definition for SCRATCH0 */ 169 union dmub_fw_boot_status { 170 struct { 171 uint32_t dal_fw : 1; 172 uint32_t mailbox_rdy : 1; 173 uint32_t optimized_init_done : 1; 174 uint32_t restore_required : 1; 175 } bits; 176 uint32_t all; 177 }; 178 179 enum dmub_fw_boot_status_bit { 180 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 181 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 182 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 183 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 184 }; 185 186 /* Register bit definition for SCRATCH15 */ 187 union dmub_fw_boot_options { 188 struct { 189 uint32_t pemu_env : 1; 190 uint32_t fpga_env : 1; 191 uint32_t optimized_init : 1; 192 uint32_t reserved : 29; 193 } bits; 194 uint32_t all; 195 }; 196 197 enum dmub_fw_boot_options_bit { 198 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 199 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 200 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 201 }; 202 203 //============================================================================== 204 //</DMUB_STATUS>================================================================ 205 //============================================================================== 206 //< DMUB_VBIOS>================================================================= 207 //============================================================================== 208 209 /* 210 * Command IDs should be treated as stable ABI. 211 * Do not reuse or modify IDs. 212 */ 213 214 enum dmub_cmd_vbios_type { 215 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 216 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 217 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 218 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 219 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 220 }; 221 222 //============================================================================== 223 //</DMUB_VBIOS>================================================================= 224 //============================================================================== 225 //< DMUB_GPINT>================================================================= 226 //============================================================================== 227 228 /** 229 * The shifts and masks below may alternatively be used to format and read 230 * the command register bits. 231 */ 232 233 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 234 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 235 236 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 237 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 238 239 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 240 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 241 242 /** 243 * Command responses. 244 */ 245 246 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 247 248 /** 249 * The register format for sending a command via the GPINT. 250 */ 251 union dmub_gpint_data_register { 252 struct { 253 uint32_t param : 16; 254 uint32_t command_code : 12; 255 uint32_t status : 4; 256 } bits; 257 uint32_t all; 258 }; 259 260 /* 261 * Command IDs should be treated as stable ABI. 262 * Do not reuse or modify IDs. 263 */ 264 265 enum dmub_gpint_command { 266 DMUB_GPINT__INVALID_COMMAND = 0, 267 DMUB_GPINT__GET_FW_VERSION = 1, 268 DMUB_GPINT__STOP_FW = 2, 269 DMUB_GPINT__GET_PSR_STATE = 7, 270 /** 271 * DESC: Notifies DMCUB of the currently active streams. 272 * ARGS: Stream mask, 1 bit per active stream index. 273 */ 274 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 275 }; 276 277 //============================================================================== 278 //</DMUB_GPINT>================================================================= 279 //============================================================================== 280 //< DMUB_CMD>=================================================================== 281 //============================================================================== 282 283 #define DMUB_RB_CMD_SIZE 64 284 #define DMUB_RB_MAX_ENTRY 128 285 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 286 #define REG_SET_MASK 0xFFFF 287 288 /* 289 * Command IDs should be treated as stable ABI. 290 * Do not reuse or modify IDs. 291 */ 292 293 enum dmub_cmd_type { 294 DMUB_CMD__NULL = 0, 295 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 296 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 297 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 298 DMUB_CMD__REG_REG_WAIT = 4, 299 DMUB_CMD__PLAT_54186_WA = 5, 300 DMUB_CMD__PSR = 64, 301 DMUB_CMD__ABM = 66, 302 DMUB_CMD__HW_LOCK = 69, 303 DMUB_CMD__DP_AUX_ACCESS = 70, 304 DMUB_CMD__OUTBOX1_ENABLE = 71, 305 DMUB_CMD__VBIOS = 128, 306 }; 307 308 enum dmub_out_cmd_type { 309 DMUB_OUT_CMD__NULL = 0, 310 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 311 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 312 }; 313 314 #pragma pack(push, 1) 315 316 struct dmub_cmd_header { 317 unsigned int type : 8; 318 unsigned int sub_type : 8; 319 unsigned int reserved0 : 8; 320 unsigned int payload_bytes : 6; /* up to 60 bytes */ 321 unsigned int reserved1 : 2; 322 }; 323 324 /* 325 * Read modify write 326 * 327 * 60 payload bytes can hold up to 5 sets of read modify writes, 328 * each take 3 dwords. 329 * 330 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 331 * 332 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 333 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 334 */ 335 struct dmub_cmd_read_modify_write_sequence { 336 uint32_t addr; 337 uint32_t modify_mask; 338 uint32_t modify_value; 339 }; 340 341 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 342 struct dmub_rb_cmd_read_modify_write { 343 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 344 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 345 }; 346 347 /* 348 * Update a register with specified masks and values sequeunce 349 * 350 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 351 * 352 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 353 * 354 * 355 * USE CASE: 356 * 1. auto-increment register where additional read would update pointer and produce wrong result 357 * 2. toggle a bit without read in the middle 358 */ 359 360 struct dmub_cmd_reg_field_update_sequence { 361 uint32_t modify_mask; // 0xffff'ffff to skip initial read 362 uint32_t modify_value; 363 }; 364 365 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 366 struct dmub_rb_cmd_reg_field_update_sequence { 367 struct dmub_cmd_header header; 368 uint32_t addr; 369 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 370 }; 371 372 /* 373 * Burst write 374 * 375 * support use case such as writing out LUTs. 376 * 377 * 60 payload bytes can hold up to 14 values to write to given address 378 * 379 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 380 */ 381 #define DMUB_BURST_WRITE_VALUES__MAX 14 382 struct dmub_rb_cmd_burst_write { 383 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 384 uint32_t addr; 385 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 386 }; 387 388 389 struct dmub_rb_cmd_common { 390 struct dmub_cmd_header header; 391 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 392 }; 393 394 struct dmub_cmd_reg_wait_data { 395 uint32_t addr; 396 uint32_t mask; 397 uint32_t condition_field_value; 398 uint32_t time_out_us; 399 }; 400 401 struct dmub_rb_cmd_reg_wait { 402 struct dmub_cmd_header header; 403 struct dmub_cmd_reg_wait_data reg_wait; 404 }; 405 406 struct dmub_cmd_PLAT_54186_wa { 407 uint32_t DCSURF_SURFACE_CONTROL; 408 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 409 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 410 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 411 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 412 struct { 413 uint8_t hubp_inst : 4; 414 uint8_t tmz_surface : 1; 415 uint8_t immediate :1; 416 uint8_t vmid : 4; 417 uint8_t grph_stereo : 1; 418 uint32_t reserved : 21; 419 } flip_params; 420 uint32_t reserved[9]; 421 }; 422 423 struct dmub_rb_cmd_PLAT_54186_wa { 424 struct dmub_cmd_header header; 425 struct dmub_cmd_PLAT_54186_wa flip; 426 }; 427 428 struct dmub_cmd_digx_encoder_control_data { 429 union dig_encoder_control_parameters_v1_5 dig; 430 }; 431 432 struct dmub_rb_cmd_digx_encoder_control { 433 struct dmub_cmd_header header; 434 struct dmub_cmd_digx_encoder_control_data encoder_control; 435 }; 436 437 struct dmub_cmd_set_pixel_clock_data { 438 struct set_pixel_clock_parameter_v1_7 clk; 439 }; 440 441 struct dmub_rb_cmd_set_pixel_clock { 442 struct dmub_cmd_header header; 443 struct dmub_cmd_set_pixel_clock_data pixel_clock; 444 }; 445 446 struct dmub_cmd_enable_disp_power_gating_data { 447 struct enable_disp_power_gating_parameters_v2_1 pwr; 448 }; 449 450 struct dmub_rb_cmd_enable_disp_power_gating { 451 struct dmub_cmd_header header; 452 struct dmub_cmd_enable_disp_power_gating_data power_gating; 453 }; 454 455 struct dmub_cmd_dig1_transmitter_control_data { 456 struct dig_transmitter_control_parameters_v1_6 dig; 457 }; 458 459 struct dmub_rb_cmd_dig1_transmitter_control { 460 struct dmub_cmd_header header; 461 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 462 }; 463 464 struct dmub_rb_cmd_dpphy_init { 465 struct dmub_cmd_header header; 466 uint8_t reserved[60]; 467 }; 468 469 enum dp_aux_request_action { 470 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 471 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 472 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 473 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 474 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 475 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 476 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 477 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 478 }; 479 480 /* DP AUX command */ 481 struct aux_transaction_parameters { 482 uint8_t is_i2c_over_aux; 483 uint8_t action; 484 uint8_t length; 485 uint8_t pad; 486 uint32_t address; 487 uint8_t data[16]; 488 }; 489 490 struct dmub_cmd_dp_aux_control_data { 491 uint32_t handle; 492 uint8_t port_index; 493 uint8_t sw_crc_enabled; 494 uint16_t timeout; 495 struct aux_transaction_parameters dpaux; 496 }; 497 498 struct dmub_rb_cmd_dp_aux_access { 499 struct dmub_cmd_header header; 500 struct dmub_cmd_dp_aux_control_data aux_control; 501 }; 502 503 struct dmub_rb_cmd_outbox1_enable { 504 struct dmub_cmd_header header; 505 uint32_t enable; 506 }; 507 508 /* DP AUX Reply command - OutBox Cmd */ 509 struct aux_reply_data { 510 uint8_t command; 511 uint8_t length; 512 uint8_t pad[2]; 513 uint8_t data[16]; 514 }; 515 516 struct aux_reply_control_data { 517 uint32_t handle; 518 uint8_t phy_port_index; 519 uint8_t result; 520 uint16_t pad; 521 }; 522 523 struct dmub_rb_cmd_dp_aux_reply { 524 struct dmub_cmd_header header; 525 struct aux_reply_control_data control; 526 struct aux_reply_data reply_data; 527 }; 528 529 struct dp_hpd_data { 530 uint8_t phy_port_index; 531 uint8_t hpd_type; 532 uint8_t hpd_status; 533 uint8_t pad; 534 }; 535 536 struct dmub_rb_cmd_dp_hpd_notify { 537 struct dmub_cmd_header header; 538 struct dp_hpd_data hpd_data; 539 }; 540 541 /* 542 * Command IDs should be treated as stable ABI. 543 * Do not reuse or modify IDs. 544 */ 545 546 enum dmub_cmd_psr_type { 547 DMUB_CMD__PSR_SET_VERSION = 0, 548 DMUB_CMD__PSR_COPY_SETTINGS = 1, 549 DMUB_CMD__PSR_ENABLE = 2, 550 DMUB_CMD__PSR_DISABLE = 3, 551 DMUB_CMD__PSR_SET_LEVEL = 4, 552 }; 553 554 enum psr_version { 555 PSR_VERSION_1 = 0, 556 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 557 }; 558 559 struct dmub_cmd_psr_copy_settings_data { 560 union dmub_psr_debug_flags debug; 561 uint16_t psr_level; 562 uint8_t dpp_inst; 563 uint8_t mpcc_inst; 564 uint8_t opp_inst; 565 uint8_t otg_inst; 566 uint8_t digfe_inst; 567 uint8_t digbe_inst; 568 uint8_t dpphy_inst; 569 uint8_t aux_inst; 570 uint8_t smu_optimizations_en; 571 uint8_t frame_delay; 572 uint8_t frame_cap_ind; 573 uint8_t pad[3]; 574 uint16_t init_sdp_deadline; 575 uint16_t pad2; 576 }; 577 578 struct dmub_rb_cmd_psr_copy_settings { 579 struct dmub_cmd_header header; 580 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 581 }; 582 583 struct dmub_cmd_psr_set_level_data { 584 uint16_t psr_level; 585 uint8_t pad[2]; 586 }; 587 588 struct dmub_rb_cmd_psr_set_level { 589 struct dmub_cmd_header header; 590 struct dmub_cmd_psr_set_level_data psr_set_level_data; 591 }; 592 593 struct dmub_rb_cmd_psr_enable { 594 struct dmub_cmd_header header; 595 }; 596 597 struct dmub_cmd_psr_set_version_data { 598 enum psr_version version; // PSR version 1 or 2 599 }; 600 601 struct dmub_rb_cmd_psr_set_version { 602 struct dmub_cmd_header header; 603 struct dmub_cmd_psr_set_version_data psr_set_version_data; 604 }; 605 606 union dmub_hw_lock_flags { 607 struct { 608 uint8_t lock_pipe : 1; 609 uint8_t lock_cursor : 1; 610 uint8_t lock_dig : 1; 611 uint8_t triple_buffer_lock : 1; 612 } bits; 613 614 uint8_t u8All; 615 }; 616 617 struct dmub_hw_lock_inst_flags { 618 uint8_t otg_inst; 619 uint8_t opp_inst; 620 uint8_t dig_inst; 621 uint8_t pad; 622 }; 623 624 enum hw_lock_client { 625 HW_LOCK_CLIENT_DRIVER = 0, 626 HW_LOCK_CLIENT_FW, 627 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 628 }; 629 630 struct dmub_cmd_lock_hw_data { 631 enum hw_lock_client client; 632 struct dmub_hw_lock_inst_flags inst_flags; 633 union dmub_hw_lock_flags hw_locks; 634 uint8_t lock; 635 uint8_t should_release; 636 uint8_t pad; 637 }; 638 639 struct dmub_rb_cmd_lock_hw { 640 struct dmub_cmd_header header; 641 struct dmub_cmd_lock_hw_data lock_hw_data; 642 }; 643 644 enum dmub_cmd_abm_type { 645 DMUB_CMD__ABM_INIT_CONFIG = 0, 646 DMUB_CMD__ABM_SET_PIPE = 1, 647 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 648 DMUB_CMD__ABM_SET_LEVEL = 3, 649 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 650 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 651 }; 652 653 #define NUM_AMBI_LEVEL 5 654 #define NUM_AGGR_LEVEL 4 655 #define NUM_POWER_FN_SEGS 8 656 #define NUM_BL_CURVE_SEGS 16 657 658 /* 659 * Parameters for ABM2.4 algorithm. 660 * Padded explicitly to 32-bit boundary. 661 */ 662 struct abm_config_table { 663 /* Parameters for crgb conversion */ 664 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 665 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 666 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 667 668 /* Parameters for custom curve */ 669 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 670 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 671 672 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 673 uint16_t min_abm_backlight; // 121B 674 675 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 676 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 677 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 678 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 679 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 680 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 681 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 682 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 683 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 684 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 685 uint8_t pad3[3]; // 228B 686 }; 687 688 struct dmub_cmd_abm_set_pipe_data { 689 uint8_t otg_inst; 690 uint8_t panel_inst; 691 uint8_t set_pipe_option; 692 uint8_t ramping_boundary; // TODO: Remove this 693 }; 694 695 struct dmub_rb_cmd_abm_set_pipe { 696 struct dmub_cmd_header header; 697 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 698 }; 699 700 struct dmub_cmd_abm_set_backlight_data { 701 uint32_t frame_ramp; 702 uint32_t backlight_user_level; 703 }; 704 705 struct dmub_rb_cmd_abm_set_backlight { 706 struct dmub_cmd_header header; 707 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 708 }; 709 710 struct dmub_cmd_abm_set_level_data { 711 uint32_t level; 712 }; 713 714 struct dmub_rb_cmd_abm_set_level { 715 struct dmub_cmd_header header; 716 struct dmub_cmd_abm_set_level_data abm_set_level_data; 717 }; 718 719 struct dmub_cmd_abm_set_ambient_level_data { 720 uint32_t ambient_lux; 721 }; 722 723 struct dmub_rb_cmd_abm_set_ambient_level { 724 struct dmub_cmd_header header; 725 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 726 }; 727 728 struct dmub_cmd_abm_set_pwm_frac_data { 729 uint32_t fractional_pwm; 730 }; 731 732 struct dmub_rb_cmd_abm_set_pwm_frac { 733 struct dmub_cmd_header header; 734 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 735 }; 736 737 struct dmub_cmd_abm_init_config_data { 738 union dmub_addr src; 739 uint16_t bytes; 740 }; 741 742 struct dmub_rb_cmd_abm_init_config { 743 struct dmub_cmd_header header; 744 struct dmub_cmd_abm_init_config_data abm_init_config_data; 745 }; 746 747 union dmub_rb_cmd { 748 struct dmub_rb_cmd_lock_hw lock_hw; 749 struct dmub_rb_cmd_read_modify_write read_modify_write; 750 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 751 struct dmub_rb_cmd_burst_write burst_write; 752 struct dmub_rb_cmd_reg_wait reg_wait; 753 struct dmub_rb_cmd_common cmd_common; 754 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 755 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 756 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 757 struct dmub_rb_cmd_dpphy_init dpphy_init; 758 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 759 struct dmub_rb_cmd_psr_set_version psr_set_version; 760 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 761 struct dmub_rb_cmd_psr_enable psr_enable; 762 struct dmub_rb_cmd_psr_set_level psr_set_level; 763 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 764 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 765 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 766 struct dmub_rb_cmd_abm_set_level abm_set_level; 767 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 768 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 769 struct dmub_rb_cmd_abm_init_config abm_init_config; 770 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 771 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 772 }; 773 774 union dmub_rb_out_cmd { 775 struct dmub_rb_cmd_common cmd_common; 776 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 777 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 778 }; 779 #pragma pack(pop) 780 781 782 //============================================================================== 783 //</DMUB_CMD>=================================================================== 784 //============================================================================== 785 //< DMUB_RB>==================================================================== 786 //============================================================================== 787 788 #if defined(__cplusplus) 789 extern "C" { 790 #endif 791 792 struct dmub_rb_init_params { 793 void *ctx; 794 void *base_address; 795 uint32_t capacity; 796 uint32_t read_ptr; 797 uint32_t write_ptr; 798 }; 799 800 struct dmub_rb { 801 void *base_address; 802 uint32_t data_count; 803 uint32_t rptr; 804 uint32_t wrpt; 805 uint32_t capacity; 806 807 void *ctx; 808 void *dmub; 809 }; 810 811 812 static inline bool dmub_rb_empty(struct dmub_rb *rb) 813 { 814 return (rb->wrpt == rb->rptr); 815 } 816 817 static inline bool dmub_rb_full(struct dmub_rb *rb) 818 { 819 uint32_t data_count; 820 821 if (rb->wrpt >= rb->rptr) 822 data_count = rb->wrpt - rb->rptr; 823 else 824 data_count = rb->capacity - (rb->rptr - rb->wrpt); 825 826 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 827 } 828 829 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 830 const union dmub_rb_cmd *cmd) 831 { 832 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 833 const uint64_t *src = (const uint64_t *)cmd; 834 int i; 835 836 if (dmub_rb_full(rb)) 837 return false; 838 839 // copying data 840 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 841 *dst++ = *src++; 842 843 rb->wrpt += DMUB_RB_CMD_SIZE; 844 845 if (rb->wrpt >= rb->capacity) 846 rb->wrpt %= rb->capacity; 847 848 return true; 849 } 850 851 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 852 const union dmub_rb_out_cmd *cmd) 853 { 854 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 855 const uint8_t *src = (uint8_t *)cmd; 856 857 if (dmub_rb_full(rb)) 858 return false; 859 860 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 861 862 rb->wrpt += DMUB_RB_CMD_SIZE; 863 864 if (rb->wrpt >= rb->capacity) 865 rb->wrpt %= rb->capacity; 866 867 return true; 868 } 869 870 static inline bool dmub_rb_front(struct dmub_rb *rb, 871 union dmub_rb_cmd *cmd) 872 { 873 uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 874 875 if (dmub_rb_empty(rb)) 876 return false; 877 878 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 879 880 return true; 881 } 882 883 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 884 union dmub_rb_out_cmd *cmd) 885 { 886 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 887 uint64_t *dst = (uint64_t *)cmd; 888 int i; 889 890 if (dmub_rb_empty(rb)) 891 return false; 892 893 // copying data 894 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 895 *dst++ = *src++; 896 897 return true; 898 } 899 900 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 901 { 902 if (dmub_rb_empty(rb)) 903 return false; 904 905 rb->rptr += DMUB_RB_CMD_SIZE; 906 907 if (rb->rptr >= rb->capacity) 908 rb->rptr %= rb->capacity; 909 910 return true; 911 } 912 913 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 914 { 915 uint32_t rptr = rb->rptr; 916 uint32_t wptr = rb->wrpt; 917 918 while (rptr != wptr) { 919 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 920 int i; 921 922 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 923 *data++; 924 925 rptr += DMUB_RB_CMD_SIZE; 926 if (rptr >= rb->capacity) 927 rptr %= rb->capacity; 928 } 929 } 930 931 static inline void dmub_rb_init(struct dmub_rb *rb, 932 struct dmub_rb_init_params *init_params) 933 { 934 rb->base_address = init_params->base_address; 935 rb->capacity = init_params->capacity; 936 rb->rptr = init_params->read_ptr; 937 rb->wrpt = init_params->write_ptr; 938 } 939 940 #if defined(__cplusplus) 941 } 942 #endif 943 944 //============================================================================== 945 //</DMUB_RB>==================================================================== 946 //============================================================================== 947 948 #endif /* _DMUB_CMD_H_ */ 949