1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 #pragma pack(push, 1) 166 /** 167 * union dmub_addr - DMUB physical/virtual 64-bit address. 168 */ 169 union dmub_addr { 170 struct { 171 uint32_t low_part; /**< Lower 32 bits */ 172 uint32_t high_part; /**< Upper 32 bits */ 173 } u; /*<< Low/high bit access */ 174 uint64_t quad_part; /*<< 64 bit address */ 175 }; 176 #pragma pack(pop) 177 178 /** 179 * Dirty rect definition. 180 */ 181 struct dmub_rect { 182 /** 183 * Dirty rect x offset. 184 */ 185 uint32_t x; 186 187 /** 188 * Dirty rect y offset. 189 */ 190 uint32_t y; 191 192 /** 193 * Dirty rect width. 194 */ 195 uint32_t width; 196 197 /** 198 * Dirty rect height. 199 */ 200 uint32_t height; 201 }; 202 203 /** 204 * Flags that can be set by driver to change some PSR behaviour. 205 */ 206 union dmub_psr_debug_flags { 207 /** 208 * Debug flags. 209 */ 210 struct { 211 /** 212 * Enable visual confirm in FW. 213 */ 214 uint32_t visual_confirm : 1; 215 216 /** 217 * Force all selective updates to bw full frame updates. 218 */ 219 uint32_t force_full_frame_update : 1; 220 221 /** 222 * Use HW Lock Mgr object to do HW locking in FW. 223 */ 224 uint32_t use_hw_lock_mgr : 1; 225 226 /** 227 * Use TPS3 signal when restore main link. 228 */ 229 uint32_t force_wakeup_by_tps3 : 1; 230 231 /** 232 * Back to back flip, therefore cannot power down PHY 233 */ 234 uint32_t back_to_back_flip : 1; 235 236 } bitfields; 237 238 /** 239 * Union for debug flags. 240 */ 241 uint32_t u32All; 242 }; 243 244 /** 245 * DMUB visual confirm color 246 */ 247 struct dmub_feature_caps { 248 /** 249 * Max PSR version supported by FW. 250 */ 251 uint8_t psr; 252 uint8_t fw_assisted_mclk_switch; 253 uint8_t reserved[6]; 254 }; 255 256 struct dmub_visual_confirm_color { 257 /** 258 * Maximum 10 bits color value 259 */ 260 uint16_t color_r_cr; 261 uint16_t color_g_y; 262 uint16_t color_b_cb; 263 uint16_t panel_inst; 264 }; 265 266 #if defined(__cplusplus) 267 } 268 #endif 269 270 //============================================================================== 271 //</DMUB_TYPES>================================================================= 272 //============================================================================== 273 //< DMUB_META>================================================================== 274 //============================================================================== 275 #pragma pack(push, 1) 276 277 /* Magic value for identifying dmub_fw_meta_info */ 278 #define DMUB_FW_META_MAGIC 0x444D5542 279 280 /* Offset from the end of the file to the dmub_fw_meta_info */ 281 #define DMUB_FW_META_OFFSET 0x24 282 283 /** 284 * struct dmub_fw_meta_info - metadata associated with fw binary 285 * 286 * NOTE: This should be considered a stable API. Fields should 287 * not be repurposed or reordered. New fields should be 288 * added instead to extend the structure. 289 * 290 * @magic_value: magic value identifying DMUB firmware meta info 291 * @fw_region_size: size of the firmware state region 292 * @trace_buffer_size: size of the tracebuffer region 293 * @fw_version: the firmware version information 294 * @dal_fw: 1 if the firmware is DAL 295 */ 296 struct dmub_fw_meta_info { 297 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 298 uint32_t fw_region_size; /**< size of the firmware state region */ 299 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 300 uint32_t fw_version; /**< the firmware version information */ 301 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 302 uint8_t reserved[3]; /**< padding bits */ 303 }; 304 305 /** 306 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 307 */ 308 union dmub_fw_meta { 309 struct dmub_fw_meta_info info; /**< metadata info */ 310 uint8_t reserved[64]; /**< padding bits */ 311 }; 312 313 #pragma pack(pop) 314 315 //============================================================================== 316 //< DMUB Trace Buffer>================================================================ 317 //============================================================================== 318 /** 319 * dmub_trace_code_t - firmware trace code, 32-bits 320 */ 321 typedef uint32_t dmub_trace_code_t; 322 323 /** 324 * struct dmcub_trace_buf_entry - Firmware trace entry 325 */ 326 struct dmcub_trace_buf_entry { 327 dmub_trace_code_t trace_code; /**< trace code for the event */ 328 uint32_t tick_count; /**< the tick count at time of trace */ 329 uint32_t param0; /**< trace defined parameter 0 */ 330 uint32_t param1; /**< trace defined parameter 1 */ 331 }; 332 333 //============================================================================== 334 //< DMUB_STATUS>================================================================ 335 //============================================================================== 336 337 /** 338 * DMCUB scratch registers can be used to determine firmware status. 339 * Current scratch register usage is as follows: 340 * 341 * SCRATCH0: FW Boot Status register 342 * SCRATCH5: LVTMA Status Register 343 * SCRATCH15: FW Boot Options register 344 */ 345 346 /** 347 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 348 */ 349 union dmub_fw_boot_status { 350 struct { 351 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 352 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 353 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 354 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 355 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 356 uint32_t reserved : 1; 357 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 358 359 } bits; /**< status bits */ 360 uint32_t all; /**< 32-bit access to status bits */ 361 }; 362 363 /** 364 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 365 */ 366 enum dmub_fw_boot_status_bit { 367 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 368 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 369 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 370 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 371 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 372 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 373 }; 374 375 /* Register bit definition for SCRATCH5 */ 376 union dmub_lvtma_status { 377 struct { 378 uint32_t psp_ok : 1; 379 uint32_t edp_on : 1; 380 uint32_t reserved : 30; 381 } bits; 382 uint32_t all; 383 }; 384 385 enum dmub_lvtma_status_bit { 386 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 387 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 388 }; 389 390 /** 391 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 392 */ 393 union dmub_fw_boot_options { 394 struct { 395 uint32_t pemu_env : 1; /**< 1 if PEMU */ 396 uint32_t fpga_env : 1; /**< 1 if FPGA */ 397 uint32_t optimized_init : 1; /**< 1 if optimized init */ 398 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 399 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 400 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 401 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 402 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 403 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 404 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 405 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 406 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 407 uint32_t power_optimization: 1; 408 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 409 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 410 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 411 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 412 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 413 414 uint32_t reserved : 15; /**< reserved */ 415 } bits; /**< boot bits */ 416 uint32_t all; /**< 32-bit access to bits */ 417 }; 418 419 enum dmub_fw_boot_options_bit { 420 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 421 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 422 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 423 }; 424 425 //============================================================================== 426 //</DMUB_STATUS>================================================================ 427 //============================================================================== 428 //< DMUB_VBIOS>================================================================= 429 //============================================================================== 430 431 /* 432 * enum dmub_cmd_vbios_type - VBIOS commands. 433 * 434 * Command IDs should be treated as stable ABI. 435 * Do not reuse or modify IDs. 436 */ 437 enum dmub_cmd_vbios_type { 438 /** 439 * Configures the DIG encoder. 440 */ 441 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 442 /** 443 * Controls the PHY. 444 */ 445 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 446 /** 447 * Sets the pixel clock/symbol clock. 448 */ 449 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 450 /** 451 * Enables or disables power gating. 452 */ 453 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 454 /** 455 * Controls embedded panels. 456 */ 457 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 458 /** 459 * Query DP alt status on a transmitter. 460 */ 461 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 462 /** 463 * Controls domain power gating 464 */ 465 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 466 }; 467 468 //============================================================================== 469 //</DMUB_VBIOS>================================================================= 470 //============================================================================== 471 //< DMUB_GPINT>================================================================= 472 //============================================================================== 473 474 /** 475 * The shifts and masks below may alternatively be used to format and read 476 * the command register bits. 477 */ 478 479 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 480 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 481 482 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 483 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 484 485 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 486 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 487 488 /** 489 * Command responses. 490 */ 491 492 /** 493 * Return response for DMUB_GPINT__STOP_FW command. 494 */ 495 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 496 497 /** 498 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 499 */ 500 union dmub_gpint_data_register { 501 struct { 502 uint32_t param : 16; /**< 16-bit parameter */ 503 uint32_t command_code : 12; /**< GPINT command */ 504 uint32_t status : 4; /**< Command status bit */ 505 } bits; /**< GPINT bit access */ 506 uint32_t all; /**< GPINT 32-bit access */ 507 }; 508 509 /* 510 * enum dmub_gpint_command - GPINT command to DMCUB FW 511 * 512 * Command IDs should be treated as stable ABI. 513 * Do not reuse or modify IDs. 514 */ 515 enum dmub_gpint_command { 516 /** 517 * Invalid command, ignored. 518 */ 519 DMUB_GPINT__INVALID_COMMAND = 0, 520 /** 521 * DESC: Queries the firmware version. 522 * RETURN: Firmware version. 523 */ 524 DMUB_GPINT__GET_FW_VERSION = 1, 525 /** 526 * DESC: Halts the firmware. 527 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 528 */ 529 DMUB_GPINT__STOP_FW = 2, 530 /** 531 * DESC: Get PSR state from FW. 532 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 533 */ 534 DMUB_GPINT__GET_PSR_STATE = 7, 535 /** 536 * DESC: Notifies DMCUB of the currently active streams. 537 * ARGS: Stream mask, 1 bit per active stream index. 538 */ 539 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 540 /** 541 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 542 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 543 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 544 * RETURN: PSR residency in milli-percent. 545 */ 546 DMUB_GPINT__PSR_RESIDENCY = 9, 547 548 /** 549 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 550 */ 551 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 552 }; 553 554 /** 555 * INBOX0 generic command definition 556 */ 557 union dmub_inbox0_cmd_common { 558 struct { 559 uint32_t command_code: 8; /**< INBOX0 command code */ 560 uint32_t param: 24; /**< 24-bit parameter */ 561 } bits; 562 uint32_t all; 563 }; 564 565 /** 566 * INBOX0 hw_lock command definition 567 */ 568 union dmub_inbox0_cmd_lock_hw { 569 struct { 570 uint32_t command_code: 8; 571 572 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 573 uint32_t hw_lock_client: 2; 574 575 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 576 uint32_t otg_inst: 3; 577 uint32_t opp_inst: 3; 578 uint32_t dig_inst: 3; 579 580 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 581 uint32_t lock_pipe: 1; 582 uint32_t lock_cursor: 1; 583 uint32_t lock_dig: 1; 584 uint32_t triple_buffer_lock: 1; 585 586 uint32_t lock: 1; /**< Lock */ 587 uint32_t should_release: 1; /**< Release */ 588 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 589 } bits; 590 uint32_t all; 591 }; 592 593 union dmub_inbox0_data_register { 594 union dmub_inbox0_cmd_common inbox0_cmd_common; 595 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 596 }; 597 598 enum dmub_inbox0_command { 599 /** 600 * DESC: Invalid command, ignored. 601 */ 602 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 603 /** 604 * DESC: Notification to acquire/release HW lock 605 * ARGS: 606 */ 607 DMUB_INBOX0_CMD__HW_LOCK = 1, 608 }; 609 //============================================================================== 610 //</DMUB_GPINT>================================================================= 611 //============================================================================== 612 //< DMUB_CMD>=================================================================== 613 //============================================================================== 614 615 /** 616 * Size in bytes of each DMUB command. 617 */ 618 #define DMUB_RB_CMD_SIZE 64 619 620 /** 621 * Maximum number of items in the DMUB ringbuffer. 622 */ 623 #define DMUB_RB_MAX_ENTRY 128 624 625 /** 626 * Ringbuffer size in bytes. 627 */ 628 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 629 630 /** 631 * REG_SET mask for reg offload. 632 */ 633 #define REG_SET_MASK 0xFFFF 634 635 /* 636 * enum dmub_cmd_type - DMUB inbox command. 637 * 638 * Command IDs should be treated as stable ABI. 639 * Do not reuse or modify IDs. 640 */ 641 enum dmub_cmd_type { 642 /** 643 * Invalid command. 644 */ 645 DMUB_CMD__NULL = 0, 646 /** 647 * Read modify write register sequence offload. 648 */ 649 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 650 /** 651 * Field update register sequence offload. 652 */ 653 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 654 /** 655 * Burst write sequence offload. 656 */ 657 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 658 /** 659 * Reg wait sequence offload. 660 */ 661 DMUB_CMD__REG_REG_WAIT = 4, 662 /** 663 * Workaround to avoid HUBP underflow during NV12 playback. 664 */ 665 DMUB_CMD__PLAT_54186_WA = 5, 666 /** 667 * Command type used to query FW feature caps. 668 */ 669 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 670 /** 671 * Command type used to get visual confirm color. 672 */ 673 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 674 /** 675 * Command type used for all PSR commands. 676 */ 677 DMUB_CMD__PSR = 64, 678 /** 679 * Command type used for all MALL commands. 680 */ 681 DMUB_CMD__MALL = 65, 682 /** 683 * Command type used for all ABM commands. 684 */ 685 DMUB_CMD__ABM = 66, 686 /** 687 * Command type used to update dirty rects in FW. 688 */ 689 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 690 /** 691 * Command type used to update cursor info in FW. 692 */ 693 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 694 /** 695 * Command type used for HW locking in FW. 696 */ 697 DMUB_CMD__HW_LOCK = 69, 698 /** 699 * Command type used to access DP AUX. 700 */ 701 DMUB_CMD__DP_AUX_ACCESS = 70, 702 /** 703 * Command type used for OUTBOX1 notification enable 704 */ 705 DMUB_CMD__OUTBOX1_ENABLE = 71, 706 707 /** 708 * Command type used for all idle optimization commands. 709 */ 710 DMUB_CMD__IDLE_OPT = 72, 711 /** 712 * Command type used for all clock manager commands. 713 */ 714 DMUB_CMD__CLK_MGR = 73, 715 /** 716 * Command type used for all panel control commands. 717 */ 718 DMUB_CMD__PANEL_CNTL = 74, 719 /** 720 * Command type used for <TODO:description> 721 */ 722 DMUB_CMD__CAB_FOR_SS = 75, 723 724 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 725 726 /** 727 * Command type used for interfacing with DPIA. 728 */ 729 DMUB_CMD__DPIA = 77, 730 /** 731 * Command type used for EDID CEA parsing 732 */ 733 DMUB_CMD__EDID_CEA = 79, 734 /** 735 * Command type used for getting usbc cable ID 736 */ 737 DMUB_CMD_GET_USBC_CABLE_ID = 81, 738 /** 739 * Command type used to query HPD state. 740 */ 741 DMUB_CMD__QUERY_HPD_STATE = 82, 742 /** 743 * Command type used for all VBIOS interface commands. 744 */ 745 746 /** 747 * Command type used for all SECURE_DISPLAY commands. 748 */ 749 DMUB_CMD__SECURE_DISPLAY = 85, 750 751 /** 752 * Command type used to set DPIA HPD interrupt state 753 */ 754 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 755 756 DMUB_CMD__VBIOS = 128, 757 }; 758 759 /** 760 * enum dmub_out_cmd_type - DMUB outbox commands. 761 */ 762 enum dmub_out_cmd_type { 763 /** 764 * Invalid outbox command, ignored. 765 */ 766 DMUB_OUT_CMD__NULL = 0, 767 /** 768 * Command type used for DP AUX Reply data notification 769 */ 770 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 771 /** 772 * Command type used for DP HPD event notification 773 */ 774 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 775 /** 776 * Command type used for SET_CONFIG Reply notification 777 */ 778 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 779 /** 780 * Command type used for USB4 DPIA notification 781 */ 782 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 783 }; 784 785 /* DMUB_CMD__DPIA command sub-types. */ 786 enum dmub_cmd_dpia_type { 787 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 788 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 789 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 790 }; 791 792 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 793 enum dmub_cmd_dpia_notification_type { 794 DPIA_NOTIFY__BW_ALLOCATION = 0, 795 }; 796 797 #pragma pack(push, 1) 798 799 /** 800 * struct dmub_cmd_header - Common command header fields. 801 */ 802 struct dmub_cmd_header { 803 unsigned int type : 8; /**< command type */ 804 unsigned int sub_type : 8; /**< command sub type */ 805 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 806 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 807 unsigned int reserved0 : 6; /**< reserved bits */ 808 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 809 unsigned int reserved1 : 2; /**< reserved bits */ 810 }; 811 812 /* 813 * struct dmub_cmd_read_modify_write_sequence - Read modify write 814 * 815 * 60 payload bytes can hold up to 5 sets of read modify writes, 816 * each take 3 dwords. 817 * 818 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 819 * 820 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 821 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 822 */ 823 struct dmub_cmd_read_modify_write_sequence { 824 uint32_t addr; /**< register address */ 825 uint32_t modify_mask; /**< modify mask */ 826 uint32_t modify_value; /**< modify value */ 827 }; 828 829 /** 830 * Maximum number of ops in read modify write sequence. 831 */ 832 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 833 834 /** 835 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 836 */ 837 struct dmub_rb_cmd_read_modify_write { 838 struct dmub_cmd_header header; /**< command header */ 839 /** 840 * Read modify write sequence. 841 */ 842 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 843 }; 844 845 /* 846 * Update a register with specified masks and values sequeunce 847 * 848 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 849 * 850 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 851 * 852 * 853 * USE CASE: 854 * 1. auto-increment register where additional read would update pointer and produce wrong result 855 * 2. toggle a bit without read in the middle 856 */ 857 858 struct dmub_cmd_reg_field_update_sequence { 859 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 860 uint32_t modify_value; /**< value to update with */ 861 }; 862 863 /** 864 * Maximum number of ops in field update sequence. 865 */ 866 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 867 868 /** 869 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 870 */ 871 struct dmub_rb_cmd_reg_field_update_sequence { 872 struct dmub_cmd_header header; /**< command header */ 873 uint32_t addr; /**< register address */ 874 /** 875 * Field update sequence. 876 */ 877 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 878 }; 879 880 881 /** 882 * Maximum number of burst write values. 883 */ 884 #define DMUB_BURST_WRITE_VALUES__MAX 14 885 886 /* 887 * struct dmub_rb_cmd_burst_write - Burst write 888 * 889 * support use case such as writing out LUTs. 890 * 891 * 60 payload bytes can hold up to 14 values to write to given address 892 * 893 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 894 */ 895 struct dmub_rb_cmd_burst_write { 896 struct dmub_cmd_header header; /**< command header */ 897 uint32_t addr; /**< register start address */ 898 /** 899 * Burst write register values. 900 */ 901 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 902 }; 903 904 /** 905 * struct dmub_rb_cmd_common - Common command header 906 */ 907 struct dmub_rb_cmd_common { 908 struct dmub_cmd_header header; /**< command header */ 909 /** 910 * Padding to RB_CMD_SIZE 911 */ 912 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 913 }; 914 915 /** 916 * struct dmub_cmd_reg_wait_data - Register wait data 917 */ 918 struct dmub_cmd_reg_wait_data { 919 uint32_t addr; /**< Register address */ 920 uint32_t mask; /**< Mask for register bits */ 921 uint32_t condition_field_value; /**< Value to wait for */ 922 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 923 }; 924 925 /** 926 * struct dmub_rb_cmd_reg_wait - Register wait command 927 */ 928 struct dmub_rb_cmd_reg_wait { 929 struct dmub_cmd_header header; /**< Command header */ 930 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 931 }; 932 933 /** 934 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 935 * 936 * Reprograms surface parameters to avoid underflow. 937 */ 938 struct dmub_cmd_PLAT_54186_wa { 939 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 940 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 941 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 942 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 943 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 944 struct { 945 uint8_t hubp_inst : 4; /**< HUBP instance */ 946 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 947 uint8_t immediate :1; /**< Immediate flip */ 948 uint8_t vmid : 4; /**< VMID */ 949 uint8_t grph_stereo : 1; /**< 1 if stereo */ 950 uint32_t reserved : 21; /**< Reserved */ 951 } flip_params; /**< Pageflip parameters */ 952 uint32_t reserved[9]; /**< Reserved bits */ 953 }; 954 955 /** 956 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 957 */ 958 struct dmub_rb_cmd_PLAT_54186_wa { 959 struct dmub_cmd_header header; /**< Command header */ 960 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 961 }; 962 963 /** 964 * struct dmub_rb_cmd_mall - MALL command data. 965 */ 966 struct dmub_rb_cmd_mall { 967 struct dmub_cmd_header header; /**< Common command header */ 968 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 969 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 970 uint32_t tmr_delay; /**< Timer delay */ 971 uint32_t tmr_scale; /**< Timer scale */ 972 uint16_t cursor_width; /**< Cursor width in pixels */ 973 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 974 uint16_t cursor_height; /**< Cursor height in pixels */ 975 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 976 uint8_t debug_bits; /**< Debug bits */ 977 978 uint8_t reserved1; /**< Reserved bits */ 979 uint8_t reserved2; /**< Reserved bits */ 980 }; 981 982 /** 983 * enum dmub_cmd_cab_type - TODO: 984 */ 985 enum dmub_cmd_cab_type { 986 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 987 DMUB_CMD__CAB_NO_DCN_REQ = 1, 988 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 989 }; 990 991 /** 992 * struct dmub_rb_cmd_cab_for_ss - TODO: 993 */ 994 struct dmub_rb_cmd_cab_for_ss { 995 struct dmub_cmd_header header; 996 uint8_t cab_alloc_ways; /* total number of ways */ 997 uint8_t debug_bits; /* debug bits */ 998 }; 999 1000 enum mclk_switch_mode { 1001 NONE = 0, 1002 FPO = 1, 1003 SUBVP = 2, 1004 VBLANK = 3, 1005 }; 1006 1007 /* Per pipe struct which stores the MCLK switch mode 1008 * data to be sent to DMUB. 1009 * Named "v2" for now -- once FPO and SUBVP are fully merged 1010 * the type name can be updated 1011 */ 1012 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1013 union { 1014 struct { 1015 uint32_t pix_clk_100hz; 1016 uint16_t main_vblank_start; 1017 uint16_t main_vblank_end; 1018 uint16_t mall_region_lines; 1019 uint16_t prefetch_lines; 1020 uint16_t prefetch_to_mall_start_lines; 1021 uint16_t processing_delay_lines; 1022 uint16_t htotal; // required to calculate line time for multi-display cases 1023 uint16_t vtotal; 1024 uint8_t main_pipe_index; 1025 uint8_t phantom_pipe_index; 1026 /* Since the microschedule is calculated in terms of OTG lines, 1027 * include any scaling factors to make sure when we get accurate 1028 * conversion when programming MALL_START_LINE (which is in terms 1029 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1030 * is 1/2 (numerator = 1, denominator = 2). 1031 */ 1032 uint8_t scale_factor_numerator; 1033 uint8_t scale_factor_denominator; 1034 uint8_t is_drr; 1035 uint8_t main_split_pipe_index; 1036 uint8_t phantom_split_pipe_index; 1037 } subvp_data; 1038 1039 struct { 1040 uint32_t pix_clk_100hz; 1041 uint16_t vblank_start; 1042 uint16_t vblank_end; 1043 uint16_t vstartup_start; 1044 uint16_t vtotal; 1045 uint16_t htotal; 1046 uint8_t vblank_pipe_index; 1047 uint8_t padding[1]; 1048 struct { 1049 uint8_t drr_in_use; 1050 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1051 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1052 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1053 uint8_t use_ramping; // Use ramping or not 1054 uint8_t drr_vblank_start_margin; 1055 } drr_info; // DRR considered as part of SubVP + VBLANK case 1056 } vblank_data; 1057 } pipe_config; 1058 1059 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1060 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1061 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1062 */ 1063 uint8_t mode; // enum mclk_switch_mode 1064 }; 1065 1066 /** 1067 * Config data for Sub-VP and FPO 1068 * Named "v2" for now -- once FPO and SUBVP are fully merged 1069 * the type name can be updated 1070 */ 1071 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1072 uint16_t watermark_a_cache; 1073 uint8_t vertical_int_margin_us; 1074 uint8_t pstate_allow_width_us; 1075 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1076 }; 1077 1078 /** 1079 * DMUB rb command definition for Sub-VP and FPO 1080 * Named "v2" for now -- once FPO and SUBVP are fully merged 1081 * the type name can be updated 1082 */ 1083 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1084 struct dmub_cmd_header header; 1085 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1086 }; 1087 1088 /** 1089 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1090 */ 1091 enum dmub_cmd_idle_opt_type { 1092 /** 1093 * DCN hardware restore. 1094 */ 1095 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1096 1097 /** 1098 * DCN hardware save. 1099 */ 1100 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1101 }; 1102 1103 /** 1104 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1105 */ 1106 struct dmub_rb_cmd_idle_opt_dcn_restore { 1107 struct dmub_cmd_header header; /**< header */ 1108 }; 1109 1110 /** 1111 * struct dmub_clocks - Clock update notification. 1112 */ 1113 struct dmub_clocks { 1114 uint32_t dispclk_khz; /**< dispclk kHz */ 1115 uint32_t dppclk_khz; /**< dppclk kHz */ 1116 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1117 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1118 }; 1119 1120 /** 1121 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1122 */ 1123 enum dmub_cmd_clk_mgr_type { 1124 /** 1125 * Notify DMCUB of clock update. 1126 */ 1127 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1128 }; 1129 1130 /** 1131 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1132 */ 1133 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1134 struct dmub_cmd_header header; /**< header */ 1135 struct dmub_clocks clocks; /**< clock data */ 1136 }; 1137 1138 /** 1139 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1140 */ 1141 struct dmub_cmd_digx_encoder_control_data { 1142 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1143 }; 1144 1145 /** 1146 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1147 */ 1148 struct dmub_rb_cmd_digx_encoder_control { 1149 struct dmub_cmd_header header; /**< header */ 1150 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1151 }; 1152 1153 /** 1154 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1155 */ 1156 struct dmub_cmd_set_pixel_clock_data { 1157 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1158 }; 1159 1160 /** 1161 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1162 */ 1163 struct dmub_rb_cmd_set_pixel_clock { 1164 struct dmub_cmd_header header; /**< header */ 1165 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1166 }; 1167 1168 /** 1169 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1170 */ 1171 struct dmub_cmd_enable_disp_power_gating_data { 1172 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1173 }; 1174 1175 /** 1176 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1177 */ 1178 struct dmub_rb_cmd_enable_disp_power_gating { 1179 struct dmub_cmd_header header; /**< header */ 1180 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1181 }; 1182 1183 /** 1184 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1185 */ 1186 struct dmub_dig_transmitter_control_data_v1_7 { 1187 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1188 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1189 union { 1190 uint8_t digmode; /**< enum atom_encode_mode_def */ 1191 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1192 } mode_laneset; 1193 uint8_t lanenum; /**< Number of lanes */ 1194 union { 1195 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1196 } symclk_units; 1197 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1198 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1199 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1200 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1201 uint8_t reserved1; /**< For future use */ 1202 uint8_t reserved2[3]; /**< For future use */ 1203 uint32_t reserved3[11]; /**< For future use */ 1204 }; 1205 1206 /** 1207 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1208 */ 1209 union dmub_cmd_dig1_transmitter_control_data { 1210 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1211 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1212 }; 1213 1214 /** 1215 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1216 */ 1217 struct dmub_rb_cmd_dig1_transmitter_control { 1218 struct dmub_cmd_header header; /**< header */ 1219 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1220 }; 1221 1222 /** 1223 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1224 */ 1225 struct dmub_rb_cmd_domain_control_data { 1226 uint8_t inst : 6; /**< DOMAIN instance to control */ 1227 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1228 uint8_t reserved[3]; /**< Reserved for future use */ 1229 }; 1230 1231 /** 1232 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1233 */ 1234 struct dmub_rb_cmd_domain_control { 1235 struct dmub_cmd_header header; /**< header */ 1236 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1237 }; 1238 1239 /** 1240 * DPIA tunnel command parameters. 1241 */ 1242 struct dmub_cmd_dig_dpia_control_data { 1243 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1244 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1245 union { 1246 uint8_t digmode; /** enum atom_encode_mode_def */ 1247 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1248 } mode_laneset; 1249 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1250 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1251 uint8_t hpdsel; /** =0: HPD is not assigned */ 1252 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1253 uint8_t dpia_id; /** Index of DPIA */ 1254 uint8_t fec_rdy : 1; 1255 uint8_t reserved : 7; 1256 uint32_t reserved1; 1257 }; 1258 1259 /** 1260 * DMUB command for DPIA tunnel control. 1261 */ 1262 struct dmub_rb_cmd_dig1_dpia_control { 1263 struct dmub_cmd_header header; 1264 struct dmub_cmd_dig_dpia_control_data dpia_control; 1265 }; 1266 1267 /** 1268 * SET_CONFIG Command Payload 1269 */ 1270 struct set_config_cmd_payload { 1271 uint8_t msg_type; /* set config message type */ 1272 uint8_t msg_data; /* set config message data */ 1273 }; 1274 1275 /** 1276 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1277 */ 1278 struct dmub_cmd_set_config_control_data { 1279 struct set_config_cmd_payload cmd_pkt; 1280 uint8_t instance; /* DPIA instance */ 1281 uint8_t immed_status; /* Immediate status returned in case of error */ 1282 }; 1283 1284 /** 1285 * DMUB command structure for SET_CONFIG command. 1286 */ 1287 struct dmub_rb_cmd_set_config_access { 1288 struct dmub_cmd_header header; /* header */ 1289 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1290 }; 1291 1292 /** 1293 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1294 */ 1295 struct dmub_cmd_mst_alloc_slots_control_data { 1296 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1297 uint8_t instance; /* DPIA instance */ 1298 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1299 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1300 }; 1301 1302 /** 1303 * DMUB command structure for SET_ command. 1304 */ 1305 struct dmub_rb_cmd_set_mst_alloc_slots { 1306 struct dmub_cmd_header header; /* header */ 1307 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1308 }; 1309 1310 /** 1311 * DMUB command structure for DPIA HPD int enable control. 1312 */ 1313 struct dmub_rb_cmd_dpia_hpd_int_enable { 1314 struct dmub_cmd_header header; /* header */ 1315 uint32_t enable; /* dpia hpd interrupt enable */ 1316 }; 1317 1318 /** 1319 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1320 */ 1321 struct dmub_rb_cmd_dpphy_init { 1322 struct dmub_cmd_header header; /**< header */ 1323 uint8_t reserved[60]; /**< reserved bits */ 1324 }; 1325 1326 /** 1327 * enum dp_aux_request_action - DP AUX request command listing. 1328 * 1329 * 4 AUX request command bits are shifted to high nibble. 1330 */ 1331 enum dp_aux_request_action { 1332 /** I2C-over-AUX write request */ 1333 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1334 /** I2C-over-AUX read request */ 1335 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1336 /** I2C-over-AUX write status request */ 1337 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1338 /** I2C-over-AUX write request with MOT=1 */ 1339 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1340 /** I2C-over-AUX read request with MOT=1 */ 1341 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1342 /** I2C-over-AUX write status request with MOT=1 */ 1343 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1344 /** Native AUX write request */ 1345 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1346 /** Native AUX read request */ 1347 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1348 }; 1349 1350 /** 1351 * enum aux_return_code_type - DP AUX process return code listing. 1352 */ 1353 enum aux_return_code_type { 1354 /** AUX process succeeded */ 1355 AUX_RET_SUCCESS = 0, 1356 /** AUX process failed with unknown reason */ 1357 AUX_RET_ERROR_UNKNOWN, 1358 /** AUX process completed with invalid reply */ 1359 AUX_RET_ERROR_INVALID_REPLY, 1360 /** AUX process timed out */ 1361 AUX_RET_ERROR_TIMEOUT, 1362 /** HPD was low during AUX process */ 1363 AUX_RET_ERROR_HPD_DISCON, 1364 /** Failed to acquire AUX engine */ 1365 AUX_RET_ERROR_ENGINE_ACQUIRE, 1366 /** AUX request not supported */ 1367 AUX_RET_ERROR_INVALID_OPERATION, 1368 /** AUX process not available */ 1369 AUX_RET_ERROR_PROTOCOL_ERROR, 1370 }; 1371 1372 /** 1373 * enum aux_channel_type - DP AUX channel type listing. 1374 */ 1375 enum aux_channel_type { 1376 /** AUX thru Legacy DP AUX */ 1377 AUX_CHANNEL_LEGACY_DDC, 1378 /** AUX thru DPIA DP tunneling */ 1379 AUX_CHANNEL_DPIA 1380 }; 1381 1382 /** 1383 * struct aux_transaction_parameters - DP AUX request transaction data 1384 */ 1385 struct aux_transaction_parameters { 1386 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1387 uint8_t action; /**< enum dp_aux_request_action */ 1388 uint8_t length; /**< DP AUX request data length */ 1389 uint8_t reserved; /**< For future use */ 1390 uint32_t address; /**< DP AUX address */ 1391 uint8_t data[16]; /**< DP AUX write data */ 1392 }; 1393 1394 /** 1395 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1396 */ 1397 struct dmub_cmd_dp_aux_control_data { 1398 uint8_t instance; /**< AUX instance or DPIA instance */ 1399 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1400 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1401 uint8_t reserved0; /**< For future use */ 1402 uint16_t timeout; /**< timeout time in us */ 1403 uint16_t reserved1; /**< For future use */ 1404 enum aux_channel_type type; /**< enum aux_channel_type */ 1405 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1406 }; 1407 1408 /** 1409 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1410 */ 1411 struct dmub_rb_cmd_dp_aux_access { 1412 /** 1413 * Command header. 1414 */ 1415 struct dmub_cmd_header header; 1416 /** 1417 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1418 */ 1419 struct dmub_cmd_dp_aux_control_data aux_control; 1420 }; 1421 1422 /** 1423 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1424 */ 1425 struct dmub_rb_cmd_outbox1_enable { 1426 /** 1427 * Command header. 1428 */ 1429 struct dmub_cmd_header header; 1430 /** 1431 * enable: 0x0 -> disable outbox1 notification (default value) 1432 * 0x1 -> enable outbox1 notification 1433 */ 1434 uint32_t enable; 1435 }; 1436 1437 /* DP AUX Reply command - OutBox Cmd */ 1438 /** 1439 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1440 */ 1441 struct aux_reply_data { 1442 /** 1443 * Aux cmd 1444 */ 1445 uint8_t command; 1446 /** 1447 * Aux reply data length (max: 16 bytes) 1448 */ 1449 uint8_t length; 1450 /** 1451 * Alignment only 1452 */ 1453 uint8_t pad[2]; 1454 /** 1455 * Aux reply data 1456 */ 1457 uint8_t data[16]; 1458 }; 1459 1460 /** 1461 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1462 */ 1463 struct aux_reply_control_data { 1464 /** 1465 * Reserved for future use 1466 */ 1467 uint32_t handle; 1468 /** 1469 * Aux Instance 1470 */ 1471 uint8_t instance; 1472 /** 1473 * Aux transaction result: definition in enum aux_return_code_type 1474 */ 1475 uint8_t result; 1476 /** 1477 * Alignment only 1478 */ 1479 uint16_t pad; 1480 }; 1481 1482 /** 1483 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1484 */ 1485 struct dmub_rb_cmd_dp_aux_reply { 1486 /** 1487 * Command header. 1488 */ 1489 struct dmub_cmd_header header; 1490 /** 1491 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1492 */ 1493 struct aux_reply_control_data control; 1494 /** 1495 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1496 */ 1497 struct aux_reply_data reply_data; 1498 }; 1499 1500 /* DP HPD Notify command - OutBox Cmd */ 1501 /** 1502 * DP HPD Type 1503 */ 1504 enum dp_hpd_type { 1505 /** 1506 * Normal DP HPD 1507 */ 1508 DP_HPD = 0, 1509 /** 1510 * DP HPD short pulse 1511 */ 1512 DP_IRQ 1513 }; 1514 1515 /** 1516 * DP HPD Status 1517 */ 1518 enum dp_hpd_status { 1519 /** 1520 * DP_HPD status low 1521 */ 1522 DP_HPD_UNPLUG = 0, 1523 /** 1524 * DP_HPD status high 1525 */ 1526 DP_HPD_PLUG 1527 }; 1528 1529 /** 1530 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1531 */ 1532 struct dp_hpd_data { 1533 /** 1534 * DP HPD instance 1535 */ 1536 uint8_t instance; 1537 /** 1538 * HPD type 1539 */ 1540 uint8_t hpd_type; 1541 /** 1542 * HPD status: only for type: DP_HPD to indicate status 1543 */ 1544 uint8_t hpd_status; 1545 /** 1546 * Alignment only 1547 */ 1548 uint8_t pad; 1549 }; 1550 1551 /** 1552 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1553 */ 1554 struct dmub_rb_cmd_dp_hpd_notify { 1555 /** 1556 * Command header. 1557 */ 1558 struct dmub_cmd_header header; 1559 /** 1560 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1561 */ 1562 struct dp_hpd_data hpd_data; 1563 }; 1564 1565 /** 1566 * Definition of a SET_CONFIG reply from DPOA. 1567 */ 1568 enum set_config_status { 1569 SET_CONFIG_PENDING = 0, 1570 SET_CONFIG_ACK_RECEIVED, 1571 SET_CONFIG_RX_TIMEOUT, 1572 SET_CONFIG_UNKNOWN_ERROR, 1573 }; 1574 1575 /** 1576 * Definition of a set_config reply 1577 */ 1578 struct set_config_reply_control_data { 1579 uint8_t instance; /* DPIA Instance */ 1580 uint8_t status; /* Set Config reply */ 1581 uint16_t pad; /* Alignment */ 1582 }; 1583 1584 /** 1585 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1586 */ 1587 struct dmub_rb_cmd_dp_set_config_reply { 1588 struct dmub_cmd_header header; 1589 struct set_config_reply_control_data set_config_reply_control; 1590 }; 1591 1592 /** 1593 * Definition of a DPIA notification header 1594 */ 1595 struct dpia_notification_header { 1596 uint8_t instance; /**< DPIA Instance */ 1597 uint8_t reserved[3]; 1598 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1599 }; 1600 1601 /** 1602 * Definition of the common data struct of DPIA notification 1603 */ 1604 struct dpia_notification_common { 1605 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1606 - sizeof(struct dpia_notification_header)]; 1607 }; 1608 1609 /** 1610 * Definition of a DPIA notification data 1611 */ 1612 struct dpia_bw_allocation_notify_data { 1613 union { 1614 struct { 1615 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1616 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1617 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1618 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1619 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1620 uint16_t reserved: 11; /**< Reserved */ 1621 } bits; 1622 1623 uint16_t flags; 1624 }; 1625 1626 uint8_t cm_id; /**< CM ID */ 1627 uint8_t group_id; /**< Group ID */ 1628 uint8_t granularity; /**< BW Allocation Granularity */ 1629 uint8_t estimated_bw; /**< Estimated_BW */ 1630 uint8_t allocated_bw; /**< Allocated_BW */ 1631 uint8_t reserved; 1632 }; 1633 1634 /** 1635 * union dpia_notify_data_type - DPIA Notification in Outbox command 1636 */ 1637 union dpia_notification_data { 1638 /** 1639 * DPIA Notification for common data struct 1640 */ 1641 struct dpia_notification_common common_data; 1642 1643 /** 1644 * DPIA Notification for DP BW Allocation support 1645 */ 1646 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1647 }; 1648 1649 /** 1650 * Definition of a DPIA notification payload 1651 */ 1652 struct dpia_notification_payload { 1653 struct dpia_notification_header header; 1654 union dpia_notification_data data; /**< DPIA notification payload data */ 1655 }; 1656 1657 /** 1658 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1659 */ 1660 struct dmub_rb_cmd_dpia_notification { 1661 struct dmub_cmd_header header; /**< DPIA notification header */ 1662 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1663 }; 1664 1665 /** 1666 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1667 */ 1668 struct dmub_cmd_hpd_state_query_data { 1669 uint8_t instance; /**< HPD instance or DPIA instance */ 1670 uint8_t result; /**< For returning HPD state */ 1671 uint16_t pad; /** < Alignment */ 1672 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1673 enum aux_return_code_type status; /**< for returning the status of command */ 1674 }; 1675 1676 /** 1677 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1678 */ 1679 struct dmub_rb_cmd_query_hpd_state { 1680 /** 1681 * Command header. 1682 */ 1683 struct dmub_cmd_header header; 1684 /** 1685 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1686 */ 1687 struct dmub_cmd_hpd_state_query_data data; 1688 }; 1689 1690 /* 1691 * Command IDs should be treated as stable ABI. 1692 * Do not reuse or modify IDs. 1693 */ 1694 1695 /** 1696 * PSR command sub-types. 1697 */ 1698 enum dmub_cmd_psr_type { 1699 /** 1700 * Set PSR version support. 1701 */ 1702 DMUB_CMD__PSR_SET_VERSION = 0, 1703 /** 1704 * Copy driver-calculated parameters to PSR state. 1705 */ 1706 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1707 /** 1708 * Enable PSR. 1709 */ 1710 DMUB_CMD__PSR_ENABLE = 2, 1711 1712 /** 1713 * Disable PSR. 1714 */ 1715 DMUB_CMD__PSR_DISABLE = 3, 1716 1717 /** 1718 * Set PSR level. 1719 * PSR level is a 16-bit value dicated by driver that 1720 * will enable/disable different functionality. 1721 */ 1722 DMUB_CMD__PSR_SET_LEVEL = 4, 1723 1724 /** 1725 * Forces PSR enabled until an explicit PSR disable call. 1726 */ 1727 DMUB_CMD__PSR_FORCE_STATIC = 5, 1728 /** 1729 * Set vtotal in psr active for FreeSync PSR. 1730 */ 1731 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1732 /** 1733 * Set PSR power option 1734 */ 1735 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1736 }; 1737 1738 enum dmub_cmd_fams_type { 1739 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1740 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1741 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1742 /** 1743 * For SubVP set manual trigger in FW because it 1744 * triggers DRR_UPDATE_PENDING which SubVP relies 1745 * on (for any SubVP cases that use a DRR display) 1746 */ 1747 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1748 }; 1749 1750 /** 1751 * PSR versions. 1752 */ 1753 enum psr_version { 1754 /** 1755 * PSR version 1. 1756 */ 1757 PSR_VERSION_1 = 0, 1758 /** 1759 * Freesync PSR SU. 1760 */ 1761 PSR_VERSION_SU_1 = 1, 1762 /** 1763 * PSR not supported. 1764 */ 1765 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1766 }; 1767 1768 /** 1769 * enum dmub_cmd_mall_type - MALL commands 1770 */ 1771 enum dmub_cmd_mall_type { 1772 /** 1773 * Allows display refresh from MALL. 1774 */ 1775 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1776 /** 1777 * Disallows display refresh from MALL. 1778 */ 1779 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1780 /** 1781 * Cursor copy for MALL. 1782 */ 1783 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1784 /** 1785 * Controls DF requests. 1786 */ 1787 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1788 }; 1789 1790 /** 1791 * PHY Link rate for DP. 1792 */ 1793 enum phy_link_rate { 1794 /** 1795 * not supported. 1796 */ 1797 PHY_RATE_UNKNOWN = 0, 1798 /** 1799 * Rate_1 (RBR) - 1.62 Gbps/Lane 1800 */ 1801 PHY_RATE_162 = 1, 1802 /** 1803 * Rate_2 - 2.16 Gbps/Lane 1804 */ 1805 PHY_RATE_216 = 2, 1806 /** 1807 * Rate_3 - 2.43 Gbps/Lane 1808 */ 1809 PHY_RATE_243 = 3, 1810 /** 1811 * Rate_4 (HBR) - 2.70 Gbps/Lane 1812 */ 1813 PHY_RATE_270 = 4, 1814 /** 1815 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1816 */ 1817 PHY_RATE_324 = 5, 1818 /** 1819 * Rate_6 - 4.32 Gbps/Lane 1820 */ 1821 PHY_RATE_432 = 6, 1822 /** 1823 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1824 */ 1825 PHY_RATE_540 = 7, 1826 /** 1827 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1828 */ 1829 PHY_RATE_810 = 8, 1830 /** 1831 * UHBR10 - 10.0 Gbps/Lane 1832 */ 1833 PHY_RATE_1000 = 9, 1834 /** 1835 * UHBR13.5 - 13.5 Gbps/Lane 1836 */ 1837 PHY_RATE_1350 = 10, 1838 /** 1839 * UHBR10 - 20.0 Gbps/Lane 1840 */ 1841 PHY_RATE_2000 = 11, 1842 }; 1843 1844 /** 1845 * enum dmub_phy_fsm_state - PHY FSM states. 1846 * PHY FSM state to transit to during PSR enable/disable. 1847 */ 1848 enum dmub_phy_fsm_state { 1849 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1850 DMUB_PHY_FSM_RESET, 1851 DMUB_PHY_FSM_RESET_RELEASED, 1852 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1853 DMUB_PHY_FSM_INITIALIZED, 1854 DMUB_PHY_FSM_CALIBRATED, 1855 DMUB_PHY_FSM_CALIBRATED_LP, 1856 DMUB_PHY_FSM_CALIBRATED_PG, 1857 DMUB_PHY_FSM_POWER_DOWN, 1858 DMUB_PHY_FSM_PLL_EN, 1859 DMUB_PHY_FSM_TX_EN, 1860 DMUB_PHY_FSM_FAST_LP, 1861 }; 1862 1863 /** 1864 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1865 */ 1866 struct dmub_cmd_psr_copy_settings_data { 1867 /** 1868 * Flags that can be set by driver to change some PSR behaviour. 1869 */ 1870 union dmub_psr_debug_flags debug; 1871 /** 1872 * 16-bit value dicated by driver that will enable/disable different functionality. 1873 */ 1874 uint16_t psr_level; 1875 /** 1876 * DPP HW instance. 1877 */ 1878 uint8_t dpp_inst; 1879 /** 1880 * MPCC HW instance. 1881 * Not used in dmub fw, 1882 * dmub fw will get active opp by reading odm registers. 1883 */ 1884 uint8_t mpcc_inst; 1885 /** 1886 * OPP HW instance. 1887 * Not used in dmub fw, 1888 * dmub fw will get active opp by reading odm registers. 1889 */ 1890 uint8_t opp_inst; 1891 /** 1892 * OTG HW instance. 1893 */ 1894 uint8_t otg_inst; 1895 /** 1896 * DIG FE HW instance. 1897 */ 1898 uint8_t digfe_inst; 1899 /** 1900 * DIG BE HW instance. 1901 */ 1902 uint8_t digbe_inst; 1903 /** 1904 * DP PHY HW instance. 1905 */ 1906 uint8_t dpphy_inst; 1907 /** 1908 * AUX HW instance. 1909 */ 1910 uint8_t aux_inst; 1911 /** 1912 * Determines if SMU optimzations are enabled/disabled. 1913 */ 1914 uint8_t smu_optimizations_en; 1915 /** 1916 * Unused. 1917 * TODO: Remove. 1918 */ 1919 uint8_t frame_delay; 1920 /** 1921 * If RFB setup time is greater than the total VBLANK time, 1922 * it is not possible for the sink to capture the video frame 1923 * in the same frame the SDP is sent. In this case, 1924 * the frame capture indication bit should be set and an extra 1925 * static frame should be transmitted to the sink. 1926 */ 1927 uint8_t frame_cap_ind; 1928 /** 1929 * Granularity of Y offset supported by sink. 1930 */ 1931 uint8_t su_y_granularity; 1932 /** 1933 * Indicates whether sink should start capturing 1934 * immediately following active scan line, 1935 * or starting with the 2nd active scan line. 1936 */ 1937 uint8_t line_capture_indication; 1938 /** 1939 * Multi-display optimizations are implemented on certain ASICs. 1940 */ 1941 uint8_t multi_disp_optimizations_en; 1942 /** 1943 * The last possible line SDP may be transmitted without violating 1944 * the RFB setup time or entering the active video frame. 1945 */ 1946 uint16_t init_sdp_deadline; 1947 /** 1948 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1949 */ 1950 uint8_t rate_control_caps ; 1951 /* 1952 * Force PSRSU always doing full frame update 1953 */ 1954 uint8_t force_ffu_mode; 1955 /** 1956 * Length of each horizontal line in us. 1957 */ 1958 uint32_t line_time_in_us; 1959 /** 1960 * FEC enable status in driver 1961 */ 1962 uint8_t fec_enable_status; 1963 /** 1964 * FEC re-enable delay when PSR exit. 1965 * unit is 100us, range form 0~255(0xFF). 1966 */ 1967 uint8_t fec_enable_delay_in100us; 1968 /** 1969 * PSR control version. 1970 */ 1971 uint8_t cmd_version; 1972 /** 1973 * Panel Instance. 1974 * Panel isntance to identify which psr_state to use 1975 * Currently the support is only for 0 or 1 1976 */ 1977 uint8_t panel_inst; 1978 /* 1979 * DSC enable status in driver 1980 */ 1981 uint8_t dsc_enable_status; 1982 /* 1983 * Use FSM state for PSR power up/down 1984 */ 1985 uint8_t use_phy_fsm; 1986 /** 1987 * frame delay for frame re-lock 1988 */ 1989 uint8_t relock_delay_frame_cnt; 1990 /** 1991 * Explicit padding to 2 byte boundary. 1992 */ 1993 uint8_t pad3; 1994 /** 1995 * DSC Slice height. 1996 */ 1997 uint16_t dsc_slice_height; 1998 /** 1999 * Explicit padding to 4 byte boundary. 2000 */ 2001 uint16_t pad; 2002 }; 2003 2004 /** 2005 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2006 */ 2007 struct dmub_rb_cmd_psr_copy_settings { 2008 /** 2009 * Command header. 2010 */ 2011 struct dmub_cmd_header header; 2012 /** 2013 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2014 */ 2015 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2016 }; 2017 2018 /** 2019 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2020 */ 2021 struct dmub_cmd_psr_set_level_data { 2022 /** 2023 * 16-bit value dicated by driver that will enable/disable different functionality. 2024 */ 2025 uint16_t psr_level; 2026 /** 2027 * PSR control version. 2028 */ 2029 uint8_t cmd_version; 2030 /** 2031 * Panel Instance. 2032 * Panel isntance to identify which psr_state to use 2033 * Currently the support is only for 0 or 1 2034 */ 2035 uint8_t panel_inst; 2036 }; 2037 2038 /** 2039 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2040 */ 2041 struct dmub_rb_cmd_psr_set_level { 2042 /** 2043 * Command header. 2044 */ 2045 struct dmub_cmd_header header; 2046 /** 2047 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2048 */ 2049 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2050 }; 2051 2052 struct dmub_rb_cmd_psr_enable_data { 2053 /** 2054 * PSR control version. 2055 */ 2056 uint8_t cmd_version; 2057 /** 2058 * Panel Instance. 2059 * Panel isntance to identify which psr_state to use 2060 * Currently the support is only for 0 or 1 2061 */ 2062 uint8_t panel_inst; 2063 /** 2064 * Phy state to enter. 2065 * Values to use are defined in dmub_phy_fsm_state 2066 */ 2067 uint8_t phy_fsm_state; 2068 /** 2069 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2070 * Set this using enum phy_link_rate. 2071 * This does not support HDMI/DP2 for now. 2072 */ 2073 uint8_t phy_rate; 2074 }; 2075 2076 /** 2077 * Definition of a DMUB_CMD__PSR_ENABLE command. 2078 * PSR enable/disable is controlled using the sub_type. 2079 */ 2080 struct dmub_rb_cmd_psr_enable { 2081 /** 2082 * Command header. 2083 */ 2084 struct dmub_cmd_header header; 2085 2086 struct dmub_rb_cmd_psr_enable_data data; 2087 }; 2088 2089 /** 2090 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2091 */ 2092 struct dmub_cmd_psr_set_version_data { 2093 /** 2094 * PSR version that FW should implement. 2095 */ 2096 enum psr_version version; 2097 /** 2098 * PSR control version. 2099 */ 2100 uint8_t cmd_version; 2101 /** 2102 * Panel Instance. 2103 * Panel isntance to identify which psr_state to use 2104 * Currently the support is only for 0 or 1 2105 */ 2106 uint8_t panel_inst; 2107 /** 2108 * Explicit padding to 4 byte boundary. 2109 */ 2110 uint8_t pad[2]; 2111 }; 2112 2113 /** 2114 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2115 */ 2116 struct dmub_rb_cmd_psr_set_version { 2117 /** 2118 * Command header. 2119 */ 2120 struct dmub_cmd_header header; 2121 /** 2122 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2123 */ 2124 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2125 }; 2126 2127 struct dmub_cmd_psr_force_static_data { 2128 /** 2129 * PSR control version. 2130 */ 2131 uint8_t cmd_version; 2132 /** 2133 * Panel Instance. 2134 * Panel isntance to identify which psr_state to use 2135 * Currently the support is only for 0 or 1 2136 */ 2137 uint8_t panel_inst; 2138 /** 2139 * Explicit padding to 4 byte boundary. 2140 */ 2141 uint8_t pad[2]; 2142 }; 2143 2144 /** 2145 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2146 */ 2147 struct dmub_rb_cmd_psr_force_static { 2148 /** 2149 * Command header. 2150 */ 2151 struct dmub_cmd_header header; 2152 /** 2153 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2154 */ 2155 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2156 }; 2157 2158 /** 2159 * PSR SU debug flags. 2160 */ 2161 union dmub_psr_su_debug_flags { 2162 /** 2163 * PSR SU debug flags. 2164 */ 2165 struct { 2166 /** 2167 * Update dirty rect in SW only. 2168 */ 2169 uint8_t update_dirty_rect_only : 1; 2170 /** 2171 * Reset the cursor/plane state before processing the call. 2172 */ 2173 uint8_t reset_state : 1; 2174 } bitfields; 2175 2176 /** 2177 * Union for debug flags. 2178 */ 2179 uint32_t u32All; 2180 }; 2181 2182 /** 2183 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2184 * This triggers a selective update for PSR SU. 2185 */ 2186 struct dmub_cmd_update_dirty_rect_data { 2187 /** 2188 * Dirty rects from OS. 2189 */ 2190 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2191 /** 2192 * PSR SU debug flags. 2193 */ 2194 union dmub_psr_su_debug_flags debug_flags; 2195 /** 2196 * OTG HW instance. 2197 */ 2198 uint8_t pipe_idx; 2199 /** 2200 * Number of dirty rects. 2201 */ 2202 uint8_t dirty_rect_count; 2203 /** 2204 * PSR control version. 2205 */ 2206 uint8_t cmd_version; 2207 /** 2208 * Panel Instance. 2209 * Panel isntance to identify which psr_state to use 2210 * Currently the support is only for 0 or 1 2211 */ 2212 uint8_t panel_inst; 2213 }; 2214 2215 /** 2216 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2217 */ 2218 struct dmub_rb_cmd_update_dirty_rect { 2219 /** 2220 * Command header. 2221 */ 2222 struct dmub_cmd_header header; 2223 /** 2224 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2225 */ 2226 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2227 }; 2228 2229 /** 2230 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2231 */ 2232 union dmub_reg_cursor_control_cfg { 2233 struct { 2234 uint32_t cur_enable: 1; 2235 uint32_t reser0: 3; 2236 uint32_t cur_2x_magnify: 1; 2237 uint32_t reser1: 3; 2238 uint32_t mode: 3; 2239 uint32_t reser2: 5; 2240 uint32_t pitch: 2; 2241 uint32_t reser3: 6; 2242 uint32_t line_per_chunk: 5; 2243 uint32_t reser4: 3; 2244 } bits; 2245 uint32_t raw; 2246 }; 2247 struct dmub_cursor_position_cache_hubp { 2248 union dmub_reg_cursor_control_cfg cur_ctl; 2249 union dmub_reg_position_cfg { 2250 struct { 2251 uint32_t cur_x_pos: 16; 2252 uint32_t cur_y_pos: 16; 2253 } bits; 2254 uint32_t raw; 2255 } position; 2256 union dmub_reg_hot_spot_cfg { 2257 struct { 2258 uint32_t hot_x: 16; 2259 uint32_t hot_y: 16; 2260 } bits; 2261 uint32_t raw; 2262 } hot_spot; 2263 union dmub_reg_dst_offset_cfg { 2264 struct { 2265 uint32_t dst_x_offset: 13; 2266 uint32_t reserved: 19; 2267 } bits; 2268 uint32_t raw; 2269 } dst_offset; 2270 }; 2271 2272 union dmub_reg_cur0_control_cfg { 2273 struct { 2274 uint32_t cur0_enable: 1; 2275 uint32_t expansion_mode: 1; 2276 uint32_t reser0: 1; 2277 uint32_t cur0_rom_en: 1; 2278 uint32_t mode: 3; 2279 uint32_t reserved: 25; 2280 } bits; 2281 uint32_t raw; 2282 }; 2283 struct dmub_cursor_position_cache_dpp { 2284 union dmub_reg_cur0_control_cfg cur0_ctl; 2285 }; 2286 struct dmub_cursor_position_cfg { 2287 struct dmub_cursor_position_cache_hubp pHubp; 2288 struct dmub_cursor_position_cache_dpp pDpp; 2289 uint8_t pipe_idx; 2290 /* 2291 * Padding is required. To be 4 Bytes Aligned. 2292 */ 2293 uint8_t padding[3]; 2294 }; 2295 2296 struct dmub_cursor_attribute_cache_hubp { 2297 uint32_t SURFACE_ADDR_HIGH; 2298 uint32_t SURFACE_ADDR; 2299 union dmub_reg_cursor_control_cfg cur_ctl; 2300 union dmub_reg_cursor_size_cfg { 2301 struct { 2302 uint32_t width: 16; 2303 uint32_t height: 16; 2304 } bits; 2305 uint32_t raw; 2306 } size; 2307 union dmub_reg_cursor_settings_cfg { 2308 struct { 2309 uint32_t dst_y_offset: 8; 2310 uint32_t chunk_hdl_adjust: 2; 2311 uint32_t reserved: 22; 2312 } bits; 2313 uint32_t raw; 2314 } settings; 2315 }; 2316 struct dmub_cursor_attribute_cache_dpp { 2317 union dmub_reg_cur0_control_cfg cur0_ctl; 2318 }; 2319 struct dmub_cursor_attributes_cfg { 2320 struct dmub_cursor_attribute_cache_hubp aHubp; 2321 struct dmub_cursor_attribute_cache_dpp aDpp; 2322 }; 2323 2324 struct dmub_cmd_update_cursor_payload0 { 2325 /** 2326 * Cursor dirty rects. 2327 */ 2328 struct dmub_rect cursor_rect; 2329 /** 2330 * PSR SU debug flags. 2331 */ 2332 union dmub_psr_su_debug_flags debug_flags; 2333 /** 2334 * Cursor enable/disable. 2335 */ 2336 uint8_t enable; 2337 /** 2338 * OTG HW instance. 2339 */ 2340 uint8_t pipe_idx; 2341 /** 2342 * PSR control version. 2343 */ 2344 uint8_t cmd_version; 2345 /** 2346 * Panel Instance. 2347 * Panel isntance to identify which psr_state to use 2348 * Currently the support is only for 0 or 1 2349 */ 2350 uint8_t panel_inst; 2351 /** 2352 * Cursor Position Register. 2353 * Registers contains Hubp & Dpp modules 2354 */ 2355 struct dmub_cursor_position_cfg position_cfg; 2356 }; 2357 2358 struct dmub_cmd_update_cursor_payload1 { 2359 struct dmub_cursor_attributes_cfg attribute_cfg; 2360 }; 2361 2362 union dmub_cmd_update_cursor_info_data { 2363 struct dmub_cmd_update_cursor_payload0 payload0; 2364 struct dmub_cmd_update_cursor_payload1 payload1; 2365 }; 2366 /** 2367 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2368 */ 2369 struct dmub_rb_cmd_update_cursor_info { 2370 /** 2371 * Command header. 2372 */ 2373 struct dmub_cmd_header header; 2374 /** 2375 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2376 */ 2377 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2378 }; 2379 2380 /** 2381 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2382 */ 2383 struct dmub_cmd_psr_set_vtotal_data { 2384 /** 2385 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2386 */ 2387 uint16_t psr_vtotal_idle; 2388 /** 2389 * PSR control version. 2390 */ 2391 uint8_t cmd_version; 2392 /** 2393 * Panel Instance. 2394 * Panel isntance to identify which psr_state to use 2395 * Currently the support is only for 0 or 1 2396 */ 2397 uint8_t panel_inst; 2398 /* 2399 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2400 */ 2401 uint16_t psr_vtotal_su; 2402 /** 2403 * Explicit padding to 4 byte boundary. 2404 */ 2405 uint8_t pad2[2]; 2406 }; 2407 2408 /** 2409 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2410 */ 2411 struct dmub_rb_cmd_psr_set_vtotal { 2412 /** 2413 * Command header. 2414 */ 2415 struct dmub_cmd_header header; 2416 /** 2417 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2418 */ 2419 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2420 }; 2421 2422 /** 2423 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2424 */ 2425 struct dmub_cmd_psr_set_power_opt_data { 2426 /** 2427 * PSR control version. 2428 */ 2429 uint8_t cmd_version; 2430 /** 2431 * Panel Instance. 2432 * Panel isntance to identify which psr_state to use 2433 * Currently the support is only for 0 or 1 2434 */ 2435 uint8_t panel_inst; 2436 /** 2437 * Explicit padding to 4 byte boundary. 2438 */ 2439 uint8_t pad[2]; 2440 /** 2441 * PSR power option 2442 */ 2443 uint32_t power_opt; 2444 }; 2445 2446 /** 2447 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2448 */ 2449 struct dmub_rb_cmd_psr_set_power_opt { 2450 /** 2451 * Command header. 2452 */ 2453 struct dmub_cmd_header header; 2454 /** 2455 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2456 */ 2457 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2458 }; 2459 2460 /** 2461 * Set of HW components that can be locked. 2462 * 2463 * Note: If updating with more HW components, fields 2464 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2465 */ 2466 union dmub_hw_lock_flags { 2467 /** 2468 * Set of HW components that can be locked. 2469 */ 2470 struct { 2471 /** 2472 * Lock/unlock OTG master update lock. 2473 */ 2474 uint8_t lock_pipe : 1; 2475 /** 2476 * Lock/unlock cursor. 2477 */ 2478 uint8_t lock_cursor : 1; 2479 /** 2480 * Lock/unlock global update lock. 2481 */ 2482 uint8_t lock_dig : 1; 2483 /** 2484 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2485 */ 2486 uint8_t triple_buffer_lock : 1; 2487 } bits; 2488 2489 /** 2490 * Union for HW Lock flags. 2491 */ 2492 uint8_t u8All; 2493 }; 2494 2495 /** 2496 * Instances of HW to be locked. 2497 * 2498 * Note: If updating with more HW components, fields 2499 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2500 */ 2501 struct dmub_hw_lock_inst_flags { 2502 /** 2503 * OTG HW instance for OTG master update lock. 2504 */ 2505 uint8_t otg_inst; 2506 /** 2507 * OPP instance for cursor lock. 2508 */ 2509 uint8_t opp_inst; 2510 /** 2511 * OTG HW instance for global update lock. 2512 * TODO: Remove, and re-use otg_inst. 2513 */ 2514 uint8_t dig_inst; 2515 /** 2516 * Explicit pad to 4 byte boundary. 2517 */ 2518 uint8_t pad; 2519 }; 2520 2521 /** 2522 * Clients that can acquire the HW Lock Manager. 2523 * 2524 * Note: If updating with more clients, fields in 2525 * dmub_inbox0_cmd_lock_hw must be updated to match. 2526 */ 2527 enum hw_lock_client { 2528 /** 2529 * Driver is the client of HW Lock Manager. 2530 */ 2531 HW_LOCK_CLIENT_DRIVER = 0, 2532 /** 2533 * PSR SU is the client of HW Lock Manager. 2534 */ 2535 HW_LOCK_CLIENT_PSR_SU = 1, 2536 /** 2537 * Invalid client. 2538 */ 2539 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2540 }; 2541 2542 /** 2543 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2544 */ 2545 struct dmub_cmd_lock_hw_data { 2546 /** 2547 * Specifies the client accessing HW Lock Manager. 2548 */ 2549 enum hw_lock_client client; 2550 /** 2551 * HW instances to be locked. 2552 */ 2553 struct dmub_hw_lock_inst_flags inst_flags; 2554 /** 2555 * Which components to be locked. 2556 */ 2557 union dmub_hw_lock_flags hw_locks; 2558 /** 2559 * Specifies lock/unlock. 2560 */ 2561 uint8_t lock; 2562 /** 2563 * HW can be unlocked separately from releasing the HW Lock Mgr. 2564 * This flag is set if the client wishes to release the object. 2565 */ 2566 uint8_t should_release; 2567 /** 2568 * Explicit padding to 4 byte boundary. 2569 */ 2570 uint8_t pad; 2571 }; 2572 2573 /** 2574 * Definition of a DMUB_CMD__HW_LOCK command. 2575 * Command is used by driver and FW. 2576 */ 2577 struct dmub_rb_cmd_lock_hw { 2578 /** 2579 * Command header. 2580 */ 2581 struct dmub_cmd_header header; 2582 /** 2583 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2584 */ 2585 struct dmub_cmd_lock_hw_data lock_hw_data; 2586 }; 2587 2588 /** 2589 * ABM command sub-types. 2590 */ 2591 enum dmub_cmd_abm_type { 2592 /** 2593 * Initialize parameters for ABM algorithm. 2594 * Data is passed through an indirect buffer. 2595 */ 2596 DMUB_CMD__ABM_INIT_CONFIG = 0, 2597 /** 2598 * Set OTG and panel HW instance. 2599 */ 2600 DMUB_CMD__ABM_SET_PIPE = 1, 2601 /** 2602 * Set user requested backklight level. 2603 */ 2604 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2605 /** 2606 * Set ABM operating/aggression level. 2607 */ 2608 DMUB_CMD__ABM_SET_LEVEL = 3, 2609 /** 2610 * Set ambient light level. 2611 */ 2612 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2613 /** 2614 * Enable/disable fractional duty cycle for backlight PWM. 2615 */ 2616 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2617 2618 /** 2619 * unregister vertical interrupt after steady state is reached 2620 */ 2621 DMUB_CMD__ABM_PAUSE = 6, 2622 }; 2623 2624 /** 2625 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2626 * Requirements: 2627 * - Padded explicitly to 32-bit boundary. 2628 * - Must ensure this structure matches the one on driver-side, 2629 * otherwise it won't be aligned. 2630 */ 2631 struct abm_config_table { 2632 /** 2633 * Gamma curve thresholds, used for crgb conversion. 2634 */ 2635 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2636 /** 2637 * Gamma curve offsets, used for crgb conversion. 2638 */ 2639 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2640 /** 2641 * Gamma curve slopes, used for crgb conversion. 2642 */ 2643 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2644 /** 2645 * Custom backlight curve thresholds. 2646 */ 2647 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2648 /** 2649 * Custom backlight curve offsets. 2650 */ 2651 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2652 /** 2653 * Ambient light thresholds. 2654 */ 2655 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2656 /** 2657 * Minimum programmable backlight. 2658 */ 2659 uint16_t min_abm_backlight; // 122B 2660 /** 2661 * Minimum reduction values. 2662 */ 2663 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2664 /** 2665 * Maximum reduction values. 2666 */ 2667 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2668 /** 2669 * Bright positive gain. 2670 */ 2671 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2672 /** 2673 * Dark negative gain. 2674 */ 2675 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2676 /** 2677 * Hybrid factor. 2678 */ 2679 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2680 /** 2681 * Contrast factor. 2682 */ 2683 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2684 /** 2685 * Deviation gain. 2686 */ 2687 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2688 /** 2689 * Minimum knee. 2690 */ 2691 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2692 /** 2693 * Maximum knee. 2694 */ 2695 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2696 /** 2697 * Unused. 2698 */ 2699 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2700 /** 2701 * Explicit padding to 4 byte boundary. 2702 */ 2703 uint8_t pad3[3]; // 229B 2704 /** 2705 * Backlight ramp reduction. 2706 */ 2707 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2708 /** 2709 * Backlight ramp start. 2710 */ 2711 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2712 }; 2713 2714 /** 2715 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2716 */ 2717 struct dmub_cmd_abm_set_pipe_data { 2718 /** 2719 * OTG HW instance. 2720 */ 2721 uint8_t otg_inst; 2722 2723 /** 2724 * Panel Control HW instance. 2725 */ 2726 uint8_t panel_inst; 2727 2728 /** 2729 * Controls how ABM will interpret a set pipe or set level command. 2730 */ 2731 uint8_t set_pipe_option; 2732 2733 /** 2734 * Unused. 2735 * TODO: Remove. 2736 */ 2737 uint8_t ramping_boundary; 2738 }; 2739 2740 /** 2741 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2742 */ 2743 struct dmub_rb_cmd_abm_set_pipe { 2744 /** 2745 * Command header. 2746 */ 2747 struct dmub_cmd_header header; 2748 2749 /** 2750 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2751 */ 2752 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2753 }; 2754 2755 /** 2756 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2757 */ 2758 struct dmub_cmd_abm_set_backlight_data { 2759 /** 2760 * Number of frames to ramp to backlight user level. 2761 */ 2762 uint32_t frame_ramp; 2763 2764 /** 2765 * Requested backlight level from user. 2766 */ 2767 uint32_t backlight_user_level; 2768 2769 /** 2770 * ABM control version. 2771 */ 2772 uint8_t version; 2773 2774 /** 2775 * Panel Control HW instance mask. 2776 * Bit 0 is Panel Control HW instance 0. 2777 * Bit 1 is Panel Control HW instance 1. 2778 */ 2779 uint8_t panel_mask; 2780 2781 /** 2782 * Explicit padding to 4 byte boundary. 2783 */ 2784 uint8_t pad[2]; 2785 }; 2786 2787 /** 2788 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2789 */ 2790 struct dmub_rb_cmd_abm_set_backlight { 2791 /** 2792 * Command header. 2793 */ 2794 struct dmub_cmd_header header; 2795 2796 /** 2797 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2798 */ 2799 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2800 }; 2801 2802 /** 2803 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2804 */ 2805 struct dmub_cmd_abm_set_level_data { 2806 /** 2807 * Set current ABM operating/aggression level. 2808 */ 2809 uint32_t level; 2810 2811 /** 2812 * ABM control version. 2813 */ 2814 uint8_t version; 2815 2816 /** 2817 * Panel Control HW instance mask. 2818 * Bit 0 is Panel Control HW instance 0. 2819 * Bit 1 is Panel Control HW instance 1. 2820 */ 2821 uint8_t panel_mask; 2822 2823 /** 2824 * Explicit padding to 4 byte boundary. 2825 */ 2826 uint8_t pad[2]; 2827 }; 2828 2829 /** 2830 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2831 */ 2832 struct dmub_rb_cmd_abm_set_level { 2833 /** 2834 * Command header. 2835 */ 2836 struct dmub_cmd_header header; 2837 2838 /** 2839 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2840 */ 2841 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2842 }; 2843 2844 /** 2845 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2846 */ 2847 struct dmub_cmd_abm_set_ambient_level_data { 2848 /** 2849 * Ambient light sensor reading from OS. 2850 */ 2851 uint32_t ambient_lux; 2852 2853 /** 2854 * ABM control version. 2855 */ 2856 uint8_t version; 2857 2858 /** 2859 * Panel Control HW instance mask. 2860 * Bit 0 is Panel Control HW instance 0. 2861 * Bit 1 is Panel Control HW instance 1. 2862 */ 2863 uint8_t panel_mask; 2864 2865 /** 2866 * Explicit padding to 4 byte boundary. 2867 */ 2868 uint8_t pad[2]; 2869 }; 2870 2871 /** 2872 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2873 */ 2874 struct dmub_rb_cmd_abm_set_ambient_level { 2875 /** 2876 * Command header. 2877 */ 2878 struct dmub_cmd_header header; 2879 2880 /** 2881 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2882 */ 2883 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2884 }; 2885 2886 /** 2887 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2888 */ 2889 struct dmub_cmd_abm_set_pwm_frac_data { 2890 /** 2891 * Enable/disable fractional duty cycle for backlight PWM. 2892 * TODO: Convert to uint8_t. 2893 */ 2894 uint32_t fractional_pwm; 2895 2896 /** 2897 * ABM control version. 2898 */ 2899 uint8_t version; 2900 2901 /** 2902 * Panel Control HW instance mask. 2903 * Bit 0 is Panel Control HW instance 0. 2904 * Bit 1 is Panel Control HW instance 1. 2905 */ 2906 uint8_t panel_mask; 2907 2908 /** 2909 * Explicit padding to 4 byte boundary. 2910 */ 2911 uint8_t pad[2]; 2912 }; 2913 2914 /** 2915 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2916 */ 2917 struct dmub_rb_cmd_abm_set_pwm_frac { 2918 /** 2919 * Command header. 2920 */ 2921 struct dmub_cmd_header header; 2922 2923 /** 2924 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2925 */ 2926 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2927 }; 2928 2929 /** 2930 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2931 */ 2932 struct dmub_cmd_abm_init_config_data { 2933 /** 2934 * Location of indirect buffer used to pass init data to ABM. 2935 */ 2936 union dmub_addr src; 2937 2938 /** 2939 * Indirect buffer length. 2940 */ 2941 uint16_t bytes; 2942 2943 2944 /** 2945 * ABM control version. 2946 */ 2947 uint8_t version; 2948 2949 /** 2950 * Panel Control HW instance mask. 2951 * Bit 0 is Panel Control HW instance 0. 2952 * Bit 1 is Panel Control HW instance 1. 2953 */ 2954 uint8_t panel_mask; 2955 2956 /** 2957 * Explicit padding to 4 byte boundary. 2958 */ 2959 uint8_t pad[2]; 2960 }; 2961 2962 /** 2963 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2964 */ 2965 struct dmub_rb_cmd_abm_init_config { 2966 /** 2967 * Command header. 2968 */ 2969 struct dmub_cmd_header header; 2970 2971 /** 2972 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2973 */ 2974 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2975 }; 2976 2977 /** 2978 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2979 */ 2980 2981 struct dmub_cmd_abm_pause_data { 2982 2983 /** 2984 * Panel Control HW instance mask. 2985 * Bit 0 is Panel Control HW instance 0. 2986 * Bit 1 is Panel Control HW instance 1. 2987 */ 2988 uint8_t panel_mask; 2989 2990 /** 2991 * OTG hw instance 2992 */ 2993 uint8_t otg_inst; 2994 2995 /** 2996 * Enable or disable ABM pause 2997 */ 2998 uint8_t enable; 2999 3000 /** 3001 * Explicit padding to 4 byte boundary. 3002 */ 3003 uint8_t pad[1]; 3004 }; 3005 3006 /** 3007 * Definition of a DMUB_CMD__ABM_PAUSE command. 3008 */ 3009 struct dmub_rb_cmd_abm_pause { 3010 /** 3011 * Command header. 3012 */ 3013 struct dmub_cmd_header header; 3014 3015 /** 3016 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3017 */ 3018 struct dmub_cmd_abm_pause_data abm_pause_data; 3019 }; 3020 3021 /** 3022 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3023 */ 3024 struct dmub_cmd_query_feature_caps_data { 3025 /** 3026 * DMUB feature capabilities. 3027 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3028 */ 3029 struct dmub_feature_caps feature_caps; 3030 }; 3031 3032 /** 3033 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3034 */ 3035 struct dmub_rb_cmd_query_feature_caps { 3036 /** 3037 * Command header. 3038 */ 3039 struct dmub_cmd_header header; 3040 /** 3041 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3042 */ 3043 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3044 }; 3045 3046 /** 3047 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3048 */ 3049 struct dmub_cmd_visual_confirm_color_data { 3050 /** 3051 * DMUB feature capabilities. 3052 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3053 */ 3054 struct dmub_visual_confirm_color visual_confirm_color; 3055 }; 3056 3057 /** 3058 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3059 */ 3060 struct dmub_rb_cmd_get_visual_confirm_color { 3061 /** 3062 * Command header. 3063 */ 3064 struct dmub_cmd_header header; 3065 /** 3066 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3067 */ 3068 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3069 }; 3070 3071 struct dmub_optc_state { 3072 uint32_t v_total_max; 3073 uint32_t v_total_min; 3074 uint32_t tg_inst; 3075 }; 3076 3077 struct dmub_rb_cmd_drr_update { 3078 struct dmub_cmd_header header; 3079 struct dmub_optc_state dmub_optc_state_req; 3080 }; 3081 3082 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3083 uint32_t pix_clk_100hz; 3084 uint8_t max_ramp_step; 3085 uint8_t pipes; 3086 uint8_t min_refresh_in_hz; 3087 uint8_t padding[1]; 3088 }; 3089 3090 struct dmub_cmd_fw_assisted_mclk_switch_config { 3091 uint8_t fams_enabled; 3092 uint8_t visual_confirm_enabled; 3093 uint8_t padding[2]; 3094 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 3095 }; 3096 3097 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3098 struct dmub_cmd_header header; 3099 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3100 }; 3101 3102 /** 3103 * enum dmub_cmd_panel_cntl_type - Panel control command. 3104 */ 3105 enum dmub_cmd_panel_cntl_type { 3106 /** 3107 * Initializes embedded panel hardware blocks. 3108 */ 3109 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3110 /** 3111 * Queries backlight info for the embedded panel. 3112 */ 3113 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3114 }; 3115 3116 /** 3117 * struct dmub_cmd_panel_cntl_data - Panel control data. 3118 */ 3119 struct dmub_cmd_panel_cntl_data { 3120 uint32_t inst; /**< panel instance */ 3121 uint32_t current_backlight; /* in/out */ 3122 uint32_t bl_pwm_cntl; /* in/out */ 3123 uint32_t bl_pwm_period_cntl; /* in/out */ 3124 uint32_t bl_pwm_ref_div1; /* in/out */ 3125 uint8_t is_backlight_on : 1; /* in/out */ 3126 uint8_t is_powered_on : 1; /* in/out */ 3127 uint8_t padding[3]; 3128 uint32_t bl_pwm_ref_div2; /* in/out */ 3129 uint8_t reserved[4]; 3130 }; 3131 3132 /** 3133 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3134 */ 3135 struct dmub_rb_cmd_panel_cntl { 3136 struct dmub_cmd_header header; /**< header */ 3137 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3138 }; 3139 3140 /** 3141 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3142 */ 3143 struct dmub_cmd_lvtma_control_data { 3144 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3145 uint8_t bypass_panel_control_wait; 3146 uint8_t reserved_0[2]; /**< For future use */ 3147 uint8_t panel_inst; /**< LVTMA control instance */ 3148 uint8_t reserved_1[3]; /**< For future use */ 3149 }; 3150 3151 /** 3152 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3153 */ 3154 struct dmub_rb_cmd_lvtma_control { 3155 /** 3156 * Command header. 3157 */ 3158 struct dmub_cmd_header header; 3159 /** 3160 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3161 */ 3162 struct dmub_cmd_lvtma_control_data data; 3163 }; 3164 3165 /** 3166 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3167 */ 3168 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3169 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3170 uint8_t is_usb; /**< is phy is usb */ 3171 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3172 uint8_t is_dp4; /**< is dp in 4 lane */ 3173 }; 3174 3175 /** 3176 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3177 */ 3178 struct dmub_rb_cmd_transmitter_query_dp_alt { 3179 struct dmub_cmd_header header; /**< header */ 3180 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3181 }; 3182 3183 /** 3184 * Maximum number of bytes a chunk sent to DMUB for parsing 3185 */ 3186 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3187 3188 /** 3189 * Represent a chunk of CEA blocks sent to DMUB for parsing 3190 */ 3191 struct dmub_cmd_send_edid_cea { 3192 uint16_t offset; /**< offset into the CEA block */ 3193 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3194 uint16_t cea_total_length; /**< total length of the CEA block */ 3195 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3196 uint8_t pad[3]; /**< padding and for future expansion */ 3197 }; 3198 3199 /** 3200 * Result of VSDB parsing from CEA block 3201 */ 3202 struct dmub_cmd_edid_cea_amd_vsdb { 3203 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3204 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3205 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3206 uint16_t min_frame_rate; /**< Maximum frame rate */ 3207 uint16_t max_frame_rate; /**< Minimum frame rate */ 3208 }; 3209 3210 /** 3211 * Result of sending a CEA chunk 3212 */ 3213 struct dmub_cmd_edid_cea_ack { 3214 uint16_t offset; /**< offset of the chunk into the CEA block */ 3215 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3216 uint8_t pad; /**< padding and for future expansion */ 3217 }; 3218 3219 /** 3220 * Specify whether the result is an ACK/NACK or the parsing has finished 3221 */ 3222 enum dmub_cmd_edid_cea_reply_type { 3223 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3224 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3225 }; 3226 3227 /** 3228 * Definition of a DMUB_CMD__EDID_CEA command. 3229 */ 3230 struct dmub_rb_cmd_edid_cea { 3231 struct dmub_cmd_header header; /**< Command header */ 3232 union dmub_cmd_edid_cea_data { 3233 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3234 struct dmub_cmd_edid_cea_output { /**< output with results */ 3235 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3236 union { 3237 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3238 struct dmub_cmd_edid_cea_ack ack; 3239 }; 3240 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3241 } data; /**< Command data */ 3242 3243 }; 3244 3245 /** 3246 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3247 */ 3248 struct dmub_cmd_cable_id_input { 3249 uint8_t phy_inst; /**< phy inst for cable id data */ 3250 }; 3251 3252 /** 3253 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3254 */ 3255 struct dmub_cmd_cable_id_output { 3256 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3257 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3258 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3259 uint8_t RESERVED :2; /**< reserved means not defined */ 3260 }; 3261 3262 /** 3263 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3264 */ 3265 struct dmub_rb_cmd_get_usbc_cable_id { 3266 struct dmub_cmd_header header; /**< Command header */ 3267 /** 3268 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3269 */ 3270 union dmub_cmd_cable_id_data { 3271 struct dmub_cmd_cable_id_input input; /**< Input */ 3272 struct dmub_cmd_cable_id_output output; /**< Output */ 3273 uint8_t output_raw; /**< Raw data output */ 3274 } data; 3275 }; 3276 3277 /** 3278 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3279 */ 3280 enum dmub_cmd_secure_display_type { 3281 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3282 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3283 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3284 }; 3285 3286 /** 3287 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3288 */ 3289 struct dmub_rb_cmd_secure_display { 3290 struct dmub_cmd_header header; 3291 /** 3292 * Data passed from driver to dmub firmware. 3293 */ 3294 struct dmub_cmd_roi_info { 3295 uint16_t x_start; 3296 uint16_t x_end; 3297 uint16_t y_start; 3298 uint16_t y_end; 3299 uint8_t otg_id; 3300 uint8_t phy_id; 3301 } roi_info; 3302 }; 3303 3304 /** 3305 * union dmub_rb_cmd - DMUB inbox command. 3306 */ 3307 union dmub_rb_cmd { 3308 /** 3309 * Elements shared with all commands. 3310 */ 3311 struct dmub_rb_cmd_common cmd_common; 3312 /** 3313 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3314 */ 3315 struct dmub_rb_cmd_read_modify_write read_modify_write; 3316 /** 3317 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3318 */ 3319 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3320 /** 3321 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3322 */ 3323 struct dmub_rb_cmd_burst_write burst_write; 3324 /** 3325 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3326 */ 3327 struct dmub_rb_cmd_reg_wait reg_wait; 3328 /** 3329 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3330 */ 3331 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3332 /** 3333 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3334 */ 3335 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3336 /** 3337 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3338 */ 3339 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3340 /** 3341 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3342 */ 3343 struct dmub_rb_cmd_dpphy_init dpphy_init; 3344 /** 3345 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3346 */ 3347 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3348 /** 3349 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3350 */ 3351 struct dmub_rb_cmd_domain_control domain_control; 3352 /** 3353 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3354 */ 3355 struct dmub_rb_cmd_psr_set_version psr_set_version; 3356 /** 3357 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3358 */ 3359 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3360 /** 3361 * Definition of a DMUB_CMD__PSR_ENABLE command. 3362 */ 3363 struct dmub_rb_cmd_psr_enable psr_enable; 3364 /** 3365 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3366 */ 3367 struct dmub_rb_cmd_psr_set_level psr_set_level; 3368 /** 3369 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3370 */ 3371 struct dmub_rb_cmd_psr_force_static psr_force_static; 3372 /** 3373 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3374 */ 3375 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3376 /** 3377 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3378 */ 3379 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3380 /** 3381 * Definition of a DMUB_CMD__HW_LOCK command. 3382 * Command is used by driver and FW. 3383 */ 3384 struct dmub_rb_cmd_lock_hw lock_hw; 3385 /** 3386 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3387 */ 3388 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3389 /** 3390 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3391 */ 3392 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3393 /** 3394 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3395 */ 3396 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3397 /** 3398 * Definition of a DMUB_CMD__MALL command. 3399 */ 3400 struct dmub_rb_cmd_mall mall; 3401 /** 3402 * Definition of a DMUB_CMD__CAB command. 3403 */ 3404 struct dmub_rb_cmd_cab_for_ss cab; 3405 3406 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3407 3408 /** 3409 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3410 */ 3411 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3412 3413 /** 3414 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3415 */ 3416 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3417 3418 /** 3419 * Definition of DMUB_CMD__PANEL_CNTL commands. 3420 */ 3421 struct dmub_rb_cmd_panel_cntl panel_cntl; 3422 /** 3423 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3424 */ 3425 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3426 3427 /** 3428 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3429 */ 3430 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3431 3432 /** 3433 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3434 */ 3435 struct dmub_rb_cmd_abm_set_level abm_set_level; 3436 3437 /** 3438 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3439 */ 3440 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3441 3442 /** 3443 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3444 */ 3445 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3446 3447 /** 3448 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3449 */ 3450 struct dmub_rb_cmd_abm_init_config abm_init_config; 3451 3452 /** 3453 * Definition of a DMUB_CMD__ABM_PAUSE command. 3454 */ 3455 struct dmub_rb_cmd_abm_pause abm_pause; 3456 3457 /** 3458 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3459 */ 3460 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3461 3462 /** 3463 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3464 */ 3465 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3466 3467 /** 3468 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3469 */ 3470 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3471 3472 /** 3473 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3474 */ 3475 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3476 struct dmub_rb_cmd_drr_update drr_update; 3477 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3478 3479 /** 3480 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3481 */ 3482 struct dmub_rb_cmd_lvtma_control lvtma_control; 3483 /** 3484 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3485 */ 3486 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3487 /** 3488 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3489 */ 3490 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3491 /** 3492 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3493 */ 3494 struct dmub_rb_cmd_set_config_access set_config_access; 3495 /** 3496 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3497 */ 3498 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3499 /** 3500 * Definition of a DMUB_CMD__EDID_CEA command. 3501 */ 3502 struct dmub_rb_cmd_edid_cea edid_cea; 3503 /** 3504 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3505 */ 3506 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3507 3508 /** 3509 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3510 */ 3511 struct dmub_rb_cmd_query_hpd_state query_hpd; 3512 /** 3513 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3514 */ 3515 struct dmub_rb_cmd_secure_display secure_display; 3516 3517 /** 3518 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3519 */ 3520 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3521 }; 3522 3523 /** 3524 * union dmub_rb_out_cmd - Outbox command 3525 */ 3526 union dmub_rb_out_cmd { 3527 /** 3528 * Parameters common to every command. 3529 */ 3530 struct dmub_rb_cmd_common cmd_common; 3531 /** 3532 * AUX reply command. 3533 */ 3534 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3535 /** 3536 * HPD notify command. 3537 */ 3538 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3539 /** 3540 * SET_CONFIG reply command. 3541 */ 3542 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3543 /** 3544 * DPIA notification command. 3545 */ 3546 struct dmub_rb_cmd_dpia_notification dpia_notification; 3547 }; 3548 #pragma pack(pop) 3549 3550 3551 //============================================================================== 3552 //</DMUB_CMD>=================================================================== 3553 //============================================================================== 3554 //< DMUB_RB>==================================================================== 3555 //============================================================================== 3556 3557 #if defined(__cplusplus) 3558 extern "C" { 3559 #endif 3560 3561 /** 3562 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3563 */ 3564 struct dmub_rb_init_params { 3565 void *ctx; /**< Caller provided context pointer */ 3566 void *base_address; /**< CPU base address for ring's data */ 3567 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3568 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3569 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3570 }; 3571 3572 /** 3573 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3574 */ 3575 struct dmub_rb { 3576 void *base_address; /**< CPU address for the ring's data */ 3577 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3578 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3579 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3580 3581 void *ctx; /**< Caller provided context pointer */ 3582 void *dmub; /**< Pointer to the DMUB interface */ 3583 }; 3584 3585 /** 3586 * @brief Checks if the ringbuffer is empty. 3587 * 3588 * @param rb DMUB Ringbuffer 3589 * @return true if empty 3590 * @return false otherwise 3591 */ 3592 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3593 { 3594 return (rb->wrpt == rb->rptr); 3595 } 3596 3597 /** 3598 * @brief Checks if the ringbuffer is full 3599 * 3600 * @param rb DMUB Ringbuffer 3601 * @return true if full 3602 * @return false otherwise 3603 */ 3604 static inline bool dmub_rb_full(struct dmub_rb *rb) 3605 { 3606 uint32_t data_count; 3607 3608 if (rb->wrpt >= rb->rptr) 3609 data_count = rb->wrpt - rb->rptr; 3610 else 3611 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3612 3613 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3614 } 3615 3616 /** 3617 * @brief Pushes a command into the ringbuffer 3618 * 3619 * @param rb DMUB ringbuffer 3620 * @param cmd The command to push 3621 * @return true if the ringbuffer was not full 3622 * @return false otherwise 3623 */ 3624 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3625 const union dmub_rb_cmd *cmd) 3626 { 3627 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3628 const uint64_t *src = (const uint64_t *)cmd; 3629 uint8_t i; 3630 3631 if (dmub_rb_full(rb)) 3632 return false; 3633 3634 // copying data 3635 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3636 *dst++ = *src++; 3637 3638 rb->wrpt += DMUB_RB_CMD_SIZE; 3639 3640 if (rb->wrpt >= rb->capacity) 3641 rb->wrpt %= rb->capacity; 3642 3643 return true; 3644 } 3645 3646 /** 3647 * @brief Pushes a command into the DMUB outbox ringbuffer 3648 * 3649 * @param rb DMUB outbox ringbuffer 3650 * @param cmd Outbox command 3651 * @return true if not full 3652 * @return false otherwise 3653 */ 3654 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3655 const union dmub_rb_out_cmd *cmd) 3656 { 3657 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3658 const uint8_t *src = (const uint8_t *)cmd; 3659 3660 if (dmub_rb_full(rb)) 3661 return false; 3662 3663 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3664 3665 rb->wrpt += DMUB_RB_CMD_SIZE; 3666 3667 if (rb->wrpt >= rb->capacity) 3668 rb->wrpt %= rb->capacity; 3669 3670 return true; 3671 } 3672 3673 /** 3674 * @brief Returns the next unprocessed command in the ringbuffer. 3675 * 3676 * @param rb DMUB ringbuffer 3677 * @param cmd The command to return 3678 * @return true if not empty 3679 * @return false otherwise 3680 */ 3681 static inline bool dmub_rb_front(struct dmub_rb *rb, 3682 union dmub_rb_cmd **cmd) 3683 { 3684 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3685 3686 if (dmub_rb_empty(rb)) 3687 return false; 3688 3689 *cmd = (union dmub_rb_cmd *)rb_cmd; 3690 3691 return true; 3692 } 3693 3694 /** 3695 * @brief Determines the next ringbuffer offset. 3696 * 3697 * @param rb DMUB inbox ringbuffer 3698 * @param num_cmds Number of commands 3699 * @param next_rptr The next offset in the ringbuffer 3700 */ 3701 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3702 uint32_t num_cmds, 3703 uint32_t *next_rptr) 3704 { 3705 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3706 3707 if (*next_rptr >= rb->capacity) 3708 *next_rptr %= rb->capacity; 3709 } 3710 3711 /** 3712 * @brief Returns a pointer to a command in the inbox. 3713 * 3714 * @param rb DMUB inbox ringbuffer 3715 * @param cmd The inbox command to return 3716 * @param rptr The ringbuffer offset 3717 * @return true if not empty 3718 * @return false otherwise 3719 */ 3720 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3721 union dmub_rb_cmd **cmd, 3722 uint32_t rptr) 3723 { 3724 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3725 3726 if (dmub_rb_empty(rb)) 3727 return false; 3728 3729 *cmd = (union dmub_rb_cmd *)rb_cmd; 3730 3731 return true; 3732 } 3733 3734 /** 3735 * @brief Returns the next unprocessed command in the outbox. 3736 * 3737 * @param rb DMUB outbox ringbuffer 3738 * @param cmd The outbox command to return 3739 * @return true if not empty 3740 * @return false otherwise 3741 */ 3742 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3743 union dmub_rb_out_cmd *cmd) 3744 { 3745 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3746 uint64_t *dst = (uint64_t *)cmd; 3747 uint8_t i; 3748 3749 if (dmub_rb_empty(rb)) 3750 return false; 3751 3752 // copying data 3753 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3754 *dst++ = *src++; 3755 3756 return true; 3757 } 3758 3759 /** 3760 * @brief Removes the front entry in the ringbuffer. 3761 * 3762 * @param rb DMUB ringbuffer 3763 * @return true if the command was removed 3764 * @return false if there were no commands 3765 */ 3766 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3767 { 3768 if (dmub_rb_empty(rb)) 3769 return false; 3770 3771 rb->rptr += DMUB_RB_CMD_SIZE; 3772 3773 if (rb->rptr >= rb->capacity) 3774 rb->rptr %= rb->capacity; 3775 3776 return true; 3777 } 3778 3779 /** 3780 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3781 * 3782 * Avoids a race condition where DMCUB accesses memory while 3783 * there are still writes in flight to framebuffer. 3784 * 3785 * @param rb DMUB ringbuffer 3786 */ 3787 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3788 { 3789 uint32_t rptr = rb->rptr; 3790 uint32_t wptr = rb->wrpt; 3791 3792 while (rptr != wptr) { 3793 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3794 uint8_t i; 3795 3796 /* Don't remove this. 3797 * The contents need to actually be read from the ring buffer 3798 * for this function to be effective. 3799 */ 3800 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3801 (void)READ_ONCE(*data++); 3802 3803 rptr += DMUB_RB_CMD_SIZE; 3804 if (rptr >= rb->capacity) 3805 rptr %= rb->capacity; 3806 } 3807 } 3808 3809 /** 3810 * @brief Initializes a DMCUB ringbuffer 3811 * 3812 * @param rb DMUB ringbuffer 3813 * @param init_params initial configuration for the ringbuffer 3814 */ 3815 static inline void dmub_rb_init(struct dmub_rb *rb, 3816 struct dmub_rb_init_params *init_params) 3817 { 3818 rb->base_address = init_params->base_address; 3819 rb->capacity = init_params->capacity; 3820 rb->rptr = init_params->read_ptr; 3821 rb->wrpt = init_params->write_ptr; 3822 } 3823 3824 /** 3825 * @brief Copies output data from in/out commands into the given command. 3826 * 3827 * @param rb DMUB ringbuffer 3828 * @param cmd Command to copy data into 3829 */ 3830 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3831 union dmub_rb_cmd *cmd) 3832 { 3833 // Copy rb entry back into command 3834 uint8_t *rd_ptr = (rb->rptr == 0) ? 3835 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3836 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3837 3838 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3839 } 3840 3841 #if defined(__cplusplus) 3842 } 3843 #endif 3844 3845 //============================================================================== 3846 //</DMUB_RB>==================================================================== 3847 //============================================================================== 3848 3849 #endif /* _DMUB_CMD_H_ */ 3850