1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0xe599e0896 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 76 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 /* Trace buffer offset for entry */ 121 #define TRACE_BUFFER_ENTRY_OFFSET 16 122 123 /** 124 * 125 * PSR control version legacy 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 128 /** 129 * PSR control version with multi edp support 130 */ 131 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 132 133 134 /** 135 * ABM control version legacy 136 */ 137 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 138 139 /** 140 * ABM control version with multi edp support 141 */ 142 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 143 144 /** 145 * Physical framebuffer address location, 64-bit. 146 */ 147 #ifndef PHYSICAL_ADDRESS_LOC 148 #define PHYSICAL_ADDRESS_LOC union large_integer 149 #endif 150 151 /** 152 * OS/FW agnostic memcpy 153 */ 154 #ifndef dmub_memcpy 155 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 156 #endif 157 158 /** 159 * OS/FW agnostic memset 160 */ 161 #ifndef dmub_memset 162 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 163 #endif 164 165 #if defined(__cplusplus) 166 extern "C" { 167 #endif 168 169 /** 170 * OS/FW agnostic udelay 171 */ 172 #ifndef dmub_udelay 173 #define dmub_udelay(microseconds) udelay(microseconds) 174 #endif 175 176 /** 177 * Number of nanoseconds per DMUB tick. 178 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 179 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 180 */ 181 #define NS_PER_DMUB_TICK 10 182 183 /** 184 * union dmub_addr - DMUB physical/virtual 64-bit address. 185 */ 186 union dmub_addr { 187 struct { 188 uint32_t low_part; /**< Lower 32 bits */ 189 uint32_t high_part; /**< Upper 32 bits */ 190 } u; /*<< Low/high bit access */ 191 uint64_t quad_part; /*<< 64 bit address */ 192 }; 193 194 /** 195 * Flags that can be set by driver to change some PSR behaviour. 196 */ 197 union dmub_psr_debug_flags { 198 /** 199 * Debug flags. 200 */ 201 struct { 202 /** 203 * Enable visual confirm in FW. 204 */ 205 uint32_t visual_confirm : 1; 206 /** 207 * Use HW Lock Mgr object to do HW locking in FW. 208 */ 209 uint32_t use_hw_lock_mgr : 1; 210 211 /** 212 * Unused. 213 * TODO: Remove. 214 */ 215 uint32_t log_line_nums : 1; 216 } bitfields; 217 218 /** 219 * Union for debug flags. 220 */ 221 uint32_t u32All; 222 }; 223 224 /** 225 * DMUB feature capabilities. 226 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 227 */ 228 struct dmub_feature_caps { 229 /** 230 * Max PSR version supported by FW. 231 */ 232 uint8_t psr; 233 uint8_t reserved[7]; 234 }; 235 236 #if defined(__cplusplus) 237 } 238 #endif 239 240 //============================================================================== 241 //</DMUB_TYPES>================================================================= 242 //============================================================================== 243 //< DMUB_META>================================================================== 244 //============================================================================== 245 #pragma pack(push, 1) 246 247 /* Magic value for identifying dmub_fw_meta_info */ 248 #define DMUB_FW_META_MAGIC 0x444D5542 249 250 /* Offset from the end of the file to the dmub_fw_meta_info */ 251 #define DMUB_FW_META_OFFSET 0x24 252 253 /** 254 * struct dmub_fw_meta_info - metadata associated with fw binary 255 * 256 * NOTE: This should be considered a stable API. Fields should 257 * not be repurposed or reordered. New fields should be 258 * added instead to extend the structure. 259 * 260 * @magic_value: magic value identifying DMUB firmware meta info 261 * @fw_region_size: size of the firmware state region 262 * @trace_buffer_size: size of the tracebuffer region 263 * @fw_version: the firmware version information 264 * @dal_fw: 1 if the firmware is DAL 265 */ 266 struct dmub_fw_meta_info { 267 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 268 uint32_t fw_region_size; /**< size of the firmware state region */ 269 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 270 uint32_t fw_version; /**< the firmware version information */ 271 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 272 uint8_t reserved[3]; /**< padding bits */ 273 }; 274 275 /** 276 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 277 */ 278 union dmub_fw_meta { 279 struct dmub_fw_meta_info info; /**< metadata info */ 280 uint8_t reserved[64]; /**< padding bits */ 281 }; 282 283 #pragma pack(pop) 284 285 //============================================================================== 286 //< DMUB Trace Buffer>================================================================ 287 //============================================================================== 288 /** 289 * dmub_trace_code_t - firmware trace code, 32-bits 290 */ 291 typedef uint32_t dmub_trace_code_t; 292 293 /** 294 * struct dmcub_trace_buf_entry - Firmware trace entry 295 */ 296 struct dmcub_trace_buf_entry { 297 dmub_trace_code_t trace_code; /**< trace code for the event */ 298 uint32_t tick_count; /**< the tick count at time of trace */ 299 uint32_t param0; /**< trace defined parameter 0 */ 300 uint32_t param1; /**< trace defined parameter 1 */ 301 }; 302 303 //============================================================================== 304 //< DMUB_STATUS>================================================================ 305 //============================================================================== 306 307 /** 308 * DMCUB scratch registers can be used to determine firmware status. 309 * Current scratch register usage is as follows: 310 * 311 * SCRATCH0: FW Boot Status register 312 * SCRATCH5: LVTMA Status Register 313 * SCRATCH15: FW Boot Options register 314 */ 315 316 /** 317 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 318 */ 319 union dmub_fw_boot_status { 320 struct { 321 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 322 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 323 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 324 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 325 } bits; /**< status bits */ 326 uint32_t all; /**< 32-bit access to status bits */ 327 }; 328 329 /** 330 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 331 */ 332 enum dmub_fw_boot_status_bit { 333 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 334 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 335 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 336 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 337 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 338 }; 339 340 /* Register bit definition for SCRATCH5 */ 341 union dmub_lvtma_status { 342 struct { 343 uint32_t psp_ok : 1; 344 uint32_t edp_on : 1; 345 uint32_t reserved : 30; 346 } bits; 347 uint32_t all; 348 }; 349 350 enum dmub_lvtma_status_bit { 351 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 352 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 353 }; 354 355 /** 356 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 357 */ 358 union dmub_fw_boot_options { 359 struct { 360 uint32_t pemu_env : 1; /**< 1 if PEMU */ 361 uint32_t fpga_env : 1; /**< 1 if FPGA */ 362 uint32_t optimized_init : 1; /**< 1 if optimized init */ 363 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 364 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 365 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 366 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 367 uint32_t reserved2: 1; /**< reserved for an unreleased feature */ 368 uint32_t reserved_unreleased1: 1; /**< reserved for an unreleased feature */ 369 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 370 uint32_t reserved : 23; /**< reserved */ 371 } bits; /**< boot bits */ 372 uint32_t all; /**< 32-bit access to bits */ 373 }; 374 375 enum dmub_fw_boot_options_bit { 376 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 377 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 378 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 379 }; 380 381 //============================================================================== 382 //</DMUB_STATUS>================================================================ 383 //============================================================================== 384 //< DMUB_VBIOS>================================================================= 385 //============================================================================== 386 387 /* 388 * enum dmub_cmd_vbios_type - VBIOS commands. 389 * 390 * Command IDs should be treated as stable ABI. 391 * Do not reuse or modify IDs. 392 */ 393 enum dmub_cmd_vbios_type { 394 /** 395 * Configures the DIG encoder. 396 */ 397 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 398 /** 399 * Controls the PHY. 400 */ 401 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 402 /** 403 * Sets the pixel clock/symbol clock. 404 */ 405 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 406 /** 407 * Enables or disables power gating. 408 */ 409 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 410 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 411 }; 412 413 //============================================================================== 414 //</DMUB_VBIOS>================================================================= 415 //============================================================================== 416 //< DMUB_GPINT>================================================================= 417 //============================================================================== 418 419 /** 420 * The shifts and masks below may alternatively be used to format and read 421 * the command register bits. 422 */ 423 424 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 425 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 426 427 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 428 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 429 430 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 431 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 432 433 /** 434 * Command responses. 435 */ 436 437 /** 438 * Return response for DMUB_GPINT__STOP_FW command. 439 */ 440 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 441 442 /** 443 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 444 */ 445 union dmub_gpint_data_register { 446 struct { 447 uint32_t param : 16; /**< 16-bit parameter */ 448 uint32_t command_code : 12; /**< GPINT command */ 449 uint32_t status : 4; /**< Command status bit */ 450 } bits; /**< GPINT bit access */ 451 uint32_t all; /**< GPINT 32-bit access */ 452 }; 453 454 /* 455 * enum dmub_gpint_command - GPINT command to DMCUB FW 456 * 457 * Command IDs should be treated as stable ABI. 458 * Do not reuse or modify IDs. 459 */ 460 enum dmub_gpint_command { 461 /** 462 * Invalid command, ignored. 463 */ 464 DMUB_GPINT__INVALID_COMMAND = 0, 465 /** 466 * DESC: Queries the firmware version. 467 * RETURN: Firmware version. 468 */ 469 DMUB_GPINT__GET_FW_VERSION = 1, 470 /** 471 * DESC: Halts the firmware. 472 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 473 */ 474 DMUB_GPINT__STOP_FW = 2, 475 /** 476 * DESC: Get PSR state from FW. 477 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 478 */ 479 DMUB_GPINT__GET_PSR_STATE = 7, 480 /** 481 * DESC: Notifies DMCUB of the currently active streams. 482 * ARGS: Stream mask, 1 bit per active stream index. 483 */ 484 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 485 /** 486 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 487 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 488 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 489 * RETURN: PSR residency in milli-percent. 490 */ 491 DMUB_GPINT__PSR_RESIDENCY = 9, 492 }; 493 494 /** 495 * INBOX0 generic command definition 496 */ 497 union dmub_inbox0_cmd_common { 498 struct { 499 uint32_t command_code: 8; /**< INBOX0 command code */ 500 uint32_t param: 24; /**< 24-bit parameter */ 501 } bits; 502 uint32_t all; 503 }; 504 505 /** 506 * INBOX0 hw_lock command definition 507 */ 508 union dmub_inbox0_cmd_lock_hw { 509 struct { 510 uint32_t command_code: 8; 511 512 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 513 uint32_t hw_lock_client: 1; 514 515 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 516 uint32_t otg_inst: 3; 517 uint32_t opp_inst: 3; 518 uint32_t dig_inst: 3; 519 520 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 521 uint32_t lock_pipe: 1; 522 uint32_t lock_cursor: 1; 523 uint32_t lock_dig: 1; 524 uint32_t triple_buffer_lock: 1; 525 526 uint32_t lock: 1; /**< Lock */ 527 uint32_t should_release: 1; /**< Release */ 528 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 529 } bits; 530 uint32_t all; 531 }; 532 533 union dmub_inbox0_data_register { 534 union dmub_inbox0_cmd_common inbox0_cmd_common; 535 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 536 }; 537 538 enum dmub_inbox0_command { 539 /** 540 * DESC: Invalid command, ignored. 541 */ 542 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 543 /** 544 * DESC: Notification to acquire/release HW lock 545 * ARGS: 546 */ 547 DMUB_INBOX0_CMD__HW_LOCK = 1, 548 }; 549 //============================================================================== 550 //</DMUB_GPINT>================================================================= 551 //============================================================================== 552 //< DMUB_CMD>=================================================================== 553 //============================================================================== 554 555 /** 556 * Size in bytes of each DMUB command. 557 */ 558 #define DMUB_RB_CMD_SIZE 64 559 560 /** 561 * Maximum number of items in the DMUB ringbuffer. 562 */ 563 #define DMUB_RB_MAX_ENTRY 128 564 565 /** 566 * Ringbuffer size in bytes. 567 */ 568 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 569 570 /** 571 * REG_SET mask for reg offload. 572 */ 573 #define REG_SET_MASK 0xFFFF 574 575 /* 576 * enum dmub_cmd_type - DMUB inbox command. 577 * 578 * Command IDs should be treated as stable ABI. 579 * Do not reuse or modify IDs. 580 */ 581 enum dmub_cmd_type { 582 /** 583 * Invalid command. 584 */ 585 DMUB_CMD__NULL = 0, 586 /** 587 * Read modify write register sequence offload. 588 */ 589 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 590 /** 591 * Field update register sequence offload. 592 */ 593 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 594 /** 595 * Burst write sequence offload. 596 */ 597 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 598 /** 599 * Reg wait sequence offload. 600 */ 601 DMUB_CMD__REG_REG_WAIT = 4, 602 /** 603 * Workaround to avoid HUBP underflow during NV12 playback. 604 */ 605 DMUB_CMD__PLAT_54186_WA = 5, 606 /** 607 * Command type used to query FW feature caps. 608 */ 609 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 610 /** 611 * Command type used for all PSR commands. 612 */ 613 DMUB_CMD__PSR = 64, 614 /** 615 * Command type used for all MALL commands. 616 */ 617 DMUB_CMD__MALL = 65, 618 /** 619 * Command type used for all ABM commands. 620 */ 621 DMUB_CMD__ABM = 66, 622 /** 623 * Command type used for HW locking in FW. 624 */ 625 DMUB_CMD__HW_LOCK = 69, 626 /** 627 * Command type used to access DP AUX. 628 */ 629 DMUB_CMD__DP_AUX_ACCESS = 70, 630 /** 631 * Command type used for OUTBOX1 notification enable 632 */ 633 DMUB_CMD__OUTBOX1_ENABLE = 71, 634 /** 635 * Command type used for all idle optimization commands. 636 */ 637 DMUB_CMD__IDLE_OPT = 72, 638 /** 639 * Command type used for all clock manager commands. 640 */ 641 DMUB_CMD__CLK_MGR = 73, 642 /** 643 * Command type used for all panel control commands. 644 */ 645 DMUB_CMD__PANEL_CNTL = 74, 646 /** 647 * Command type used for EDID CEA parsing 648 */ 649 DMUB_CMD__EDID_CEA = 79, 650 /** 651 * Command type used for all VBIOS interface commands. 652 */ 653 DMUB_CMD__VBIOS = 128, 654 }; 655 656 /** 657 * enum dmub_out_cmd_type - DMUB outbox commands. 658 */ 659 enum dmub_out_cmd_type { 660 /** 661 * Invalid outbox command, ignored. 662 */ 663 DMUB_OUT_CMD__NULL = 0, 664 /** 665 * Command type used for DP AUX Reply data notification 666 */ 667 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 668 }; 669 670 #pragma pack(push, 1) 671 672 /** 673 * struct dmub_cmd_header - Common command header fields. 674 */ 675 struct dmub_cmd_header { 676 unsigned int type : 8; /**< command type */ 677 unsigned int sub_type : 8; /**< command sub type */ 678 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 679 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 680 unsigned int reserved0 : 6; /**< reserved bits */ 681 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 682 unsigned int reserved1 : 2; /**< reserved bits */ 683 }; 684 685 /* 686 * struct dmub_cmd_read_modify_write_sequence - Read modify write 687 * 688 * 60 payload bytes can hold up to 5 sets of read modify writes, 689 * each take 3 dwords. 690 * 691 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 692 * 693 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 694 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 695 */ 696 struct dmub_cmd_read_modify_write_sequence { 697 uint32_t addr; /**< register address */ 698 uint32_t modify_mask; /**< modify mask */ 699 uint32_t modify_value; /**< modify value */ 700 }; 701 702 /** 703 * Maximum number of ops in read modify write sequence. 704 */ 705 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 706 707 /** 708 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 709 */ 710 struct dmub_rb_cmd_read_modify_write { 711 struct dmub_cmd_header header; /**< command header */ 712 /** 713 * Read modify write sequence. 714 */ 715 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 716 }; 717 718 /* 719 * Update a register with specified masks and values sequeunce 720 * 721 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 722 * 723 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 724 * 725 * 726 * USE CASE: 727 * 1. auto-increment register where additional read would update pointer and produce wrong result 728 * 2. toggle a bit without read in the middle 729 */ 730 731 struct dmub_cmd_reg_field_update_sequence { 732 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 733 uint32_t modify_value; /**< value to update with */ 734 }; 735 736 /** 737 * Maximum number of ops in field update sequence. 738 */ 739 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 740 741 /** 742 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 743 */ 744 struct dmub_rb_cmd_reg_field_update_sequence { 745 struct dmub_cmd_header header; /**< command header */ 746 uint32_t addr; /**< register address */ 747 /** 748 * Field update sequence. 749 */ 750 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 751 }; 752 753 754 /** 755 * Maximum number of burst write values. 756 */ 757 #define DMUB_BURST_WRITE_VALUES__MAX 14 758 759 /* 760 * struct dmub_rb_cmd_burst_write - Burst write 761 * 762 * support use case such as writing out LUTs. 763 * 764 * 60 payload bytes can hold up to 14 values to write to given address 765 * 766 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 767 */ 768 struct dmub_rb_cmd_burst_write { 769 struct dmub_cmd_header header; /**< command header */ 770 uint32_t addr; /**< register start address */ 771 /** 772 * Burst write register values. 773 */ 774 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 775 }; 776 777 /** 778 * struct dmub_rb_cmd_common - Common command header 779 */ 780 struct dmub_rb_cmd_common { 781 struct dmub_cmd_header header; /**< command header */ 782 /** 783 * Padding to RB_CMD_SIZE 784 */ 785 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 786 }; 787 788 /** 789 * struct dmub_cmd_reg_wait_data - Register wait data 790 */ 791 struct dmub_cmd_reg_wait_data { 792 uint32_t addr; /**< Register address */ 793 uint32_t mask; /**< Mask for register bits */ 794 uint32_t condition_field_value; /**< Value to wait for */ 795 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 796 }; 797 798 /** 799 * struct dmub_rb_cmd_reg_wait - Register wait command 800 */ 801 struct dmub_rb_cmd_reg_wait { 802 struct dmub_cmd_header header; /**< Command header */ 803 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 804 }; 805 806 /** 807 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 808 * 809 * Reprograms surface parameters to avoid underflow. 810 */ 811 struct dmub_cmd_PLAT_54186_wa { 812 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 813 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 814 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 815 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 816 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 817 struct { 818 uint8_t hubp_inst : 4; /**< HUBP instance */ 819 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 820 uint8_t immediate :1; /**< Immediate flip */ 821 uint8_t vmid : 4; /**< VMID */ 822 uint8_t grph_stereo : 1; /**< 1 if stereo */ 823 uint32_t reserved : 21; /**< Reserved */ 824 } flip_params; /**< Pageflip parameters */ 825 uint32_t reserved[9]; /**< Reserved bits */ 826 }; 827 828 /** 829 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 830 */ 831 struct dmub_rb_cmd_PLAT_54186_wa { 832 struct dmub_cmd_header header; /**< Command header */ 833 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 834 }; 835 836 /** 837 * struct dmub_rb_cmd_mall - MALL command data. 838 */ 839 struct dmub_rb_cmd_mall { 840 struct dmub_cmd_header header; /**< Common command header */ 841 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 842 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 843 uint32_t tmr_delay; /**< Timer delay */ 844 uint32_t tmr_scale; /**< Timer scale */ 845 uint16_t cursor_width; /**< Cursor width in pixels */ 846 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 847 uint16_t cursor_height; /**< Cursor height in pixels */ 848 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 849 uint8_t debug_bits; /**< Debug bits */ 850 851 uint8_t reserved1; /**< Reserved bits */ 852 uint8_t reserved2; /**< Reserved bits */ 853 }; 854 855 /** 856 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 857 */ 858 enum dmub_cmd_idle_opt_type { 859 /** 860 * DCN hardware restore. 861 */ 862 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 863 }; 864 865 /** 866 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 867 */ 868 struct dmub_rb_cmd_idle_opt_dcn_restore { 869 struct dmub_cmd_header header; /**< header */ 870 }; 871 872 /** 873 * struct dmub_clocks - Clock update notification. 874 */ 875 struct dmub_clocks { 876 uint32_t dispclk_khz; /**< dispclk kHz */ 877 uint32_t dppclk_khz; /**< dppclk kHz */ 878 uint32_t dcfclk_khz; /**< dcfclk kHz */ 879 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 880 }; 881 882 /** 883 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 884 */ 885 enum dmub_cmd_clk_mgr_type { 886 /** 887 * Notify DMCUB of clock update. 888 */ 889 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 890 }; 891 892 /** 893 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 894 */ 895 struct dmub_rb_cmd_clk_mgr_notify_clocks { 896 struct dmub_cmd_header header; /**< header */ 897 struct dmub_clocks clocks; /**< clock data */ 898 }; 899 900 /** 901 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 902 */ 903 struct dmub_cmd_digx_encoder_control_data { 904 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 905 }; 906 907 /** 908 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 909 */ 910 struct dmub_rb_cmd_digx_encoder_control { 911 struct dmub_cmd_header header; /**< header */ 912 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 913 }; 914 915 /** 916 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 917 */ 918 struct dmub_cmd_set_pixel_clock_data { 919 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 920 }; 921 922 /** 923 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 924 */ 925 struct dmub_rb_cmd_set_pixel_clock { 926 struct dmub_cmd_header header; /**< header */ 927 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 928 }; 929 930 /** 931 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 932 */ 933 struct dmub_cmd_enable_disp_power_gating_data { 934 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 935 }; 936 937 /** 938 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 939 */ 940 struct dmub_rb_cmd_enable_disp_power_gating { 941 struct dmub_cmd_header header; /**< header */ 942 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 943 }; 944 945 /** 946 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 947 */ 948 struct dmub_dig_transmitter_control_data_v1_7 { 949 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 950 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 951 union { 952 uint8_t digmode; /**< enum atom_encode_mode_def */ 953 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 954 } mode_laneset; 955 uint8_t lanenum; /**< Number of lanes */ 956 union { 957 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 958 } symclk_units; 959 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 960 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 961 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 962 uint8_t reserved0; /**< For future use */ 963 uint8_t reserved1; /**< For future use */ 964 uint8_t reserved2[3]; /**< For future use */ 965 uint32_t reserved3[11]; /**< For future use */ 966 }; 967 968 /** 969 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 970 */ 971 union dmub_cmd_dig1_transmitter_control_data { 972 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 973 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 974 }; 975 976 /** 977 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 978 */ 979 struct dmub_rb_cmd_dig1_transmitter_control { 980 struct dmub_cmd_header header; /**< header */ 981 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 982 }; 983 984 /** 985 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 986 */ 987 struct dmub_rb_cmd_dpphy_init { 988 struct dmub_cmd_header header; /**< header */ 989 uint8_t reserved[60]; /**< reserved bits */ 990 }; 991 992 /** 993 * enum dp_aux_request_action - DP AUX request command listing. 994 * 995 * 4 AUX request command bits are shifted to high nibble. 996 */ 997 enum dp_aux_request_action { 998 /** I2C-over-AUX write request */ 999 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1000 /** I2C-over-AUX read request */ 1001 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1002 /** I2C-over-AUX write status request */ 1003 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1004 /** I2C-over-AUX write request with MOT=1 */ 1005 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1006 /** I2C-over-AUX read request with MOT=1 */ 1007 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1008 /** I2C-over-AUX write status request with MOT=1 */ 1009 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1010 /** Native AUX write request */ 1011 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1012 /** Native AUX read request */ 1013 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1014 }; 1015 1016 /** 1017 * enum aux_return_code_type - DP AUX process return code listing. 1018 */ 1019 enum aux_return_code_type { 1020 /** AUX process succeeded */ 1021 AUX_RET_SUCCESS = 0, 1022 /** AUX process failed with unknown reason */ 1023 AUX_RET_ERROR_UNKNOWN, 1024 /** AUX process completed with invalid reply */ 1025 AUX_RET_ERROR_INVALID_REPLY, 1026 /** AUX process timed out */ 1027 AUX_RET_ERROR_TIMEOUT, 1028 /** HPD was low during AUX process */ 1029 AUX_RET_ERROR_HPD_DISCON, 1030 /** Failed to acquire AUX engine */ 1031 AUX_RET_ERROR_ENGINE_ACQUIRE, 1032 /** AUX request not supported */ 1033 AUX_RET_ERROR_INVALID_OPERATION, 1034 /** AUX process not available */ 1035 AUX_RET_ERROR_PROTOCOL_ERROR, 1036 }; 1037 1038 /** 1039 * enum aux_channel_type - DP AUX channel type listing. 1040 */ 1041 enum aux_channel_type { 1042 /** AUX thru Legacy DP AUX */ 1043 AUX_CHANNEL_LEGACY_DDC, 1044 /** AUX thru DPIA DP tunneling */ 1045 AUX_CHANNEL_DPIA 1046 }; 1047 1048 /** 1049 * struct aux_transaction_parameters - DP AUX request transaction data 1050 */ 1051 struct aux_transaction_parameters { 1052 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1053 uint8_t action; /**< enum dp_aux_request_action */ 1054 uint8_t length; /**< DP AUX request data length */ 1055 uint8_t reserved; /**< For future use */ 1056 uint32_t address; /**< DP AUX address */ 1057 uint8_t data[16]; /**< DP AUX write data */ 1058 }; 1059 1060 /** 1061 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1062 */ 1063 struct dmub_cmd_dp_aux_control_data { 1064 uint8_t instance; /**< AUX instance or DPIA instance */ 1065 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1066 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1067 uint8_t reserved0; /**< For future use */ 1068 uint16_t timeout; /**< timeout time in us */ 1069 uint16_t reserved1; /**< For future use */ 1070 enum aux_channel_type type; /**< enum aux_channel_type */ 1071 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1072 }; 1073 1074 /** 1075 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1076 */ 1077 struct dmub_rb_cmd_dp_aux_access { 1078 /** 1079 * Command header. 1080 */ 1081 struct dmub_cmd_header header; 1082 /** 1083 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1084 */ 1085 struct dmub_cmd_dp_aux_control_data aux_control; 1086 }; 1087 1088 /** 1089 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1090 */ 1091 struct dmub_rb_cmd_outbox1_enable { 1092 /** 1093 * Command header. 1094 */ 1095 struct dmub_cmd_header header; 1096 /** 1097 * enable: 0x0 -> disable outbox1 notification (default value) 1098 * 0x1 -> enable outbox1 notification 1099 */ 1100 uint32_t enable; 1101 }; 1102 1103 /* DP AUX Reply command - OutBox Cmd */ 1104 /** 1105 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1106 */ 1107 struct aux_reply_data { 1108 /** 1109 * Aux cmd 1110 */ 1111 uint8_t command; 1112 /** 1113 * Aux reply data length (max: 16 bytes) 1114 */ 1115 uint8_t length; 1116 /** 1117 * Alignment only 1118 */ 1119 uint8_t pad[2]; 1120 /** 1121 * Aux reply data 1122 */ 1123 uint8_t data[16]; 1124 }; 1125 1126 /** 1127 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1128 */ 1129 struct aux_reply_control_data { 1130 /** 1131 * Reserved for future use 1132 */ 1133 uint32_t handle; 1134 /** 1135 * Aux Instance 1136 */ 1137 uint8_t instance; 1138 /** 1139 * Aux transaction result: definition in enum aux_return_code_type 1140 */ 1141 uint8_t result; 1142 /** 1143 * Alignment only 1144 */ 1145 uint16_t pad; 1146 }; 1147 1148 /** 1149 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1150 */ 1151 struct dmub_rb_cmd_dp_aux_reply { 1152 /** 1153 * Command header. 1154 */ 1155 struct dmub_cmd_header header; 1156 /** 1157 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1158 */ 1159 struct aux_reply_control_data control; 1160 /** 1161 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1162 */ 1163 struct aux_reply_data reply_data; 1164 }; 1165 1166 /* DP HPD Notify command - OutBox Cmd */ 1167 /** 1168 * DP HPD Type 1169 */ 1170 enum dp_hpd_type { 1171 /** 1172 * Normal DP HPD 1173 */ 1174 DP_HPD = 0, 1175 /** 1176 * DP HPD short pulse 1177 */ 1178 DP_IRQ 1179 }; 1180 1181 /** 1182 * DP HPD Status 1183 */ 1184 enum dp_hpd_status { 1185 /** 1186 * DP_HPD status low 1187 */ 1188 DP_HPD_UNPLUG = 0, 1189 /** 1190 * DP_HPD status high 1191 */ 1192 DP_HPD_PLUG 1193 }; 1194 1195 /** 1196 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1197 */ 1198 struct dp_hpd_data { 1199 /** 1200 * DP HPD instance 1201 */ 1202 uint8_t instance; 1203 /** 1204 * HPD type 1205 */ 1206 uint8_t hpd_type; 1207 /** 1208 * HPD status: only for type: DP_HPD to indicate status 1209 */ 1210 uint8_t hpd_status; 1211 /** 1212 * Alignment only 1213 */ 1214 uint8_t pad; 1215 }; 1216 1217 /** 1218 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1219 */ 1220 struct dmub_rb_cmd_dp_hpd_notify { 1221 /** 1222 * Command header. 1223 */ 1224 struct dmub_cmd_header header; 1225 /** 1226 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1227 */ 1228 struct dp_hpd_data hpd_data; 1229 }; 1230 1231 /* 1232 * Command IDs should be treated as stable ABI. 1233 * Do not reuse or modify IDs. 1234 */ 1235 1236 /** 1237 * PSR command sub-types. 1238 */ 1239 enum dmub_cmd_psr_type { 1240 /** 1241 * Set PSR version support. 1242 */ 1243 DMUB_CMD__PSR_SET_VERSION = 0, 1244 /** 1245 * Copy driver-calculated parameters to PSR state. 1246 */ 1247 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1248 /** 1249 * Enable PSR. 1250 */ 1251 DMUB_CMD__PSR_ENABLE = 2, 1252 1253 /** 1254 * Disable PSR. 1255 */ 1256 DMUB_CMD__PSR_DISABLE = 3, 1257 1258 /** 1259 * Set PSR level. 1260 * PSR level is a 16-bit value dicated by driver that 1261 * will enable/disable different functionality. 1262 */ 1263 DMUB_CMD__PSR_SET_LEVEL = 4, 1264 1265 /** 1266 * Forces PSR enabled until an explicit PSR disable call. 1267 */ 1268 DMUB_CMD__PSR_FORCE_STATIC = 5, 1269 }; 1270 1271 /** 1272 * PSR versions. 1273 */ 1274 enum psr_version { 1275 /** 1276 * PSR version 1. 1277 */ 1278 PSR_VERSION_1 = 0, 1279 /** 1280 * PSR not supported. 1281 */ 1282 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1283 }; 1284 1285 /** 1286 * enum dmub_cmd_mall_type - MALL commands 1287 */ 1288 enum dmub_cmd_mall_type { 1289 /** 1290 * Allows display refresh from MALL. 1291 */ 1292 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1293 /** 1294 * Disallows display refresh from MALL. 1295 */ 1296 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1297 /** 1298 * Cursor copy for MALL. 1299 */ 1300 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1301 /** 1302 * Controls DF requests. 1303 */ 1304 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1305 }; 1306 1307 1308 /** 1309 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1310 */ 1311 struct dmub_cmd_psr_copy_settings_data { 1312 /** 1313 * Flags that can be set by driver to change some PSR behaviour. 1314 */ 1315 union dmub_psr_debug_flags debug; 1316 /** 1317 * 16-bit value dicated by driver that will enable/disable different functionality. 1318 */ 1319 uint16_t psr_level; 1320 /** 1321 * DPP HW instance. 1322 */ 1323 uint8_t dpp_inst; 1324 /** 1325 * MPCC HW instance. 1326 * Not used in dmub fw, 1327 * dmub fw will get active opp by reading odm registers. 1328 */ 1329 uint8_t mpcc_inst; 1330 /** 1331 * OPP HW instance. 1332 * Not used in dmub fw, 1333 * dmub fw will get active opp by reading odm registers. 1334 */ 1335 uint8_t opp_inst; 1336 /** 1337 * OTG HW instance. 1338 */ 1339 uint8_t otg_inst; 1340 /** 1341 * DIG FE HW instance. 1342 */ 1343 uint8_t digfe_inst; 1344 /** 1345 * DIG BE HW instance. 1346 */ 1347 uint8_t digbe_inst; 1348 /** 1349 * DP PHY HW instance. 1350 */ 1351 uint8_t dpphy_inst; 1352 /** 1353 * AUX HW instance. 1354 */ 1355 uint8_t aux_inst; 1356 /** 1357 * Determines if SMU optimzations are enabled/disabled. 1358 */ 1359 uint8_t smu_optimizations_en; 1360 /** 1361 * Unused. 1362 * TODO: Remove. 1363 */ 1364 uint8_t frame_delay; 1365 /** 1366 * If RFB setup time is greater than the total VBLANK time, 1367 * it is not possible for the sink to capture the video frame 1368 * in the same frame the SDP is sent. In this case, 1369 * the frame capture indication bit should be set and an extra 1370 * static frame should be transmitted to the sink. 1371 */ 1372 uint8_t frame_cap_ind; 1373 /** 1374 * Explicit padding to 4 byte boundary. 1375 */ 1376 uint8_t pad[2]; 1377 /** 1378 * Multi-display optimizations are implemented on certain ASICs. 1379 */ 1380 uint8_t multi_disp_optimizations_en; 1381 /** 1382 * The last possible line SDP may be transmitted without violating 1383 * the RFB setup time or entering the active video frame. 1384 */ 1385 uint16_t init_sdp_deadline; 1386 /** 1387 * Explicit padding to 4 byte boundary. 1388 */ 1389 uint16_t pad2; 1390 /** 1391 * Length of each horizontal line in us. 1392 */ 1393 uint32_t line_time_in_us; 1394 /** 1395 * FEC enable status in driver 1396 */ 1397 uint8_t fec_enable_status; 1398 /** 1399 * FEC re-enable delay when PSR exit. 1400 * unit is 100us, range form 0~255(0xFF). 1401 */ 1402 uint8_t fec_enable_delay_in100us; 1403 /** 1404 * PSR control version. 1405 */ 1406 uint8_t cmd_version; 1407 /** 1408 * Panel Instance. 1409 * Panel isntance to identify which psr_state to use 1410 * Currently the support is only for 0 or 1 1411 */ 1412 uint8_t panel_inst; 1413 /** 1414 * Explicit padding to 4 byte boundary. 1415 */ 1416 uint8_t pad3[4]; 1417 }; 1418 1419 /** 1420 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1421 */ 1422 struct dmub_rb_cmd_psr_copy_settings { 1423 /** 1424 * Command header. 1425 */ 1426 struct dmub_cmd_header header; 1427 /** 1428 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1429 */ 1430 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1431 }; 1432 1433 /** 1434 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1435 */ 1436 struct dmub_cmd_psr_set_level_data { 1437 /** 1438 * 16-bit value dicated by driver that will enable/disable different functionality. 1439 */ 1440 uint16_t psr_level; 1441 /** 1442 * PSR control version. 1443 */ 1444 uint8_t cmd_version; 1445 /** 1446 * Panel Instance. 1447 * Panel isntance to identify which psr_state to use 1448 * Currently the support is only for 0 or 1 1449 */ 1450 uint8_t panel_inst; 1451 }; 1452 1453 /** 1454 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1455 */ 1456 struct dmub_rb_cmd_psr_set_level { 1457 /** 1458 * Command header. 1459 */ 1460 struct dmub_cmd_header header; 1461 /** 1462 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1463 */ 1464 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1465 }; 1466 1467 struct dmub_rb_cmd_psr_enable_data { 1468 /** 1469 * PSR control version. 1470 */ 1471 uint8_t cmd_version; 1472 /** 1473 * Panel Instance. 1474 * Panel isntance to identify which psr_state to use 1475 * Currently the support is only for 0 or 1 1476 */ 1477 uint8_t panel_inst; 1478 /** 1479 * Explicit padding to 4 byte boundary. 1480 */ 1481 uint8_t pad[2]; 1482 }; 1483 1484 /** 1485 * Definition of a DMUB_CMD__PSR_ENABLE command. 1486 * PSR enable/disable is controlled using the sub_type. 1487 */ 1488 struct dmub_rb_cmd_psr_enable { 1489 /** 1490 * Command header. 1491 */ 1492 struct dmub_cmd_header header; 1493 1494 struct dmub_rb_cmd_psr_enable_data data; 1495 }; 1496 1497 /** 1498 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1499 */ 1500 struct dmub_cmd_psr_set_version_data { 1501 /** 1502 * PSR version that FW should implement. 1503 */ 1504 enum psr_version version; 1505 /** 1506 * PSR control version. 1507 */ 1508 uint8_t cmd_version; 1509 /** 1510 * Panel Instance. 1511 * Panel isntance to identify which psr_state to use 1512 * Currently the support is only for 0 or 1 1513 */ 1514 uint8_t panel_inst; 1515 /** 1516 * Explicit padding to 4 byte boundary. 1517 */ 1518 uint8_t pad[2]; 1519 }; 1520 1521 /** 1522 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1523 */ 1524 struct dmub_rb_cmd_psr_set_version { 1525 /** 1526 * Command header. 1527 */ 1528 struct dmub_cmd_header header; 1529 /** 1530 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1531 */ 1532 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1533 }; 1534 1535 struct dmub_cmd_psr_force_static_data { 1536 /** 1537 * PSR control version. 1538 */ 1539 uint8_t cmd_version; 1540 /** 1541 * Panel Instance. 1542 * Panel isntance to identify which psr_state to use 1543 * Currently the support is only for 0 or 1 1544 */ 1545 uint8_t panel_inst; 1546 /** 1547 * Explicit padding to 4 byte boundary. 1548 */ 1549 uint8_t pad[2]; 1550 }; 1551 1552 /** 1553 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1554 */ 1555 struct dmub_rb_cmd_psr_force_static { 1556 /** 1557 * Command header. 1558 */ 1559 struct dmub_cmd_header header; 1560 /** 1561 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1562 */ 1563 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1564 }; 1565 1566 /** 1567 * Set of HW components that can be locked. 1568 * 1569 * Note: If updating with more HW components, fields 1570 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1571 */ 1572 union dmub_hw_lock_flags { 1573 /** 1574 * Set of HW components that can be locked. 1575 */ 1576 struct { 1577 /** 1578 * Lock/unlock OTG master update lock. 1579 */ 1580 uint8_t lock_pipe : 1; 1581 /** 1582 * Lock/unlock cursor. 1583 */ 1584 uint8_t lock_cursor : 1; 1585 /** 1586 * Lock/unlock global update lock. 1587 */ 1588 uint8_t lock_dig : 1; 1589 /** 1590 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1591 */ 1592 uint8_t triple_buffer_lock : 1; 1593 } bits; 1594 1595 /** 1596 * Union for HW Lock flags. 1597 */ 1598 uint8_t u8All; 1599 }; 1600 1601 /** 1602 * Instances of HW to be locked. 1603 * 1604 * Note: If updating with more HW components, fields 1605 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1606 */ 1607 struct dmub_hw_lock_inst_flags { 1608 /** 1609 * OTG HW instance for OTG master update lock. 1610 */ 1611 uint8_t otg_inst; 1612 /** 1613 * OPP instance for cursor lock. 1614 */ 1615 uint8_t opp_inst; 1616 /** 1617 * OTG HW instance for global update lock. 1618 * TODO: Remove, and re-use otg_inst. 1619 */ 1620 uint8_t dig_inst; 1621 /** 1622 * Explicit pad to 4 byte boundary. 1623 */ 1624 uint8_t pad; 1625 }; 1626 1627 /** 1628 * Clients that can acquire the HW Lock Manager. 1629 * 1630 * Note: If updating with more clients, fields in 1631 * dmub_inbox0_cmd_lock_hw must be updated to match. 1632 */ 1633 enum hw_lock_client { 1634 /** 1635 * Driver is the client of HW Lock Manager. 1636 */ 1637 HW_LOCK_CLIENT_DRIVER = 0, 1638 /** 1639 * Invalid client. 1640 */ 1641 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1642 }; 1643 1644 /** 1645 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1646 */ 1647 struct dmub_cmd_lock_hw_data { 1648 /** 1649 * Specifies the client accessing HW Lock Manager. 1650 */ 1651 enum hw_lock_client client; 1652 /** 1653 * HW instances to be locked. 1654 */ 1655 struct dmub_hw_lock_inst_flags inst_flags; 1656 /** 1657 * Which components to be locked. 1658 */ 1659 union dmub_hw_lock_flags hw_locks; 1660 /** 1661 * Specifies lock/unlock. 1662 */ 1663 uint8_t lock; 1664 /** 1665 * HW can be unlocked separately from releasing the HW Lock Mgr. 1666 * This flag is set if the client wishes to release the object. 1667 */ 1668 uint8_t should_release; 1669 /** 1670 * Explicit padding to 4 byte boundary. 1671 */ 1672 uint8_t pad; 1673 }; 1674 1675 /** 1676 * Definition of a DMUB_CMD__HW_LOCK command. 1677 * Command is used by driver and FW. 1678 */ 1679 struct dmub_rb_cmd_lock_hw { 1680 /** 1681 * Command header. 1682 */ 1683 struct dmub_cmd_header header; 1684 /** 1685 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1686 */ 1687 struct dmub_cmd_lock_hw_data lock_hw_data; 1688 }; 1689 1690 /** 1691 * ABM command sub-types. 1692 */ 1693 enum dmub_cmd_abm_type { 1694 /** 1695 * Initialize parameters for ABM algorithm. 1696 * Data is passed through an indirect buffer. 1697 */ 1698 DMUB_CMD__ABM_INIT_CONFIG = 0, 1699 /** 1700 * Set OTG and panel HW instance. 1701 */ 1702 DMUB_CMD__ABM_SET_PIPE = 1, 1703 /** 1704 * Set user requested backklight level. 1705 */ 1706 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1707 /** 1708 * Set ABM operating/aggression level. 1709 */ 1710 DMUB_CMD__ABM_SET_LEVEL = 3, 1711 /** 1712 * Set ambient light level. 1713 */ 1714 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1715 /** 1716 * Enable/disable fractional duty cycle for backlight PWM. 1717 */ 1718 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1719 }; 1720 1721 /** 1722 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1723 * Requirements: 1724 * - Padded explicitly to 32-bit boundary. 1725 * - Must ensure this structure matches the one on driver-side, 1726 * otherwise it won't be aligned. 1727 */ 1728 struct abm_config_table { 1729 /** 1730 * Gamma curve thresholds, used for crgb conversion. 1731 */ 1732 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1733 /** 1734 * Gamma curve offsets, used for crgb conversion. 1735 */ 1736 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1737 /** 1738 * Gamma curve slopes, used for crgb conversion. 1739 */ 1740 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1741 /** 1742 * Custom backlight curve thresholds. 1743 */ 1744 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1745 /** 1746 * Custom backlight curve offsets. 1747 */ 1748 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1749 /** 1750 * Ambient light thresholds. 1751 */ 1752 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1753 /** 1754 * Minimum programmable backlight. 1755 */ 1756 uint16_t min_abm_backlight; // 122B 1757 /** 1758 * Minimum reduction values. 1759 */ 1760 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1761 /** 1762 * Maximum reduction values. 1763 */ 1764 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1765 /** 1766 * Bright positive gain. 1767 */ 1768 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1769 /** 1770 * Dark negative gain. 1771 */ 1772 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1773 /** 1774 * Hybrid factor. 1775 */ 1776 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1777 /** 1778 * Contrast factor. 1779 */ 1780 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1781 /** 1782 * Deviation gain. 1783 */ 1784 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1785 /** 1786 * Minimum knee. 1787 */ 1788 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1789 /** 1790 * Maximum knee. 1791 */ 1792 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1793 /** 1794 * Unused. 1795 */ 1796 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1797 /** 1798 * Explicit padding to 4 byte boundary. 1799 */ 1800 uint8_t pad3[3]; // 229B 1801 /** 1802 * Backlight ramp reduction. 1803 */ 1804 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1805 /** 1806 * Backlight ramp start. 1807 */ 1808 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1809 }; 1810 1811 /** 1812 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1813 */ 1814 struct dmub_cmd_abm_set_pipe_data { 1815 /** 1816 * OTG HW instance. 1817 */ 1818 uint8_t otg_inst; 1819 1820 /** 1821 * Panel Control HW instance. 1822 */ 1823 uint8_t panel_inst; 1824 1825 /** 1826 * Controls how ABM will interpret a set pipe or set level command. 1827 */ 1828 uint8_t set_pipe_option; 1829 1830 /** 1831 * Unused. 1832 * TODO: Remove. 1833 */ 1834 uint8_t ramping_boundary; 1835 }; 1836 1837 /** 1838 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1839 */ 1840 struct dmub_rb_cmd_abm_set_pipe { 1841 /** 1842 * Command header. 1843 */ 1844 struct dmub_cmd_header header; 1845 1846 /** 1847 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1848 */ 1849 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1850 }; 1851 1852 /** 1853 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1854 */ 1855 struct dmub_cmd_abm_set_backlight_data { 1856 /** 1857 * Number of frames to ramp to backlight user level. 1858 */ 1859 uint32_t frame_ramp; 1860 1861 /** 1862 * Requested backlight level from user. 1863 */ 1864 uint32_t backlight_user_level; 1865 1866 /** 1867 * ABM control version. 1868 */ 1869 uint8_t version; 1870 1871 /** 1872 * Panel Control HW instance mask. 1873 * Bit 0 is Panel Control HW instance 0. 1874 * Bit 1 is Panel Control HW instance 1. 1875 */ 1876 uint8_t panel_mask; 1877 1878 /** 1879 * Explicit padding to 4 byte boundary. 1880 */ 1881 uint8_t pad[2]; 1882 }; 1883 1884 /** 1885 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1886 */ 1887 struct dmub_rb_cmd_abm_set_backlight { 1888 /** 1889 * Command header. 1890 */ 1891 struct dmub_cmd_header header; 1892 1893 /** 1894 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1895 */ 1896 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1897 }; 1898 1899 /** 1900 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1901 */ 1902 struct dmub_cmd_abm_set_level_data { 1903 /** 1904 * Set current ABM operating/aggression level. 1905 */ 1906 uint32_t level; 1907 1908 /** 1909 * ABM control version. 1910 */ 1911 uint8_t version; 1912 1913 /** 1914 * Panel Control HW instance mask. 1915 * Bit 0 is Panel Control HW instance 0. 1916 * Bit 1 is Panel Control HW instance 1. 1917 */ 1918 uint8_t panel_mask; 1919 1920 /** 1921 * Explicit padding to 4 byte boundary. 1922 */ 1923 uint8_t pad[2]; 1924 }; 1925 1926 /** 1927 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1928 */ 1929 struct dmub_rb_cmd_abm_set_level { 1930 /** 1931 * Command header. 1932 */ 1933 struct dmub_cmd_header header; 1934 1935 /** 1936 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1937 */ 1938 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1939 }; 1940 1941 /** 1942 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1943 */ 1944 struct dmub_cmd_abm_set_ambient_level_data { 1945 /** 1946 * Ambient light sensor reading from OS. 1947 */ 1948 uint32_t ambient_lux; 1949 1950 /** 1951 * ABM control version. 1952 */ 1953 uint8_t version; 1954 1955 /** 1956 * Panel Control HW instance mask. 1957 * Bit 0 is Panel Control HW instance 0. 1958 * Bit 1 is Panel Control HW instance 1. 1959 */ 1960 uint8_t panel_mask; 1961 1962 /** 1963 * Explicit padding to 4 byte boundary. 1964 */ 1965 uint8_t pad[2]; 1966 }; 1967 1968 /** 1969 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1970 */ 1971 struct dmub_rb_cmd_abm_set_ambient_level { 1972 /** 1973 * Command header. 1974 */ 1975 struct dmub_cmd_header header; 1976 1977 /** 1978 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1979 */ 1980 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1981 }; 1982 1983 /** 1984 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1985 */ 1986 struct dmub_cmd_abm_set_pwm_frac_data { 1987 /** 1988 * Enable/disable fractional duty cycle for backlight PWM. 1989 * TODO: Convert to uint8_t. 1990 */ 1991 uint32_t fractional_pwm; 1992 1993 /** 1994 * ABM control version. 1995 */ 1996 uint8_t version; 1997 1998 /** 1999 * Panel Control HW instance mask. 2000 * Bit 0 is Panel Control HW instance 0. 2001 * Bit 1 is Panel Control HW instance 1. 2002 */ 2003 uint8_t panel_mask; 2004 2005 /** 2006 * Explicit padding to 4 byte boundary. 2007 */ 2008 uint8_t pad[2]; 2009 }; 2010 2011 /** 2012 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2013 */ 2014 struct dmub_rb_cmd_abm_set_pwm_frac { 2015 /** 2016 * Command header. 2017 */ 2018 struct dmub_cmd_header header; 2019 2020 /** 2021 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2022 */ 2023 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2024 }; 2025 2026 /** 2027 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2028 */ 2029 struct dmub_cmd_abm_init_config_data { 2030 /** 2031 * Location of indirect buffer used to pass init data to ABM. 2032 */ 2033 union dmub_addr src; 2034 2035 /** 2036 * Indirect buffer length. 2037 */ 2038 uint16_t bytes; 2039 2040 2041 /** 2042 * ABM control version. 2043 */ 2044 uint8_t version; 2045 2046 /** 2047 * Panel Control HW instance mask. 2048 * Bit 0 is Panel Control HW instance 0. 2049 * Bit 1 is Panel Control HW instance 1. 2050 */ 2051 uint8_t panel_mask; 2052 2053 /** 2054 * Explicit padding to 4 byte boundary. 2055 */ 2056 uint8_t pad[2]; 2057 }; 2058 2059 /** 2060 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2061 */ 2062 struct dmub_rb_cmd_abm_init_config { 2063 /** 2064 * Command header. 2065 */ 2066 struct dmub_cmd_header header; 2067 2068 /** 2069 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2070 */ 2071 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2072 }; 2073 2074 /** 2075 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2076 */ 2077 struct dmub_cmd_query_feature_caps_data { 2078 /** 2079 * DMUB feature capabilities. 2080 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2081 */ 2082 struct dmub_feature_caps feature_caps; 2083 }; 2084 2085 /** 2086 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2087 */ 2088 struct dmub_rb_cmd_query_feature_caps { 2089 /** 2090 * Command header. 2091 */ 2092 struct dmub_cmd_header header; 2093 /** 2094 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2095 */ 2096 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2097 }; 2098 2099 struct dmub_optc_state { 2100 uint32_t v_total_max; 2101 uint32_t v_total_min; 2102 uint32_t v_total_mid; 2103 uint32_t v_total_mid_frame_num; 2104 uint32_t tg_inst; 2105 uint32_t enable_manual_trigger; 2106 uint32_t clear_force_vsync; 2107 }; 2108 2109 struct dmub_rb_cmd_drr_update { 2110 struct dmub_cmd_header header; 2111 struct dmub_optc_state dmub_optc_state_req; 2112 }; 2113 2114 /** 2115 * enum dmub_cmd_panel_cntl_type - Panel control command. 2116 */ 2117 enum dmub_cmd_panel_cntl_type { 2118 /** 2119 * Initializes embedded panel hardware blocks. 2120 */ 2121 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2122 /** 2123 * Queries backlight info for the embedded panel. 2124 */ 2125 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2126 }; 2127 2128 /** 2129 * struct dmub_cmd_panel_cntl_data - Panel control data. 2130 */ 2131 struct dmub_cmd_panel_cntl_data { 2132 uint32_t inst; /**< panel instance */ 2133 uint32_t current_backlight; /* in/out */ 2134 uint32_t bl_pwm_cntl; /* in/out */ 2135 uint32_t bl_pwm_period_cntl; /* in/out */ 2136 uint32_t bl_pwm_ref_div1; /* in/out */ 2137 uint8_t is_backlight_on : 1; /* in/out */ 2138 uint8_t is_powered_on : 1; /* in/out */ 2139 }; 2140 2141 /** 2142 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2143 */ 2144 struct dmub_rb_cmd_panel_cntl { 2145 struct dmub_cmd_header header; /**< header */ 2146 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2147 }; 2148 2149 /** 2150 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2151 */ 2152 struct dmub_cmd_lvtma_control_data { 2153 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2154 uint8_t reserved_0[3]; /**< For future use */ 2155 uint8_t panel_inst; /**< LVTMA control instance */ 2156 uint8_t reserved_1[3]; /**< For future use */ 2157 }; 2158 2159 /** 2160 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2161 */ 2162 struct dmub_rb_cmd_lvtma_control { 2163 /** 2164 * Command header. 2165 */ 2166 struct dmub_cmd_header header; 2167 /** 2168 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2169 */ 2170 struct dmub_cmd_lvtma_control_data data; 2171 }; 2172 2173 /** 2174 * Maximum number of bytes a chunk sent to DMUB for parsing 2175 */ 2176 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2177 2178 /** 2179 * Represent a chunk of CEA blocks sent to DMUB for parsing 2180 */ 2181 struct dmub_cmd_send_edid_cea { 2182 uint16_t offset; /**< offset into the CEA block */ 2183 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2184 uint16_t total_length; /**< total length of the CEA block */ 2185 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2186 uint8_t pad[3]; /**< padding and for future expansion */ 2187 }; 2188 2189 /** 2190 * Result of VSDB parsing from CEA block 2191 */ 2192 struct dmub_cmd_edid_cea_amd_vsdb { 2193 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2194 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2195 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2196 uint16_t min_frame_rate; /**< Maximum frame rate */ 2197 uint16_t max_frame_rate; /**< Minimum frame rate */ 2198 }; 2199 2200 /** 2201 * Result of sending a CEA chunk 2202 */ 2203 struct dmub_cmd_edid_cea_ack { 2204 uint16_t offset; /**< offset of the chunk into the CEA block */ 2205 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2206 uint8_t pad; /**< padding and for future expansion */ 2207 }; 2208 2209 /** 2210 * Specify whether the result is an ACK/NACK or the parsing has finished 2211 */ 2212 enum dmub_cmd_edid_cea_reply_type { 2213 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2214 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2215 }; 2216 2217 /** 2218 * Definition of a DMUB_CMD__EDID_CEA command. 2219 */ 2220 struct dmub_rb_cmd_edid_cea { 2221 struct dmub_cmd_header header; /**< Command header */ 2222 union dmub_cmd_edid_cea_data { 2223 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2224 struct dmub_cmd_edid_cea_output { /**< output with results */ 2225 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2226 union { 2227 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2228 struct dmub_cmd_edid_cea_ack ack; 2229 }; 2230 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2231 } data; /**< Command data */ 2232 2233 }; 2234 2235 /** 2236 * union dmub_rb_cmd - DMUB inbox command. 2237 */ 2238 union dmub_rb_cmd { 2239 struct dmub_rb_cmd_lock_hw lock_hw; 2240 /** 2241 * Elements shared with all commands. 2242 */ 2243 struct dmub_rb_cmd_common cmd_common; 2244 /** 2245 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2246 */ 2247 struct dmub_rb_cmd_read_modify_write read_modify_write; 2248 /** 2249 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2250 */ 2251 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2252 /** 2253 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2254 */ 2255 struct dmub_rb_cmd_burst_write burst_write; 2256 /** 2257 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2258 */ 2259 struct dmub_rb_cmd_reg_wait reg_wait; 2260 /** 2261 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2262 */ 2263 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2264 /** 2265 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2266 */ 2267 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2268 /** 2269 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2270 */ 2271 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2272 /** 2273 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2274 */ 2275 struct dmub_rb_cmd_dpphy_init dpphy_init; 2276 /** 2277 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2278 */ 2279 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2280 /** 2281 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2282 */ 2283 struct dmub_rb_cmd_psr_set_version psr_set_version; 2284 /** 2285 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2286 */ 2287 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2288 /** 2289 * Definition of a DMUB_CMD__PSR_ENABLE command. 2290 */ 2291 struct dmub_rb_cmd_psr_enable psr_enable; 2292 /** 2293 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2294 */ 2295 struct dmub_rb_cmd_psr_set_level psr_set_level; 2296 /** 2297 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2298 */ 2299 struct dmub_rb_cmd_psr_force_static psr_force_static; 2300 /** 2301 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2302 */ 2303 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2304 /** 2305 * Definition of a DMUB_CMD__MALL command. 2306 */ 2307 struct dmub_rb_cmd_mall mall; 2308 /** 2309 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2310 */ 2311 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2312 2313 /** 2314 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2315 */ 2316 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2317 2318 /** 2319 * Definition of DMUB_CMD__PANEL_CNTL commands. 2320 */ 2321 struct dmub_rb_cmd_panel_cntl panel_cntl; 2322 /** 2323 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2324 */ 2325 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2326 2327 /** 2328 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2329 */ 2330 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2331 2332 /** 2333 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2334 */ 2335 struct dmub_rb_cmd_abm_set_level abm_set_level; 2336 2337 /** 2338 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2339 */ 2340 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2341 2342 /** 2343 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2344 */ 2345 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2346 2347 /** 2348 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2349 */ 2350 struct dmub_rb_cmd_abm_init_config abm_init_config; 2351 2352 /** 2353 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2354 */ 2355 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2356 2357 /** 2358 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2359 */ 2360 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2361 2362 /** 2363 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2364 */ 2365 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2366 struct dmub_rb_cmd_drr_update drr_update; 2367 /** 2368 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2369 */ 2370 struct dmub_rb_cmd_lvtma_control lvtma_control; 2371 /** 2372 * Definition of a DMUB_CMD__EDID_CEA command. 2373 */ 2374 struct dmub_rb_cmd_edid_cea edid_cea; 2375 }; 2376 2377 /** 2378 * union dmub_rb_out_cmd - Outbox command 2379 */ 2380 union dmub_rb_out_cmd { 2381 /** 2382 * Parameters common to every command. 2383 */ 2384 struct dmub_rb_cmd_common cmd_common; 2385 /** 2386 * AUX reply command. 2387 */ 2388 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2389 /** 2390 * HPD notify command. 2391 */ 2392 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2393 }; 2394 #pragma pack(pop) 2395 2396 2397 //============================================================================== 2398 //</DMUB_CMD>=================================================================== 2399 //============================================================================== 2400 //< DMUB_RB>==================================================================== 2401 //============================================================================== 2402 2403 #if defined(__cplusplus) 2404 extern "C" { 2405 #endif 2406 2407 /** 2408 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2409 */ 2410 struct dmub_rb_init_params { 2411 void *ctx; /**< Caller provided context pointer */ 2412 void *base_address; /**< CPU base address for ring's data */ 2413 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2414 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2415 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2416 }; 2417 2418 /** 2419 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2420 */ 2421 struct dmub_rb { 2422 void *base_address; /**< CPU address for the ring's data */ 2423 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2424 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2425 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2426 2427 void *ctx; /**< Caller provided context pointer */ 2428 void *dmub; /**< Pointer to the DMUB interface */ 2429 }; 2430 2431 /** 2432 * @brief Checks if the ringbuffer is empty. 2433 * 2434 * @param rb DMUB Ringbuffer 2435 * @return true if empty 2436 * @return false otherwise 2437 */ 2438 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2439 { 2440 return (rb->wrpt == rb->rptr); 2441 } 2442 2443 /** 2444 * @brief Checks if the ringbuffer is full 2445 * 2446 * @param rb DMUB Ringbuffer 2447 * @return true if full 2448 * @return false otherwise 2449 */ 2450 static inline bool dmub_rb_full(struct dmub_rb *rb) 2451 { 2452 uint32_t data_count; 2453 2454 if (rb->wrpt >= rb->rptr) 2455 data_count = rb->wrpt - rb->rptr; 2456 else 2457 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2458 2459 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2460 } 2461 2462 /** 2463 * @brief Pushes a command into the ringbuffer 2464 * 2465 * @param rb DMUB ringbuffer 2466 * @param cmd The command to push 2467 * @return true if the ringbuffer was not full 2468 * @return false otherwise 2469 */ 2470 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2471 const union dmub_rb_cmd *cmd) 2472 { 2473 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2474 const uint8_t *src = (const uint8_t *)cmd; 2475 2476 if (dmub_rb_full(rb)) 2477 return false; 2478 2479 // copying data 2480 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2481 2482 rb->wrpt += DMUB_RB_CMD_SIZE; 2483 2484 if (rb->wrpt >= rb->capacity) 2485 rb->wrpt %= rb->capacity; 2486 2487 return true; 2488 } 2489 2490 /** 2491 * @brief Pushes a command into the DMUB outbox ringbuffer 2492 * 2493 * @param rb DMUB outbox ringbuffer 2494 * @param cmd Outbox command 2495 * @return true if not full 2496 * @return false otherwise 2497 */ 2498 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2499 const union dmub_rb_out_cmd *cmd) 2500 { 2501 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2502 const uint8_t *src = (const uint8_t *)cmd; 2503 2504 if (dmub_rb_full(rb)) 2505 return false; 2506 2507 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2508 2509 rb->wrpt += DMUB_RB_CMD_SIZE; 2510 2511 if (rb->wrpt >= rb->capacity) 2512 rb->wrpt %= rb->capacity; 2513 2514 return true; 2515 } 2516 2517 /** 2518 * @brief Returns the next unprocessed command in the ringbuffer. 2519 * 2520 * @param rb DMUB ringbuffer 2521 * @param cmd The command to return 2522 * @return true if not empty 2523 * @return false otherwise 2524 */ 2525 static inline bool dmub_rb_front(struct dmub_rb *rb, 2526 union dmub_rb_cmd **cmd) 2527 { 2528 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2529 2530 if (dmub_rb_empty(rb)) 2531 return false; 2532 2533 *cmd = (union dmub_rb_cmd *)rb_cmd; 2534 2535 return true; 2536 } 2537 2538 /** 2539 * @brief Determines the next ringbuffer offset. 2540 * 2541 * @param rb DMUB inbox ringbuffer 2542 * @param num_cmds Number of commands 2543 * @param next_rptr The next offset in the ringbuffer 2544 */ 2545 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2546 uint32_t num_cmds, 2547 uint32_t *next_rptr) 2548 { 2549 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2550 2551 if (*next_rptr >= rb->capacity) 2552 *next_rptr %= rb->capacity; 2553 } 2554 2555 /** 2556 * @brief Returns a pointer to a command in the inbox. 2557 * 2558 * @param rb DMUB inbox ringbuffer 2559 * @param cmd The inbox command to return 2560 * @param rptr The ringbuffer offset 2561 * @return true if not empty 2562 * @return false otherwise 2563 */ 2564 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2565 union dmub_rb_cmd **cmd, 2566 uint32_t rptr) 2567 { 2568 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2569 2570 if (dmub_rb_empty(rb)) 2571 return false; 2572 2573 *cmd = (union dmub_rb_cmd *)rb_cmd; 2574 2575 return true; 2576 } 2577 2578 /** 2579 * @brief Returns the next unprocessed command in the outbox. 2580 * 2581 * @param rb DMUB outbox ringbuffer 2582 * @param cmd The outbox command to return 2583 * @return true if not empty 2584 * @return false otherwise 2585 */ 2586 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2587 union dmub_rb_out_cmd *cmd) 2588 { 2589 const uint8_t *src = (const uint8_t *)(rb->base_address) + rb->rptr; 2590 uint8_t *dst = (uint8_t *)cmd; 2591 2592 if (dmub_rb_empty(rb)) 2593 return false; 2594 2595 // copying data 2596 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2597 2598 return true; 2599 } 2600 2601 /** 2602 * @brief Removes the front entry in the ringbuffer. 2603 * 2604 * @param rb DMUB ringbuffer 2605 * @return true if the command was removed 2606 * @return false if there were no commands 2607 */ 2608 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2609 { 2610 if (dmub_rb_empty(rb)) 2611 return false; 2612 2613 rb->rptr += DMUB_RB_CMD_SIZE; 2614 2615 if (rb->rptr >= rb->capacity) 2616 rb->rptr %= rb->capacity; 2617 2618 return true; 2619 } 2620 2621 /** 2622 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2623 * 2624 * Avoids a race condition where DMCUB accesses memory while 2625 * there are still writes in flight to framebuffer. 2626 * 2627 * @param rb DMUB ringbuffer 2628 */ 2629 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2630 { 2631 uint8_t buf[DMUB_RB_CMD_SIZE]; 2632 uint32_t rptr = rb->rptr; 2633 uint32_t wptr = rb->wrpt; 2634 2635 while (rptr != wptr) { 2636 const uint8_t *data = (const uint8_t *)rb->base_address + rptr; 2637 2638 dmub_memcpy(buf, data, DMUB_RB_CMD_SIZE); 2639 2640 rptr += DMUB_RB_CMD_SIZE; 2641 if (rptr >= rb->capacity) 2642 rptr %= rb->capacity; 2643 } 2644 } 2645 2646 /** 2647 * @brief Initializes a DMCUB ringbuffer 2648 * 2649 * @param rb DMUB ringbuffer 2650 * @param init_params initial configuration for the ringbuffer 2651 */ 2652 static inline void dmub_rb_init(struct dmub_rb *rb, 2653 struct dmub_rb_init_params *init_params) 2654 { 2655 rb->base_address = init_params->base_address; 2656 rb->capacity = init_params->capacity; 2657 rb->rptr = init_params->read_ptr; 2658 rb->wrpt = init_params->write_ptr; 2659 } 2660 2661 /** 2662 * @brief Copies output data from in/out commands into the given command. 2663 * 2664 * @param rb DMUB ringbuffer 2665 * @param cmd Command to copy data into 2666 */ 2667 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2668 union dmub_rb_cmd *cmd) 2669 { 2670 // Copy rb entry back into command 2671 uint8_t *rd_ptr = (rb->rptr == 0) ? 2672 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2673 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2674 2675 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2676 } 2677 2678 #if defined(__cplusplus) 2679 } 2680 #endif 2681 2682 //============================================================================== 2683 //</DMUB_RB>==================================================================== 2684 //============================================================================== 2685 2686 #endif /* _DMUB_CMD_H_ */ 2687