1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of streams on any ASIC. */ 96 #define DMUB_MAX_STREAMS 6 97 98 /* Maximum number of planes on any ASIC. */ 99 #define DMUB_MAX_PLANES 6 100 101 /* Trace buffer offset for entry */ 102 #define TRACE_BUFFER_ENTRY_OFFSET 16 103 104 /** 105 * 106 * PSR control version legacy 107 */ 108 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 109 /** 110 * PSR control version with multi edp support 111 */ 112 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 113 114 115 /** 116 * ABM control version legacy 117 */ 118 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 119 120 /** 121 * ABM control version with multi edp support 122 */ 123 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 124 125 /** 126 * Physical framebuffer address location, 64-bit. 127 */ 128 #ifndef PHYSICAL_ADDRESS_LOC 129 #define PHYSICAL_ADDRESS_LOC union large_integer 130 #endif 131 132 /** 133 * OS/FW agnostic memcpy 134 */ 135 #ifndef dmub_memcpy 136 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 137 #endif 138 139 /** 140 * OS/FW agnostic memset 141 */ 142 #ifndef dmub_memset 143 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 144 #endif 145 146 #if defined(__cplusplus) 147 extern "C" { 148 #endif 149 150 /** 151 * OS/FW agnostic udelay 152 */ 153 #ifndef dmub_udelay 154 #define dmub_udelay(microseconds) udelay(microseconds) 155 #endif 156 157 /** 158 * union dmub_addr - DMUB physical/virtual 64-bit address. 159 */ 160 union dmub_addr { 161 struct { 162 uint32_t low_part; /**< Lower 32 bits */ 163 uint32_t high_part; /**< Upper 32 bits */ 164 } u; /*<< Low/high bit access */ 165 uint64_t quad_part; /*<< 64 bit address */ 166 }; 167 168 /** 169 * Flags that can be set by driver to change some PSR behaviour. 170 */ 171 union dmub_psr_debug_flags { 172 /** 173 * Debug flags. 174 */ 175 struct { 176 /** 177 * Enable visual confirm in FW. 178 */ 179 uint32_t visual_confirm : 1; 180 /** 181 * Use HW Lock Mgr object to do HW locking in FW. 182 */ 183 uint32_t use_hw_lock_mgr : 1; 184 185 /** 186 * Use TPS3 signal when restore main link. 187 */ 188 uint32_t force_wakeup_by_tps3 : 1; 189 } bitfields; 190 191 /** 192 * Union for debug flags. 193 */ 194 uint32_t u32All; 195 }; 196 197 /** 198 * DMUB feature capabilities. 199 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 200 */ 201 struct dmub_feature_caps { 202 /** 203 * Max PSR version supported by FW. 204 */ 205 uint8_t psr; 206 uint8_t reserved[7]; 207 }; 208 209 #if defined(__cplusplus) 210 } 211 #endif 212 213 //============================================================================== 214 //</DMUB_TYPES>================================================================= 215 //============================================================================== 216 //< DMUB_META>================================================================== 217 //============================================================================== 218 #pragma pack(push, 1) 219 220 /* Magic value for identifying dmub_fw_meta_info */ 221 #define DMUB_FW_META_MAGIC 0x444D5542 222 223 /* Offset from the end of the file to the dmub_fw_meta_info */ 224 #define DMUB_FW_META_OFFSET 0x24 225 226 /** 227 * struct dmub_fw_meta_info - metadata associated with fw binary 228 * 229 * NOTE: This should be considered a stable API. Fields should 230 * not be repurposed or reordered. New fields should be 231 * added instead to extend the structure. 232 * 233 * @magic_value: magic value identifying DMUB firmware meta info 234 * @fw_region_size: size of the firmware state region 235 * @trace_buffer_size: size of the tracebuffer region 236 * @fw_version: the firmware version information 237 * @dal_fw: 1 if the firmware is DAL 238 */ 239 struct dmub_fw_meta_info { 240 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 241 uint32_t fw_region_size; /**< size of the firmware state region */ 242 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 243 uint32_t fw_version; /**< the firmware version information */ 244 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 245 uint8_t reserved[3]; /**< padding bits */ 246 }; 247 248 /** 249 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 250 */ 251 union dmub_fw_meta { 252 struct dmub_fw_meta_info info; /**< metadata info */ 253 uint8_t reserved[64]; /**< padding bits */ 254 }; 255 256 #pragma pack(pop) 257 258 //============================================================================== 259 //< DMUB Trace Buffer>================================================================ 260 //============================================================================== 261 /** 262 * dmub_trace_code_t - firmware trace code, 32-bits 263 */ 264 typedef uint32_t dmub_trace_code_t; 265 266 /** 267 * struct dmcub_trace_buf_entry - Firmware trace entry 268 */ 269 struct dmcub_trace_buf_entry { 270 dmub_trace_code_t trace_code; /**< trace code for the event */ 271 uint32_t tick_count; /**< the tick count at time of trace */ 272 uint32_t param0; /**< trace defined parameter 0 */ 273 uint32_t param1; /**< trace defined parameter 1 */ 274 }; 275 276 //============================================================================== 277 //< DMUB_STATUS>================================================================ 278 //============================================================================== 279 280 /** 281 * DMCUB scratch registers can be used to determine firmware status. 282 * Current scratch register usage is as follows: 283 * 284 * SCRATCH0: FW Boot Status register 285 * SCRATCH5: LVTMA Status Register 286 * SCRATCH15: FW Boot Options register 287 */ 288 289 /** 290 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 291 */ 292 union dmub_fw_boot_status { 293 struct { 294 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 295 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 296 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 297 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 298 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 299 uint32_t reserved : 1; 300 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 301 302 } bits; /**< status bits */ 303 uint32_t all; /**< 32-bit access to status bits */ 304 }; 305 306 /** 307 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 308 */ 309 enum dmub_fw_boot_status_bit { 310 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 311 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 312 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 313 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 314 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 315 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 316 }; 317 318 /* Register bit definition for SCRATCH5 */ 319 union dmub_lvtma_status { 320 struct { 321 uint32_t psp_ok : 1; 322 uint32_t edp_on : 1; 323 uint32_t reserved : 30; 324 } bits; 325 uint32_t all; 326 }; 327 328 enum dmub_lvtma_status_bit { 329 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 330 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 331 }; 332 333 /** 334 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 335 */ 336 union dmub_fw_boot_options { 337 struct { 338 uint32_t pemu_env : 1; /**< 1 if PEMU */ 339 uint32_t fpga_env : 1; /**< 1 if FPGA */ 340 uint32_t optimized_init : 1; /**< 1 if optimized init */ 341 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 342 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 343 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 344 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 345 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 346 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 347 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 348 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 349 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 350 uint32_t power_optimization: 1; 351 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 352 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 353 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 354 355 uint32_t reserved : 17; /**< reserved */ 356 } bits; /**< boot bits */ 357 uint32_t all; /**< 32-bit access to bits */ 358 }; 359 360 enum dmub_fw_boot_options_bit { 361 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 362 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 363 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 364 }; 365 366 //============================================================================== 367 //</DMUB_STATUS>================================================================ 368 //============================================================================== 369 //< DMUB_VBIOS>================================================================= 370 //============================================================================== 371 372 /* 373 * enum dmub_cmd_vbios_type - VBIOS commands. 374 * 375 * Command IDs should be treated as stable ABI. 376 * Do not reuse or modify IDs. 377 */ 378 enum dmub_cmd_vbios_type { 379 /** 380 * Configures the DIG encoder. 381 */ 382 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 383 /** 384 * Controls the PHY. 385 */ 386 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 387 /** 388 * Sets the pixel clock/symbol clock. 389 */ 390 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 391 /** 392 * Enables or disables power gating. 393 */ 394 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 395 /** 396 * Controls embedded panels. 397 */ 398 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 399 /** 400 * Query DP alt status on a transmitter. 401 */ 402 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 403 }; 404 405 //============================================================================== 406 //</DMUB_VBIOS>================================================================= 407 //============================================================================== 408 //< DMUB_GPINT>================================================================= 409 //============================================================================== 410 411 /** 412 * The shifts and masks below may alternatively be used to format and read 413 * the command register bits. 414 */ 415 416 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 417 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 418 419 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 420 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 421 422 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 423 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 424 425 /** 426 * Command responses. 427 */ 428 429 /** 430 * Return response for DMUB_GPINT__STOP_FW command. 431 */ 432 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 433 434 /** 435 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 436 */ 437 union dmub_gpint_data_register { 438 struct { 439 uint32_t param : 16; /**< 16-bit parameter */ 440 uint32_t command_code : 12; /**< GPINT command */ 441 uint32_t status : 4; /**< Command status bit */ 442 } bits; /**< GPINT bit access */ 443 uint32_t all; /**< GPINT 32-bit access */ 444 }; 445 446 /* 447 * enum dmub_gpint_command - GPINT command to DMCUB FW 448 * 449 * Command IDs should be treated as stable ABI. 450 * Do not reuse or modify IDs. 451 */ 452 enum dmub_gpint_command { 453 /** 454 * Invalid command, ignored. 455 */ 456 DMUB_GPINT__INVALID_COMMAND = 0, 457 /** 458 * DESC: Queries the firmware version. 459 * RETURN: Firmware version. 460 */ 461 DMUB_GPINT__GET_FW_VERSION = 1, 462 /** 463 * DESC: Halts the firmware. 464 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 465 */ 466 DMUB_GPINT__STOP_FW = 2, 467 /** 468 * DESC: Get PSR state from FW. 469 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 470 */ 471 DMUB_GPINT__GET_PSR_STATE = 7, 472 /** 473 * DESC: Notifies DMCUB of the currently active streams. 474 * ARGS: Stream mask, 1 bit per active stream index. 475 */ 476 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 477 /** 478 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 479 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 480 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 481 * RETURN: PSR residency in milli-percent. 482 */ 483 DMUB_GPINT__PSR_RESIDENCY = 9, 484 485 /** 486 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 487 */ 488 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 489 }; 490 491 /** 492 * INBOX0 generic command definition 493 */ 494 union dmub_inbox0_cmd_common { 495 struct { 496 uint32_t command_code: 8; /**< INBOX0 command code */ 497 uint32_t param: 24; /**< 24-bit parameter */ 498 } bits; 499 uint32_t all; 500 }; 501 502 /** 503 * INBOX0 hw_lock command definition 504 */ 505 union dmub_inbox0_cmd_lock_hw { 506 struct { 507 uint32_t command_code: 8; 508 509 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 510 uint32_t hw_lock_client: 2; 511 512 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 513 uint32_t otg_inst: 3; 514 uint32_t opp_inst: 3; 515 uint32_t dig_inst: 3; 516 517 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 518 uint32_t lock_pipe: 1; 519 uint32_t lock_cursor: 1; 520 uint32_t lock_dig: 1; 521 uint32_t triple_buffer_lock: 1; 522 523 uint32_t lock: 1; /**< Lock */ 524 uint32_t should_release: 1; /**< Release */ 525 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 526 } bits; 527 uint32_t all; 528 }; 529 530 union dmub_inbox0_data_register { 531 union dmub_inbox0_cmd_common inbox0_cmd_common; 532 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 533 }; 534 535 enum dmub_inbox0_command { 536 /** 537 * DESC: Invalid command, ignored. 538 */ 539 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 540 /** 541 * DESC: Notification to acquire/release HW lock 542 * ARGS: 543 */ 544 DMUB_INBOX0_CMD__HW_LOCK = 1, 545 }; 546 //============================================================================== 547 //</DMUB_GPINT>================================================================= 548 //============================================================================== 549 //< DMUB_CMD>=================================================================== 550 //============================================================================== 551 552 /** 553 * Size in bytes of each DMUB command. 554 */ 555 #define DMUB_RB_CMD_SIZE 64 556 557 /** 558 * Maximum number of items in the DMUB ringbuffer. 559 */ 560 #define DMUB_RB_MAX_ENTRY 128 561 562 /** 563 * Ringbuffer size in bytes. 564 */ 565 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 566 567 /** 568 * REG_SET mask for reg offload. 569 */ 570 #define REG_SET_MASK 0xFFFF 571 572 /* 573 * enum dmub_cmd_type - DMUB inbox command. 574 * 575 * Command IDs should be treated as stable ABI. 576 * Do not reuse or modify IDs. 577 */ 578 enum dmub_cmd_type { 579 /** 580 * Invalid command. 581 */ 582 DMUB_CMD__NULL = 0, 583 /** 584 * Read modify write register sequence offload. 585 */ 586 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 587 /** 588 * Field update register sequence offload. 589 */ 590 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 591 /** 592 * Burst write sequence offload. 593 */ 594 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 595 /** 596 * Reg wait sequence offload. 597 */ 598 DMUB_CMD__REG_REG_WAIT = 4, 599 /** 600 * Workaround to avoid HUBP underflow during NV12 playback. 601 */ 602 DMUB_CMD__PLAT_54186_WA = 5, 603 /** 604 * Command type used to query FW feature caps. 605 */ 606 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 607 /** 608 * Command type used for all PSR commands. 609 */ 610 DMUB_CMD__PSR = 64, 611 /** 612 * Command type used for all MALL commands. 613 */ 614 DMUB_CMD__MALL = 65, 615 /** 616 * Command type used for all ABM commands. 617 */ 618 DMUB_CMD__ABM = 66, 619 /** 620 * Command type used for HW locking in FW. 621 */ 622 DMUB_CMD__HW_LOCK = 69, 623 /** 624 * Command type used to access DP AUX. 625 */ 626 DMUB_CMD__DP_AUX_ACCESS = 70, 627 /** 628 * Command type used for OUTBOX1 notification enable 629 */ 630 DMUB_CMD__OUTBOX1_ENABLE = 71, 631 632 /** 633 * Command type used for all idle optimization commands. 634 */ 635 DMUB_CMD__IDLE_OPT = 72, 636 /** 637 * Command type used for all clock manager commands. 638 */ 639 DMUB_CMD__CLK_MGR = 73, 640 /** 641 * Command type used for all panel control commands. 642 */ 643 DMUB_CMD__PANEL_CNTL = 74, 644 /** 645 * Command type used for <TODO:description> 646 */ 647 DMUB_CMD__CAB_FOR_SS = 75, 648 /** 649 * Command type used for interfacing with DPIA. 650 */ 651 DMUB_CMD__DPIA = 77, 652 /** 653 * Command type used for EDID CEA parsing 654 */ 655 DMUB_CMD__EDID_CEA = 79, 656 /** 657 * Command type used for getting usbc cable ID 658 */ 659 DMUB_CMD_GET_USBC_CABLE_ID = 81, 660 /** 661 * Command type used to query HPD state. 662 */ 663 DMUB_CMD__QUERY_HPD_STATE = 82, 664 /** 665 * Command type used for all VBIOS interface commands. 666 */ 667 DMUB_CMD__VBIOS = 128, 668 }; 669 670 /** 671 * enum dmub_out_cmd_type - DMUB outbox commands. 672 */ 673 enum dmub_out_cmd_type { 674 /** 675 * Invalid outbox command, ignored. 676 */ 677 DMUB_OUT_CMD__NULL = 0, 678 /** 679 * Command type used for DP AUX Reply data notification 680 */ 681 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 682 /** 683 * Command type used for DP HPD event notification 684 */ 685 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 686 /** 687 * Command type used for SET_CONFIG Reply notification 688 */ 689 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 690 }; 691 692 /* DMUB_CMD__DPIA command sub-types. */ 693 enum dmub_cmd_dpia_type { 694 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 695 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 696 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 697 }; 698 699 #pragma pack(push, 1) 700 701 /** 702 * struct dmub_cmd_header - Common command header fields. 703 */ 704 struct dmub_cmd_header { 705 unsigned int type : 8; /**< command type */ 706 unsigned int sub_type : 8; /**< command sub type */ 707 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 708 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 709 unsigned int reserved0 : 6; /**< reserved bits */ 710 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 711 unsigned int reserved1 : 2; /**< reserved bits */ 712 }; 713 714 /* 715 * struct dmub_cmd_read_modify_write_sequence - Read modify write 716 * 717 * 60 payload bytes can hold up to 5 sets of read modify writes, 718 * each take 3 dwords. 719 * 720 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 721 * 722 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 723 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 724 */ 725 struct dmub_cmd_read_modify_write_sequence { 726 uint32_t addr; /**< register address */ 727 uint32_t modify_mask; /**< modify mask */ 728 uint32_t modify_value; /**< modify value */ 729 }; 730 731 /** 732 * Maximum number of ops in read modify write sequence. 733 */ 734 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 735 736 /** 737 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 738 */ 739 struct dmub_rb_cmd_read_modify_write { 740 struct dmub_cmd_header header; /**< command header */ 741 /** 742 * Read modify write sequence. 743 */ 744 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 745 }; 746 747 /* 748 * Update a register with specified masks and values sequeunce 749 * 750 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 751 * 752 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 753 * 754 * 755 * USE CASE: 756 * 1. auto-increment register where additional read would update pointer and produce wrong result 757 * 2. toggle a bit without read in the middle 758 */ 759 760 struct dmub_cmd_reg_field_update_sequence { 761 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 762 uint32_t modify_value; /**< value to update with */ 763 }; 764 765 /** 766 * Maximum number of ops in field update sequence. 767 */ 768 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 769 770 /** 771 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 772 */ 773 struct dmub_rb_cmd_reg_field_update_sequence { 774 struct dmub_cmd_header header; /**< command header */ 775 uint32_t addr; /**< register address */ 776 /** 777 * Field update sequence. 778 */ 779 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 780 }; 781 782 783 /** 784 * Maximum number of burst write values. 785 */ 786 #define DMUB_BURST_WRITE_VALUES__MAX 14 787 788 /* 789 * struct dmub_rb_cmd_burst_write - Burst write 790 * 791 * support use case such as writing out LUTs. 792 * 793 * 60 payload bytes can hold up to 14 values to write to given address 794 * 795 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 796 */ 797 struct dmub_rb_cmd_burst_write { 798 struct dmub_cmd_header header; /**< command header */ 799 uint32_t addr; /**< register start address */ 800 /** 801 * Burst write register values. 802 */ 803 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 804 }; 805 806 /** 807 * struct dmub_rb_cmd_common - Common command header 808 */ 809 struct dmub_rb_cmd_common { 810 struct dmub_cmd_header header; /**< command header */ 811 /** 812 * Padding to RB_CMD_SIZE 813 */ 814 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 815 }; 816 817 /** 818 * struct dmub_cmd_reg_wait_data - Register wait data 819 */ 820 struct dmub_cmd_reg_wait_data { 821 uint32_t addr; /**< Register address */ 822 uint32_t mask; /**< Mask for register bits */ 823 uint32_t condition_field_value; /**< Value to wait for */ 824 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 825 }; 826 827 /** 828 * struct dmub_rb_cmd_reg_wait - Register wait command 829 */ 830 struct dmub_rb_cmd_reg_wait { 831 struct dmub_cmd_header header; /**< Command header */ 832 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 833 }; 834 835 /** 836 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 837 * 838 * Reprograms surface parameters to avoid underflow. 839 */ 840 struct dmub_cmd_PLAT_54186_wa { 841 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 842 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 843 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 844 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 845 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 846 struct { 847 uint8_t hubp_inst : 4; /**< HUBP instance */ 848 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 849 uint8_t immediate :1; /**< Immediate flip */ 850 uint8_t vmid : 4; /**< VMID */ 851 uint8_t grph_stereo : 1; /**< 1 if stereo */ 852 uint32_t reserved : 21; /**< Reserved */ 853 } flip_params; /**< Pageflip parameters */ 854 uint32_t reserved[9]; /**< Reserved bits */ 855 }; 856 857 /** 858 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 859 */ 860 struct dmub_rb_cmd_PLAT_54186_wa { 861 struct dmub_cmd_header header; /**< Command header */ 862 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 863 }; 864 865 /** 866 * struct dmub_rb_cmd_mall - MALL command data. 867 */ 868 struct dmub_rb_cmd_mall { 869 struct dmub_cmd_header header; /**< Common command header */ 870 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 871 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 872 uint32_t tmr_delay; /**< Timer delay */ 873 uint32_t tmr_scale; /**< Timer scale */ 874 uint16_t cursor_width; /**< Cursor width in pixels */ 875 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 876 uint16_t cursor_height; /**< Cursor height in pixels */ 877 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 878 uint8_t debug_bits; /**< Debug bits */ 879 880 uint8_t reserved1; /**< Reserved bits */ 881 uint8_t reserved2; /**< Reserved bits */ 882 }; 883 884 /** 885 * enum dmub_cmd_cab_type - TODO: 886 */ 887 enum dmub_cmd_cab_type { 888 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 889 DMUB_CMD__CAB_NO_DCN_REQ = 1, 890 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 891 }; 892 893 /** 894 * struct dmub_rb_cmd_cab_for_ss - TODO: 895 */ 896 struct dmub_rb_cmd_cab_for_ss { 897 struct dmub_cmd_header header; 898 uint8_t cab_alloc_ways; /* total number of ways */ 899 uint8_t debug_bits; /* debug bits */ 900 }; 901 /** 902 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 903 */ 904 enum dmub_cmd_idle_opt_type { 905 /** 906 * DCN hardware restore. 907 */ 908 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 909 910 /** 911 * DCN hardware save. 912 */ 913 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 914 }; 915 916 /** 917 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 918 */ 919 struct dmub_rb_cmd_idle_opt_dcn_restore { 920 struct dmub_cmd_header header; /**< header */ 921 }; 922 923 /** 924 * struct dmub_clocks - Clock update notification. 925 */ 926 struct dmub_clocks { 927 uint32_t dispclk_khz; /**< dispclk kHz */ 928 uint32_t dppclk_khz; /**< dppclk kHz */ 929 uint32_t dcfclk_khz; /**< dcfclk kHz */ 930 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 931 }; 932 933 /** 934 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 935 */ 936 enum dmub_cmd_clk_mgr_type { 937 /** 938 * Notify DMCUB of clock update. 939 */ 940 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 941 }; 942 943 /** 944 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 945 */ 946 struct dmub_rb_cmd_clk_mgr_notify_clocks { 947 struct dmub_cmd_header header; /**< header */ 948 struct dmub_clocks clocks; /**< clock data */ 949 }; 950 951 /** 952 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 953 */ 954 struct dmub_cmd_digx_encoder_control_data { 955 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 956 }; 957 958 /** 959 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 960 */ 961 struct dmub_rb_cmd_digx_encoder_control { 962 struct dmub_cmd_header header; /**< header */ 963 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 964 }; 965 966 /** 967 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 968 */ 969 struct dmub_cmd_set_pixel_clock_data { 970 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 971 }; 972 973 /** 974 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 975 */ 976 struct dmub_rb_cmd_set_pixel_clock { 977 struct dmub_cmd_header header; /**< header */ 978 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 979 }; 980 981 /** 982 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 983 */ 984 struct dmub_cmd_enable_disp_power_gating_data { 985 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 986 }; 987 988 /** 989 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 990 */ 991 struct dmub_rb_cmd_enable_disp_power_gating { 992 struct dmub_cmd_header header; /**< header */ 993 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 994 }; 995 996 /** 997 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 998 */ 999 struct dmub_dig_transmitter_control_data_v1_7 { 1000 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1001 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1002 union { 1003 uint8_t digmode; /**< enum atom_encode_mode_def */ 1004 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1005 } mode_laneset; 1006 uint8_t lanenum; /**< Number of lanes */ 1007 union { 1008 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1009 } symclk_units; 1010 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1011 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1012 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1013 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1014 uint8_t reserved1; /**< For future use */ 1015 uint8_t reserved2[3]; /**< For future use */ 1016 uint32_t reserved3[11]; /**< For future use */ 1017 }; 1018 1019 /** 1020 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1021 */ 1022 union dmub_cmd_dig1_transmitter_control_data { 1023 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1024 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1025 }; 1026 1027 /** 1028 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1029 */ 1030 struct dmub_rb_cmd_dig1_transmitter_control { 1031 struct dmub_cmd_header header; /**< header */ 1032 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1033 }; 1034 1035 /** 1036 * DPIA tunnel command parameters. 1037 */ 1038 struct dmub_cmd_dig_dpia_control_data { 1039 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1040 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1041 union { 1042 uint8_t digmode; /** enum atom_encode_mode_def */ 1043 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1044 } mode_laneset; 1045 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1046 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1047 uint8_t hpdsel; /** =0: HPD is not assigned */ 1048 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1049 uint8_t dpia_id; /** Index of DPIA */ 1050 uint8_t fec_rdy : 1; 1051 uint8_t reserved : 7; 1052 uint32_t reserved1; 1053 }; 1054 1055 /** 1056 * DMUB command for DPIA tunnel control. 1057 */ 1058 struct dmub_rb_cmd_dig1_dpia_control { 1059 struct dmub_cmd_header header; 1060 struct dmub_cmd_dig_dpia_control_data dpia_control; 1061 }; 1062 1063 /** 1064 * SET_CONFIG Command Payload 1065 */ 1066 struct set_config_cmd_payload { 1067 uint8_t msg_type; /* set config message type */ 1068 uint8_t msg_data; /* set config message data */ 1069 }; 1070 1071 /** 1072 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1073 */ 1074 struct dmub_cmd_set_config_control_data { 1075 struct set_config_cmd_payload cmd_pkt; 1076 uint8_t instance; /* DPIA instance */ 1077 uint8_t immed_status; /* Immediate status returned in case of error */ 1078 }; 1079 1080 /** 1081 * DMUB command structure for SET_CONFIG command. 1082 */ 1083 struct dmub_rb_cmd_set_config_access { 1084 struct dmub_cmd_header header; /* header */ 1085 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1086 }; 1087 1088 /** 1089 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1090 */ 1091 struct dmub_cmd_mst_alloc_slots_control_data { 1092 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1093 uint8_t instance; /* DPIA instance */ 1094 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1095 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1096 }; 1097 1098 /** 1099 * DMUB command structure for SET_ command. 1100 */ 1101 struct dmub_rb_cmd_set_mst_alloc_slots { 1102 struct dmub_cmd_header header; /* header */ 1103 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1104 }; 1105 1106 /** 1107 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1108 */ 1109 struct dmub_rb_cmd_dpphy_init { 1110 struct dmub_cmd_header header; /**< header */ 1111 uint8_t reserved[60]; /**< reserved bits */ 1112 }; 1113 1114 /** 1115 * enum dp_aux_request_action - DP AUX request command listing. 1116 * 1117 * 4 AUX request command bits are shifted to high nibble. 1118 */ 1119 enum dp_aux_request_action { 1120 /** I2C-over-AUX write request */ 1121 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1122 /** I2C-over-AUX read request */ 1123 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1124 /** I2C-over-AUX write status request */ 1125 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1126 /** I2C-over-AUX write request with MOT=1 */ 1127 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1128 /** I2C-over-AUX read request with MOT=1 */ 1129 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1130 /** I2C-over-AUX write status request with MOT=1 */ 1131 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1132 /** Native AUX write request */ 1133 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1134 /** Native AUX read request */ 1135 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1136 }; 1137 1138 /** 1139 * enum aux_return_code_type - DP AUX process return code listing. 1140 */ 1141 enum aux_return_code_type { 1142 /** AUX process succeeded */ 1143 AUX_RET_SUCCESS = 0, 1144 /** AUX process failed with unknown reason */ 1145 AUX_RET_ERROR_UNKNOWN, 1146 /** AUX process completed with invalid reply */ 1147 AUX_RET_ERROR_INVALID_REPLY, 1148 /** AUX process timed out */ 1149 AUX_RET_ERROR_TIMEOUT, 1150 /** HPD was low during AUX process */ 1151 AUX_RET_ERROR_HPD_DISCON, 1152 /** Failed to acquire AUX engine */ 1153 AUX_RET_ERROR_ENGINE_ACQUIRE, 1154 /** AUX request not supported */ 1155 AUX_RET_ERROR_INVALID_OPERATION, 1156 /** AUX process not available */ 1157 AUX_RET_ERROR_PROTOCOL_ERROR, 1158 }; 1159 1160 /** 1161 * enum aux_channel_type - DP AUX channel type listing. 1162 */ 1163 enum aux_channel_type { 1164 /** AUX thru Legacy DP AUX */ 1165 AUX_CHANNEL_LEGACY_DDC, 1166 /** AUX thru DPIA DP tunneling */ 1167 AUX_CHANNEL_DPIA 1168 }; 1169 1170 /** 1171 * struct aux_transaction_parameters - DP AUX request transaction data 1172 */ 1173 struct aux_transaction_parameters { 1174 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1175 uint8_t action; /**< enum dp_aux_request_action */ 1176 uint8_t length; /**< DP AUX request data length */ 1177 uint8_t reserved; /**< For future use */ 1178 uint32_t address; /**< DP AUX address */ 1179 uint8_t data[16]; /**< DP AUX write data */ 1180 }; 1181 1182 /** 1183 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1184 */ 1185 struct dmub_cmd_dp_aux_control_data { 1186 uint8_t instance; /**< AUX instance or DPIA instance */ 1187 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1188 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1189 uint8_t reserved0; /**< For future use */ 1190 uint16_t timeout; /**< timeout time in us */ 1191 uint16_t reserved1; /**< For future use */ 1192 enum aux_channel_type type; /**< enum aux_channel_type */ 1193 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1194 }; 1195 1196 /** 1197 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1198 */ 1199 struct dmub_rb_cmd_dp_aux_access { 1200 /** 1201 * Command header. 1202 */ 1203 struct dmub_cmd_header header; 1204 /** 1205 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1206 */ 1207 struct dmub_cmd_dp_aux_control_data aux_control; 1208 }; 1209 1210 /** 1211 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1212 */ 1213 struct dmub_rb_cmd_outbox1_enable { 1214 /** 1215 * Command header. 1216 */ 1217 struct dmub_cmd_header header; 1218 /** 1219 * enable: 0x0 -> disable outbox1 notification (default value) 1220 * 0x1 -> enable outbox1 notification 1221 */ 1222 uint32_t enable; 1223 }; 1224 1225 /* DP AUX Reply command - OutBox Cmd */ 1226 /** 1227 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1228 */ 1229 struct aux_reply_data { 1230 /** 1231 * Aux cmd 1232 */ 1233 uint8_t command; 1234 /** 1235 * Aux reply data length (max: 16 bytes) 1236 */ 1237 uint8_t length; 1238 /** 1239 * Alignment only 1240 */ 1241 uint8_t pad[2]; 1242 /** 1243 * Aux reply data 1244 */ 1245 uint8_t data[16]; 1246 }; 1247 1248 /** 1249 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1250 */ 1251 struct aux_reply_control_data { 1252 /** 1253 * Reserved for future use 1254 */ 1255 uint32_t handle; 1256 /** 1257 * Aux Instance 1258 */ 1259 uint8_t instance; 1260 /** 1261 * Aux transaction result: definition in enum aux_return_code_type 1262 */ 1263 uint8_t result; 1264 /** 1265 * Alignment only 1266 */ 1267 uint16_t pad; 1268 }; 1269 1270 /** 1271 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1272 */ 1273 struct dmub_rb_cmd_dp_aux_reply { 1274 /** 1275 * Command header. 1276 */ 1277 struct dmub_cmd_header header; 1278 /** 1279 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1280 */ 1281 struct aux_reply_control_data control; 1282 /** 1283 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1284 */ 1285 struct aux_reply_data reply_data; 1286 }; 1287 1288 /* DP HPD Notify command - OutBox Cmd */ 1289 /** 1290 * DP HPD Type 1291 */ 1292 enum dp_hpd_type { 1293 /** 1294 * Normal DP HPD 1295 */ 1296 DP_HPD = 0, 1297 /** 1298 * DP HPD short pulse 1299 */ 1300 DP_IRQ 1301 }; 1302 1303 /** 1304 * DP HPD Status 1305 */ 1306 enum dp_hpd_status { 1307 /** 1308 * DP_HPD status low 1309 */ 1310 DP_HPD_UNPLUG = 0, 1311 /** 1312 * DP_HPD status high 1313 */ 1314 DP_HPD_PLUG 1315 }; 1316 1317 /** 1318 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1319 */ 1320 struct dp_hpd_data { 1321 /** 1322 * DP HPD instance 1323 */ 1324 uint8_t instance; 1325 /** 1326 * HPD type 1327 */ 1328 uint8_t hpd_type; 1329 /** 1330 * HPD status: only for type: DP_HPD to indicate status 1331 */ 1332 uint8_t hpd_status; 1333 /** 1334 * Alignment only 1335 */ 1336 uint8_t pad; 1337 }; 1338 1339 /** 1340 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1341 */ 1342 struct dmub_rb_cmd_dp_hpd_notify { 1343 /** 1344 * Command header. 1345 */ 1346 struct dmub_cmd_header header; 1347 /** 1348 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1349 */ 1350 struct dp_hpd_data hpd_data; 1351 }; 1352 1353 /** 1354 * Definition of a SET_CONFIG reply from DPOA. 1355 */ 1356 enum set_config_status { 1357 SET_CONFIG_PENDING = 0, 1358 SET_CONFIG_ACK_RECEIVED, 1359 SET_CONFIG_RX_TIMEOUT, 1360 SET_CONFIG_UNKNOWN_ERROR, 1361 }; 1362 1363 /** 1364 * Definition of a set_config reply 1365 */ 1366 struct set_config_reply_control_data { 1367 uint8_t instance; /* DPIA Instance */ 1368 uint8_t status; /* Set Config reply */ 1369 uint16_t pad; /* Alignment */ 1370 }; 1371 1372 /** 1373 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1374 */ 1375 struct dmub_rb_cmd_dp_set_config_reply { 1376 struct dmub_cmd_header header; 1377 struct set_config_reply_control_data set_config_reply_control; 1378 }; 1379 1380 /** 1381 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1382 */ 1383 struct dmub_cmd_hpd_state_query_data { 1384 uint8_t instance; /**< HPD instance or DPIA instance */ 1385 uint8_t result; /**< For returning HPD state */ 1386 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1387 enum aux_return_code_type status; /**< for returning the status of command */ 1388 }; 1389 1390 /** 1391 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1392 */ 1393 struct dmub_rb_cmd_query_hpd_state { 1394 /** 1395 * Command header. 1396 */ 1397 struct dmub_cmd_header header; 1398 /** 1399 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1400 */ 1401 struct dmub_cmd_hpd_state_query_data data; 1402 }; 1403 1404 /* 1405 * Command IDs should be treated as stable ABI. 1406 * Do not reuse or modify IDs. 1407 */ 1408 1409 /** 1410 * PSR command sub-types. 1411 */ 1412 enum dmub_cmd_psr_type { 1413 /** 1414 * Set PSR version support. 1415 */ 1416 DMUB_CMD__PSR_SET_VERSION = 0, 1417 /** 1418 * Copy driver-calculated parameters to PSR state. 1419 */ 1420 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1421 /** 1422 * Enable PSR. 1423 */ 1424 DMUB_CMD__PSR_ENABLE = 2, 1425 1426 /** 1427 * Disable PSR. 1428 */ 1429 DMUB_CMD__PSR_DISABLE = 3, 1430 1431 /** 1432 * Set PSR level. 1433 * PSR level is a 16-bit value dicated by driver that 1434 * will enable/disable different functionality. 1435 */ 1436 DMUB_CMD__PSR_SET_LEVEL = 4, 1437 1438 /** 1439 * Forces PSR enabled until an explicit PSR disable call. 1440 */ 1441 DMUB_CMD__PSR_FORCE_STATIC = 5, 1442 /** 1443 * Set PSR power option 1444 */ 1445 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1446 }; 1447 1448 /** 1449 * PSR versions. 1450 */ 1451 enum psr_version { 1452 /** 1453 * PSR version 1. 1454 */ 1455 PSR_VERSION_1 = 0, 1456 /** 1457 * PSR not supported. 1458 */ 1459 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1460 }; 1461 1462 /** 1463 * enum dmub_cmd_mall_type - MALL commands 1464 */ 1465 enum dmub_cmd_mall_type { 1466 /** 1467 * Allows display refresh from MALL. 1468 */ 1469 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1470 /** 1471 * Disallows display refresh from MALL. 1472 */ 1473 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1474 /** 1475 * Cursor copy for MALL. 1476 */ 1477 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1478 /** 1479 * Controls DF requests. 1480 */ 1481 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1482 }; 1483 1484 /** 1485 * PHY Link rate for DP. 1486 */ 1487 enum phy_link_rate { 1488 /** 1489 * not supported. 1490 */ 1491 PHY_RATE_UNKNOWN = 0, 1492 /** 1493 * Rate_1 (RBR) - 1.62 Gbps/Lane 1494 */ 1495 PHY_RATE_162 = 1, 1496 /** 1497 * Rate_2 - 2.16 Gbps/Lane 1498 */ 1499 PHY_RATE_216 = 2, 1500 /** 1501 * Rate_3 - 2.43 Gbps/Lane 1502 */ 1503 PHY_RATE_243 = 3, 1504 /** 1505 * Rate_4 (HBR) - 2.70 Gbps/Lane 1506 */ 1507 PHY_RATE_270 = 4, 1508 /** 1509 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1510 */ 1511 PHY_RATE_324 = 5, 1512 /** 1513 * Rate_6 - 4.32 Gbps/Lane 1514 */ 1515 PHY_RATE_432 = 6, 1516 /** 1517 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1518 */ 1519 PHY_RATE_540 = 7, 1520 /** 1521 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1522 */ 1523 PHY_RATE_810 = 8, 1524 /** 1525 * UHBR10 - 10.0 Gbps/Lane 1526 */ 1527 PHY_RATE_1000 = 9, 1528 /** 1529 * UHBR13.5 - 13.5 Gbps/Lane 1530 */ 1531 PHY_RATE_1350 = 10, 1532 /** 1533 * UHBR10 - 20.0 Gbps/Lane 1534 */ 1535 PHY_RATE_2000 = 11, 1536 }; 1537 1538 /** 1539 * enum dmub_phy_fsm_state - PHY FSM states. 1540 * PHY FSM state to transit to during PSR enable/disable. 1541 */ 1542 enum dmub_phy_fsm_state { 1543 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1544 DMUB_PHY_FSM_RESET, 1545 DMUB_PHY_FSM_RESET_RELEASED, 1546 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1547 DMUB_PHY_FSM_INITIALIZED, 1548 DMUB_PHY_FSM_CALIBRATED, 1549 DMUB_PHY_FSM_CALIBRATED_LP, 1550 DMUB_PHY_FSM_CALIBRATED_PG, 1551 DMUB_PHY_FSM_POWER_DOWN, 1552 DMUB_PHY_FSM_PLL_EN, 1553 DMUB_PHY_FSM_TX_EN, 1554 DMUB_PHY_FSM_FAST_LP, 1555 }; 1556 1557 /** 1558 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1559 */ 1560 struct dmub_cmd_psr_copy_settings_data { 1561 /** 1562 * Flags that can be set by driver to change some PSR behaviour. 1563 */ 1564 union dmub_psr_debug_flags debug; 1565 /** 1566 * 16-bit value dicated by driver that will enable/disable different functionality. 1567 */ 1568 uint16_t psr_level; 1569 /** 1570 * DPP HW instance. 1571 */ 1572 uint8_t dpp_inst; 1573 /** 1574 * MPCC HW instance. 1575 * Not used in dmub fw, 1576 * dmub fw will get active opp by reading odm registers. 1577 */ 1578 uint8_t mpcc_inst; 1579 /** 1580 * OPP HW instance. 1581 * Not used in dmub fw, 1582 * dmub fw will get active opp by reading odm registers. 1583 */ 1584 uint8_t opp_inst; 1585 /** 1586 * OTG HW instance. 1587 */ 1588 uint8_t otg_inst; 1589 /** 1590 * DIG FE HW instance. 1591 */ 1592 uint8_t digfe_inst; 1593 /** 1594 * DIG BE HW instance. 1595 */ 1596 uint8_t digbe_inst; 1597 /** 1598 * DP PHY HW instance. 1599 */ 1600 uint8_t dpphy_inst; 1601 /** 1602 * AUX HW instance. 1603 */ 1604 uint8_t aux_inst; 1605 /** 1606 * Determines if SMU optimzations are enabled/disabled. 1607 */ 1608 uint8_t smu_optimizations_en; 1609 /** 1610 * Unused. 1611 * TODO: Remove. 1612 */ 1613 uint8_t frame_delay; 1614 /** 1615 * If RFB setup time is greater than the total VBLANK time, 1616 * it is not possible for the sink to capture the video frame 1617 * in the same frame the SDP is sent. In this case, 1618 * the frame capture indication bit should be set and an extra 1619 * static frame should be transmitted to the sink. 1620 */ 1621 uint8_t frame_cap_ind; 1622 /** 1623 * Explicit padding to 4 byte boundary. 1624 */ 1625 uint8_t pad[2]; 1626 /** 1627 * Multi-display optimizations are implemented on certain ASICs. 1628 */ 1629 uint8_t multi_disp_optimizations_en; 1630 /** 1631 * The last possible line SDP may be transmitted without violating 1632 * the RFB setup time or entering the active video frame. 1633 */ 1634 uint16_t init_sdp_deadline; 1635 /** 1636 * Explicit padding to 4 byte boundary. 1637 */ 1638 uint16_t pad2; 1639 /** 1640 * Length of each horizontal line in us. 1641 */ 1642 uint32_t line_time_in_us; 1643 /** 1644 * FEC enable status in driver 1645 */ 1646 uint8_t fec_enable_status; 1647 /** 1648 * FEC re-enable delay when PSR exit. 1649 * unit is 100us, range form 0~255(0xFF). 1650 */ 1651 uint8_t fec_enable_delay_in100us; 1652 /** 1653 * PSR control version. 1654 */ 1655 uint8_t cmd_version; 1656 /** 1657 * Panel Instance. 1658 * Panel isntance to identify which psr_state to use 1659 * Currently the support is only for 0 or 1 1660 */ 1661 uint8_t panel_inst; 1662 /* 1663 * DSC enable status in driver 1664 */ 1665 uint8_t dsc_enable_status; 1666 /* 1667 * Use FSM state for PSR power up/down 1668 */ 1669 uint8_t use_phy_fsm; 1670 /** 1671 * Explicit padding to 2 byte boundary. 1672 */ 1673 uint8_t pad3[2]; 1674 }; 1675 1676 /** 1677 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1678 */ 1679 struct dmub_rb_cmd_psr_copy_settings { 1680 /** 1681 * Command header. 1682 */ 1683 struct dmub_cmd_header header; 1684 /** 1685 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1686 */ 1687 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1688 }; 1689 1690 /** 1691 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1692 */ 1693 struct dmub_cmd_psr_set_level_data { 1694 /** 1695 * 16-bit value dicated by driver that will enable/disable different functionality. 1696 */ 1697 uint16_t psr_level; 1698 /** 1699 * PSR control version. 1700 */ 1701 uint8_t cmd_version; 1702 /** 1703 * Panel Instance. 1704 * Panel isntance to identify which psr_state to use 1705 * Currently the support is only for 0 or 1 1706 */ 1707 uint8_t panel_inst; 1708 }; 1709 1710 /** 1711 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1712 */ 1713 struct dmub_rb_cmd_psr_set_level { 1714 /** 1715 * Command header. 1716 */ 1717 struct dmub_cmd_header header; 1718 /** 1719 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1720 */ 1721 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1722 }; 1723 1724 struct dmub_rb_cmd_psr_enable_data { 1725 /** 1726 * PSR control version. 1727 */ 1728 uint8_t cmd_version; 1729 /** 1730 * Panel Instance. 1731 * Panel isntance to identify which psr_state to use 1732 * Currently the support is only for 0 or 1 1733 */ 1734 uint8_t panel_inst; 1735 /** 1736 * Phy state to enter. 1737 * Values to use are defined in dmub_phy_fsm_state 1738 */ 1739 uint8_t phy_fsm_state; 1740 /** 1741 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1742 * Set this using enum phy_link_rate. 1743 * This does not support HDMI/DP2 for now. 1744 */ 1745 uint8_t phy_rate; 1746 }; 1747 1748 /** 1749 * Definition of a DMUB_CMD__PSR_ENABLE command. 1750 * PSR enable/disable is controlled using the sub_type. 1751 */ 1752 struct dmub_rb_cmd_psr_enable { 1753 /** 1754 * Command header. 1755 */ 1756 struct dmub_cmd_header header; 1757 1758 struct dmub_rb_cmd_psr_enable_data data; 1759 }; 1760 1761 /** 1762 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1763 */ 1764 struct dmub_cmd_psr_set_version_data { 1765 /** 1766 * PSR version that FW should implement. 1767 */ 1768 enum psr_version version; 1769 /** 1770 * PSR control version. 1771 */ 1772 uint8_t cmd_version; 1773 /** 1774 * Panel Instance. 1775 * Panel isntance to identify which psr_state to use 1776 * Currently the support is only for 0 or 1 1777 */ 1778 uint8_t panel_inst; 1779 /** 1780 * Explicit padding to 4 byte boundary. 1781 */ 1782 uint8_t pad[2]; 1783 }; 1784 1785 /** 1786 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1787 */ 1788 struct dmub_rb_cmd_psr_set_version { 1789 /** 1790 * Command header. 1791 */ 1792 struct dmub_cmd_header header; 1793 /** 1794 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1795 */ 1796 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1797 }; 1798 1799 struct dmub_cmd_psr_force_static_data { 1800 /** 1801 * PSR control version. 1802 */ 1803 uint8_t cmd_version; 1804 /** 1805 * Panel Instance. 1806 * Panel isntance to identify which psr_state to use 1807 * Currently the support is only for 0 or 1 1808 */ 1809 uint8_t panel_inst; 1810 /** 1811 * Explicit padding to 4 byte boundary. 1812 */ 1813 uint8_t pad[2]; 1814 }; 1815 1816 /** 1817 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1818 */ 1819 struct dmub_rb_cmd_psr_force_static { 1820 /** 1821 * Command header. 1822 */ 1823 struct dmub_cmd_header header; 1824 /** 1825 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1826 */ 1827 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1828 }; 1829 1830 /** 1831 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 1832 */ 1833 struct dmub_cmd_psr_set_power_opt_data { 1834 /** 1835 * PSR control version. 1836 */ 1837 uint8_t cmd_version; 1838 /** 1839 * Panel Instance. 1840 * Panel isntance to identify which psr_state to use 1841 * Currently the support is only for 0 or 1 1842 */ 1843 uint8_t panel_inst; 1844 /** 1845 * Explicit padding to 4 byte boundary. 1846 */ 1847 uint8_t pad[2]; 1848 /** 1849 * PSR power option 1850 */ 1851 uint32_t power_opt; 1852 }; 1853 1854 /** 1855 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1856 */ 1857 struct dmub_rb_cmd_psr_set_power_opt { 1858 /** 1859 * Command header. 1860 */ 1861 struct dmub_cmd_header header; 1862 /** 1863 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1864 */ 1865 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 1866 }; 1867 1868 /** 1869 * Set of HW components that can be locked. 1870 * 1871 * Note: If updating with more HW components, fields 1872 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1873 */ 1874 union dmub_hw_lock_flags { 1875 /** 1876 * Set of HW components that can be locked. 1877 */ 1878 struct { 1879 /** 1880 * Lock/unlock OTG master update lock. 1881 */ 1882 uint8_t lock_pipe : 1; 1883 /** 1884 * Lock/unlock cursor. 1885 */ 1886 uint8_t lock_cursor : 1; 1887 /** 1888 * Lock/unlock global update lock. 1889 */ 1890 uint8_t lock_dig : 1; 1891 /** 1892 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1893 */ 1894 uint8_t triple_buffer_lock : 1; 1895 } bits; 1896 1897 /** 1898 * Union for HW Lock flags. 1899 */ 1900 uint8_t u8All; 1901 }; 1902 1903 /** 1904 * Instances of HW to be locked. 1905 * 1906 * Note: If updating with more HW components, fields 1907 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1908 */ 1909 struct dmub_hw_lock_inst_flags { 1910 /** 1911 * OTG HW instance for OTG master update lock. 1912 */ 1913 uint8_t otg_inst; 1914 /** 1915 * OPP instance for cursor lock. 1916 */ 1917 uint8_t opp_inst; 1918 /** 1919 * OTG HW instance for global update lock. 1920 * TODO: Remove, and re-use otg_inst. 1921 */ 1922 uint8_t dig_inst; 1923 /** 1924 * Explicit pad to 4 byte boundary. 1925 */ 1926 uint8_t pad; 1927 }; 1928 1929 /** 1930 * Clients that can acquire the HW Lock Manager. 1931 * 1932 * Note: If updating with more clients, fields in 1933 * dmub_inbox0_cmd_lock_hw must be updated to match. 1934 */ 1935 enum hw_lock_client { 1936 /** 1937 * Driver is the client of HW Lock Manager. 1938 */ 1939 HW_LOCK_CLIENT_DRIVER = 0, 1940 /** 1941 * Invalid client. 1942 */ 1943 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1944 }; 1945 1946 /** 1947 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1948 */ 1949 struct dmub_cmd_lock_hw_data { 1950 /** 1951 * Specifies the client accessing HW Lock Manager. 1952 */ 1953 enum hw_lock_client client; 1954 /** 1955 * HW instances to be locked. 1956 */ 1957 struct dmub_hw_lock_inst_flags inst_flags; 1958 /** 1959 * Which components to be locked. 1960 */ 1961 union dmub_hw_lock_flags hw_locks; 1962 /** 1963 * Specifies lock/unlock. 1964 */ 1965 uint8_t lock; 1966 /** 1967 * HW can be unlocked separately from releasing the HW Lock Mgr. 1968 * This flag is set if the client wishes to release the object. 1969 */ 1970 uint8_t should_release; 1971 /** 1972 * Explicit padding to 4 byte boundary. 1973 */ 1974 uint8_t pad; 1975 }; 1976 1977 /** 1978 * Definition of a DMUB_CMD__HW_LOCK command. 1979 * Command is used by driver and FW. 1980 */ 1981 struct dmub_rb_cmd_lock_hw { 1982 /** 1983 * Command header. 1984 */ 1985 struct dmub_cmd_header header; 1986 /** 1987 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1988 */ 1989 struct dmub_cmd_lock_hw_data lock_hw_data; 1990 }; 1991 1992 /** 1993 * ABM command sub-types. 1994 */ 1995 enum dmub_cmd_abm_type { 1996 /** 1997 * Initialize parameters for ABM algorithm. 1998 * Data is passed through an indirect buffer. 1999 */ 2000 DMUB_CMD__ABM_INIT_CONFIG = 0, 2001 /** 2002 * Set OTG and panel HW instance. 2003 */ 2004 DMUB_CMD__ABM_SET_PIPE = 1, 2005 /** 2006 * Set user requested backklight level. 2007 */ 2008 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2009 /** 2010 * Set ABM operating/aggression level. 2011 */ 2012 DMUB_CMD__ABM_SET_LEVEL = 3, 2013 /** 2014 * Set ambient light level. 2015 */ 2016 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2017 /** 2018 * Enable/disable fractional duty cycle for backlight PWM. 2019 */ 2020 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2021 2022 /** 2023 * unregister vertical interrupt after steady state is reached 2024 */ 2025 DMUB_CMD__ABM_PAUSE = 6, 2026 }; 2027 2028 /** 2029 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2030 * Requirements: 2031 * - Padded explicitly to 32-bit boundary. 2032 * - Must ensure this structure matches the one on driver-side, 2033 * otherwise it won't be aligned. 2034 */ 2035 struct abm_config_table { 2036 /** 2037 * Gamma curve thresholds, used for crgb conversion. 2038 */ 2039 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2040 /** 2041 * Gamma curve offsets, used for crgb conversion. 2042 */ 2043 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2044 /** 2045 * Gamma curve slopes, used for crgb conversion. 2046 */ 2047 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2048 /** 2049 * Custom backlight curve thresholds. 2050 */ 2051 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2052 /** 2053 * Custom backlight curve offsets. 2054 */ 2055 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2056 /** 2057 * Ambient light thresholds. 2058 */ 2059 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2060 /** 2061 * Minimum programmable backlight. 2062 */ 2063 uint16_t min_abm_backlight; // 122B 2064 /** 2065 * Minimum reduction values. 2066 */ 2067 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2068 /** 2069 * Maximum reduction values. 2070 */ 2071 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2072 /** 2073 * Bright positive gain. 2074 */ 2075 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2076 /** 2077 * Dark negative gain. 2078 */ 2079 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2080 /** 2081 * Hybrid factor. 2082 */ 2083 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2084 /** 2085 * Contrast factor. 2086 */ 2087 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2088 /** 2089 * Deviation gain. 2090 */ 2091 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2092 /** 2093 * Minimum knee. 2094 */ 2095 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2096 /** 2097 * Maximum knee. 2098 */ 2099 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2100 /** 2101 * Unused. 2102 */ 2103 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2104 /** 2105 * Explicit padding to 4 byte boundary. 2106 */ 2107 uint8_t pad3[3]; // 229B 2108 /** 2109 * Backlight ramp reduction. 2110 */ 2111 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2112 /** 2113 * Backlight ramp start. 2114 */ 2115 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2116 }; 2117 2118 /** 2119 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2120 */ 2121 struct dmub_cmd_abm_set_pipe_data { 2122 /** 2123 * OTG HW instance. 2124 */ 2125 uint8_t otg_inst; 2126 2127 /** 2128 * Panel Control HW instance. 2129 */ 2130 uint8_t panel_inst; 2131 2132 /** 2133 * Controls how ABM will interpret a set pipe or set level command. 2134 */ 2135 uint8_t set_pipe_option; 2136 2137 /** 2138 * Unused. 2139 * TODO: Remove. 2140 */ 2141 uint8_t ramping_boundary; 2142 }; 2143 2144 /** 2145 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2146 */ 2147 struct dmub_rb_cmd_abm_set_pipe { 2148 /** 2149 * Command header. 2150 */ 2151 struct dmub_cmd_header header; 2152 2153 /** 2154 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2155 */ 2156 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2157 }; 2158 2159 /** 2160 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2161 */ 2162 struct dmub_cmd_abm_set_backlight_data { 2163 /** 2164 * Number of frames to ramp to backlight user level. 2165 */ 2166 uint32_t frame_ramp; 2167 2168 /** 2169 * Requested backlight level from user. 2170 */ 2171 uint32_t backlight_user_level; 2172 2173 /** 2174 * ABM control version. 2175 */ 2176 uint8_t version; 2177 2178 /** 2179 * Panel Control HW instance mask. 2180 * Bit 0 is Panel Control HW instance 0. 2181 * Bit 1 is Panel Control HW instance 1. 2182 */ 2183 uint8_t panel_mask; 2184 2185 /** 2186 * Explicit padding to 4 byte boundary. 2187 */ 2188 uint8_t pad[2]; 2189 }; 2190 2191 /** 2192 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2193 */ 2194 struct dmub_rb_cmd_abm_set_backlight { 2195 /** 2196 * Command header. 2197 */ 2198 struct dmub_cmd_header header; 2199 2200 /** 2201 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2202 */ 2203 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2204 }; 2205 2206 /** 2207 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2208 */ 2209 struct dmub_cmd_abm_set_level_data { 2210 /** 2211 * Set current ABM operating/aggression level. 2212 */ 2213 uint32_t level; 2214 2215 /** 2216 * ABM control version. 2217 */ 2218 uint8_t version; 2219 2220 /** 2221 * Panel Control HW instance mask. 2222 * Bit 0 is Panel Control HW instance 0. 2223 * Bit 1 is Panel Control HW instance 1. 2224 */ 2225 uint8_t panel_mask; 2226 2227 /** 2228 * Explicit padding to 4 byte boundary. 2229 */ 2230 uint8_t pad[2]; 2231 }; 2232 2233 /** 2234 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2235 */ 2236 struct dmub_rb_cmd_abm_set_level { 2237 /** 2238 * Command header. 2239 */ 2240 struct dmub_cmd_header header; 2241 2242 /** 2243 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2244 */ 2245 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2246 }; 2247 2248 /** 2249 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2250 */ 2251 struct dmub_cmd_abm_set_ambient_level_data { 2252 /** 2253 * Ambient light sensor reading from OS. 2254 */ 2255 uint32_t ambient_lux; 2256 2257 /** 2258 * ABM control version. 2259 */ 2260 uint8_t version; 2261 2262 /** 2263 * Panel Control HW instance mask. 2264 * Bit 0 is Panel Control HW instance 0. 2265 * Bit 1 is Panel Control HW instance 1. 2266 */ 2267 uint8_t panel_mask; 2268 2269 /** 2270 * Explicit padding to 4 byte boundary. 2271 */ 2272 uint8_t pad[2]; 2273 }; 2274 2275 /** 2276 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2277 */ 2278 struct dmub_rb_cmd_abm_set_ambient_level { 2279 /** 2280 * Command header. 2281 */ 2282 struct dmub_cmd_header header; 2283 2284 /** 2285 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2286 */ 2287 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2288 }; 2289 2290 /** 2291 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2292 */ 2293 struct dmub_cmd_abm_set_pwm_frac_data { 2294 /** 2295 * Enable/disable fractional duty cycle for backlight PWM. 2296 * TODO: Convert to uint8_t. 2297 */ 2298 uint32_t fractional_pwm; 2299 2300 /** 2301 * ABM control version. 2302 */ 2303 uint8_t version; 2304 2305 /** 2306 * Panel Control HW instance mask. 2307 * Bit 0 is Panel Control HW instance 0. 2308 * Bit 1 is Panel Control HW instance 1. 2309 */ 2310 uint8_t panel_mask; 2311 2312 /** 2313 * Explicit padding to 4 byte boundary. 2314 */ 2315 uint8_t pad[2]; 2316 }; 2317 2318 /** 2319 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2320 */ 2321 struct dmub_rb_cmd_abm_set_pwm_frac { 2322 /** 2323 * Command header. 2324 */ 2325 struct dmub_cmd_header header; 2326 2327 /** 2328 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2329 */ 2330 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2331 }; 2332 2333 /** 2334 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2335 */ 2336 struct dmub_cmd_abm_init_config_data { 2337 /** 2338 * Location of indirect buffer used to pass init data to ABM. 2339 */ 2340 union dmub_addr src; 2341 2342 /** 2343 * Indirect buffer length. 2344 */ 2345 uint16_t bytes; 2346 2347 2348 /** 2349 * ABM control version. 2350 */ 2351 uint8_t version; 2352 2353 /** 2354 * Panel Control HW instance mask. 2355 * Bit 0 is Panel Control HW instance 0. 2356 * Bit 1 is Panel Control HW instance 1. 2357 */ 2358 uint8_t panel_mask; 2359 2360 /** 2361 * Explicit padding to 4 byte boundary. 2362 */ 2363 uint8_t pad[2]; 2364 }; 2365 2366 /** 2367 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2368 */ 2369 struct dmub_rb_cmd_abm_init_config { 2370 /** 2371 * Command header. 2372 */ 2373 struct dmub_cmd_header header; 2374 2375 /** 2376 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2377 */ 2378 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2379 }; 2380 2381 /** 2382 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2383 */ 2384 2385 struct dmub_cmd_abm_pause_data { 2386 2387 /** 2388 * Panel Control HW instance mask. 2389 * Bit 0 is Panel Control HW instance 0. 2390 * Bit 1 is Panel Control HW instance 1. 2391 */ 2392 uint8_t panel_mask; 2393 2394 /** 2395 * OTG hw instance 2396 */ 2397 uint8_t otg_inst; 2398 2399 /** 2400 * Enable or disable ABM pause 2401 */ 2402 uint8_t enable; 2403 2404 /** 2405 * Explicit padding to 4 byte boundary. 2406 */ 2407 uint8_t pad[1]; 2408 }; 2409 2410 /** 2411 * Definition of a DMUB_CMD__ABM_PAUSE command. 2412 */ 2413 struct dmub_rb_cmd_abm_pause { 2414 /** 2415 * Command header. 2416 */ 2417 struct dmub_cmd_header header; 2418 2419 /** 2420 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2421 */ 2422 struct dmub_cmd_abm_pause_data abm_pause_data; 2423 }; 2424 2425 /** 2426 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2427 */ 2428 struct dmub_cmd_query_feature_caps_data { 2429 /** 2430 * DMUB feature capabilities. 2431 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2432 */ 2433 struct dmub_feature_caps feature_caps; 2434 }; 2435 2436 /** 2437 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2438 */ 2439 struct dmub_rb_cmd_query_feature_caps { 2440 /** 2441 * Command header. 2442 */ 2443 struct dmub_cmd_header header; 2444 /** 2445 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2446 */ 2447 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2448 }; 2449 2450 struct dmub_optc_state { 2451 uint32_t v_total_max; 2452 uint32_t v_total_min; 2453 uint32_t v_total_mid; 2454 uint32_t v_total_mid_frame_num; 2455 uint32_t tg_inst; 2456 uint32_t enable_manual_trigger; 2457 uint32_t clear_force_vsync; 2458 }; 2459 2460 struct dmub_rb_cmd_drr_update { 2461 struct dmub_cmd_header header; 2462 struct dmub_optc_state dmub_optc_state_req; 2463 }; 2464 2465 /** 2466 * enum dmub_cmd_panel_cntl_type - Panel control command. 2467 */ 2468 enum dmub_cmd_panel_cntl_type { 2469 /** 2470 * Initializes embedded panel hardware blocks. 2471 */ 2472 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2473 /** 2474 * Queries backlight info for the embedded panel. 2475 */ 2476 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2477 }; 2478 2479 /** 2480 * struct dmub_cmd_panel_cntl_data - Panel control data. 2481 */ 2482 struct dmub_cmd_panel_cntl_data { 2483 uint32_t inst; /**< panel instance */ 2484 uint32_t current_backlight; /* in/out */ 2485 uint32_t bl_pwm_cntl; /* in/out */ 2486 uint32_t bl_pwm_period_cntl; /* in/out */ 2487 uint32_t bl_pwm_ref_div1; /* in/out */ 2488 uint8_t is_backlight_on : 1; /* in/out */ 2489 uint8_t is_powered_on : 1; /* in/out */ 2490 uint8_t padding[3]; 2491 uint32_t bl_pwm_ref_div2; /* in/out */ 2492 uint8_t reserved[4]; 2493 }; 2494 2495 /** 2496 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2497 */ 2498 struct dmub_rb_cmd_panel_cntl { 2499 struct dmub_cmd_header header; /**< header */ 2500 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2501 }; 2502 2503 /** 2504 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2505 */ 2506 struct dmub_cmd_lvtma_control_data { 2507 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2508 uint8_t reserved_0[3]; /**< For future use */ 2509 uint8_t panel_inst; /**< LVTMA control instance */ 2510 uint8_t reserved_1[3]; /**< For future use */ 2511 }; 2512 2513 /** 2514 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2515 */ 2516 struct dmub_rb_cmd_lvtma_control { 2517 /** 2518 * Command header. 2519 */ 2520 struct dmub_cmd_header header; 2521 /** 2522 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2523 */ 2524 struct dmub_cmd_lvtma_control_data data; 2525 }; 2526 2527 /** 2528 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2529 */ 2530 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2531 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2532 uint8_t is_usb; /**< is phy is usb */ 2533 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2534 uint8_t is_dp4; /**< is dp in 4 lane */ 2535 }; 2536 2537 /** 2538 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2539 */ 2540 struct dmub_rb_cmd_transmitter_query_dp_alt { 2541 struct dmub_cmd_header header; /**< header */ 2542 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2543 }; 2544 2545 /** 2546 * Maximum number of bytes a chunk sent to DMUB for parsing 2547 */ 2548 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2549 2550 /** 2551 * Represent a chunk of CEA blocks sent to DMUB for parsing 2552 */ 2553 struct dmub_cmd_send_edid_cea { 2554 uint16_t offset; /**< offset into the CEA block */ 2555 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2556 uint16_t cea_total_length; /**< total length of the CEA block */ 2557 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2558 uint8_t pad[3]; /**< padding and for future expansion */ 2559 }; 2560 2561 /** 2562 * Result of VSDB parsing from CEA block 2563 */ 2564 struct dmub_cmd_edid_cea_amd_vsdb { 2565 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2566 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2567 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2568 uint16_t min_frame_rate; /**< Maximum frame rate */ 2569 uint16_t max_frame_rate; /**< Minimum frame rate */ 2570 }; 2571 2572 /** 2573 * Result of sending a CEA chunk 2574 */ 2575 struct dmub_cmd_edid_cea_ack { 2576 uint16_t offset; /**< offset of the chunk into the CEA block */ 2577 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2578 uint8_t pad; /**< padding and for future expansion */ 2579 }; 2580 2581 /** 2582 * Specify whether the result is an ACK/NACK or the parsing has finished 2583 */ 2584 enum dmub_cmd_edid_cea_reply_type { 2585 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2586 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2587 }; 2588 2589 /** 2590 * Definition of a DMUB_CMD__EDID_CEA command. 2591 */ 2592 struct dmub_rb_cmd_edid_cea { 2593 struct dmub_cmd_header header; /**< Command header */ 2594 union dmub_cmd_edid_cea_data { 2595 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2596 struct dmub_cmd_edid_cea_output { /**< output with results */ 2597 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2598 union { 2599 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2600 struct dmub_cmd_edid_cea_ack ack; 2601 }; 2602 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2603 } data; /**< Command data */ 2604 2605 }; 2606 2607 /** 2608 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2609 */ 2610 struct dmub_cmd_cable_id_input { 2611 uint8_t phy_inst; /**< phy inst for cable id data */ 2612 }; 2613 2614 /** 2615 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2616 */ 2617 struct dmub_cmd_cable_id_output { 2618 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2619 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2620 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2621 uint8_t RESERVED :2; /**< reserved means not defined */ 2622 }; 2623 2624 /** 2625 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2626 */ 2627 struct dmub_rb_cmd_get_usbc_cable_id { 2628 struct dmub_cmd_header header; /**< Command header */ 2629 /** 2630 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2631 */ 2632 union dmub_cmd_cable_id_data { 2633 struct dmub_cmd_cable_id_input input; /**< Input */ 2634 struct dmub_cmd_cable_id_output output; /**< Output */ 2635 uint8_t output_raw; /**< Raw data output */ 2636 } data; 2637 }; 2638 2639 /** 2640 * union dmub_rb_cmd - DMUB inbox command. 2641 */ 2642 union dmub_rb_cmd { 2643 struct dmub_rb_cmd_lock_hw lock_hw; 2644 /** 2645 * Elements shared with all commands. 2646 */ 2647 struct dmub_rb_cmd_common cmd_common; 2648 /** 2649 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2650 */ 2651 struct dmub_rb_cmd_read_modify_write read_modify_write; 2652 /** 2653 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2654 */ 2655 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2656 /** 2657 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2658 */ 2659 struct dmub_rb_cmd_burst_write burst_write; 2660 /** 2661 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2662 */ 2663 struct dmub_rb_cmd_reg_wait reg_wait; 2664 /** 2665 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2666 */ 2667 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2668 /** 2669 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2670 */ 2671 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2672 /** 2673 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2674 */ 2675 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2676 /** 2677 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2678 */ 2679 struct dmub_rb_cmd_dpphy_init dpphy_init; 2680 /** 2681 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2682 */ 2683 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2684 /** 2685 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2686 */ 2687 struct dmub_rb_cmd_psr_set_version psr_set_version; 2688 /** 2689 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2690 */ 2691 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2692 /** 2693 * Definition of a DMUB_CMD__PSR_ENABLE command. 2694 */ 2695 struct dmub_rb_cmd_psr_enable psr_enable; 2696 /** 2697 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2698 */ 2699 struct dmub_rb_cmd_psr_set_level psr_set_level; 2700 /** 2701 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2702 */ 2703 struct dmub_rb_cmd_psr_force_static psr_force_static; 2704 /** 2705 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2706 */ 2707 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2708 /** 2709 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2710 */ 2711 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2712 /** 2713 * Definition of a DMUB_CMD__MALL command. 2714 */ 2715 struct dmub_rb_cmd_mall mall; 2716 /** 2717 * Definition of a DMUB_CMD__CAB command. 2718 */ 2719 struct dmub_rb_cmd_cab_for_ss cab; 2720 /** 2721 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2722 */ 2723 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2724 2725 /** 2726 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2727 */ 2728 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2729 2730 /** 2731 * Definition of DMUB_CMD__PANEL_CNTL commands. 2732 */ 2733 struct dmub_rb_cmd_panel_cntl panel_cntl; 2734 /** 2735 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2736 */ 2737 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2738 2739 /** 2740 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2741 */ 2742 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2743 2744 /** 2745 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2746 */ 2747 struct dmub_rb_cmd_abm_set_level abm_set_level; 2748 2749 /** 2750 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2751 */ 2752 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2753 2754 /** 2755 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2756 */ 2757 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2758 2759 /** 2760 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2761 */ 2762 struct dmub_rb_cmd_abm_init_config abm_init_config; 2763 2764 /** 2765 * Definition of a DMUB_CMD__ABM_PAUSE command. 2766 */ 2767 struct dmub_rb_cmd_abm_pause abm_pause; 2768 2769 /** 2770 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2771 */ 2772 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2773 2774 /** 2775 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2776 */ 2777 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2778 2779 /** 2780 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2781 */ 2782 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2783 struct dmub_rb_cmd_drr_update drr_update; 2784 /** 2785 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2786 */ 2787 struct dmub_rb_cmd_lvtma_control lvtma_control; 2788 /** 2789 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2790 */ 2791 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 2792 /** 2793 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 2794 */ 2795 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 2796 /** 2797 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2798 */ 2799 struct dmub_rb_cmd_set_config_access set_config_access; 2800 /** 2801 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2802 */ 2803 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 2804 /** 2805 * Definition of a DMUB_CMD__EDID_CEA command. 2806 */ 2807 struct dmub_rb_cmd_edid_cea edid_cea; 2808 /** 2809 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 2810 */ 2811 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 2812 2813 /** 2814 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2815 */ 2816 struct dmub_rb_cmd_query_hpd_state query_hpd; 2817 }; 2818 2819 /** 2820 * union dmub_rb_out_cmd - Outbox command 2821 */ 2822 union dmub_rb_out_cmd { 2823 /** 2824 * Parameters common to every command. 2825 */ 2826 struct dmub_rb_cmd_common cmd_common; 2827 /** 2828 * AUX reply command. 2829 */ 2830 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2831 /** 2832 * HPD notify command. 2833 */ 2834 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2835 /** 2836 * SET_CONFIG reply command. 2837 */ 2838 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2839 }; 2840 #pragma pack(pop) 2841 2842 2843 //============================================================================== 2844 //</DMUB_CMD>=================================================================== 2845 //============================================================================== 2846 //< DMUB_RB>==================================================================== 2847 //============================================================================== 2848 2849 #if defined(__cplusplus) 2850 extern "C" { 2851 #endif 2852 2853 /** 2854 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2855 */ 2856 struct dmub_rb_init_params { 2857 void *ctx; /**< Caller provided context pointer */ 2858 void *base_address; /**< CPU base address for ring's data */ 2859 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2860 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2861 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2862 }; 2863 2864 /** 2865 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2866 */ 2867 struct dmub_rb { 2868 void *base_address; /**< CPU address for the ring's data */ 2869 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2870 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2871 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2872 2873 void *ctx; /**< Caller provided context pointer */ 2874 void *dmub; /**< Pointer to the DMUB interface */ 2875 }; 2876 2877 /** 2878 * @brief Checks if the ringbuffer is empty. 2879 * 2880 * @param rb DMUB Ringbuffer 2881 * @return true if empty 2882 * @return false otherwise 2883 */ 2884 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2885 { 2886 return (rb->wrpt == rb->rptr); 2887 } 2888 2889 /** 2890 * @brief Checks if the ringbuffer is full 2891 * 2892 * @param rb DMUB Ringbuffer 2893 * @return true if full 2894 * @return false otherwise 2895 */ 2896 static inline bool dmub_rb_full(struct dmub_rb *rb) 2897 { 2898 uint32_t data_count; 2899 2900 if (rb->wrpt >= rb->rptr) 2901 data_count = rb->wrpt - rb->rptr; 2902 else 2903 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2904 2905 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2906 } 2907 2908 /** 2909 * @brief Pushes a command into the ringbuffer 2910 * 2911 * @param rb DMUB ringbuffer 2912 * @param cmd The command to push 2913 * @return true if the ringbuffer was not full 2914 * @return false otherwise 2915 */ 2916 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2917 const union dmub_rb_cmd *cmd) 2918 { 2919 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 2920 const uint64_t *src = (const uint64_t *)cmd; 2921 uint8_t i; 2922 2923 if (dmub_rb_full(rb)) 2924 return false; 2925 2926 // copying data 2927 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2928 *dst++ = *src++; 2929 2930 rb->wrpt += DMUB_RB_CMD_SIZE; 2931 2932 if (rb->wrpt >= rb->capacity) 2933 rb->wrpt %= rb->capacity; 2934 2935 return true; 2936 } 2937 2938 /** 2939 * @brief Pushes a command into the DMUB outbox ringbuffer 2940 * 2941 * @param rb DMUB outbox ringbuffer 2942 * @param cmd Outbox command 2943 * @return true if not full 2944 * @return false otherwise 2945 */ 2946 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2947 const union dmub_rb_out_cmd *cmd) 2948 { 2949 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2950 const uint8_t *src = (const uint8_t *)cmd; 2951 2952 if (dmub_rb_full(rb)) 2953 return false; 2954 2955 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2956 2957 rb->wrpt += DMUB_RB_CMD_SIZE; 2958 2959 if (rb->wrpt >= rb->capacity) 2960 rb->wrpt %= rb->capacity; 2961 2962 return true; 2963 } 2964 2965 /** 2966 * @brief Returns the next unprocessed command in the ringbuffer. 2967 * 2968 * @param rb DMUB ringbuffer 2969 * @param cmd The command to return 2970 * @return true if not empty 2971 * @return false otherwise 2972 */ 2973 static inline bool dmub_rb_front(struct dmub_rb *rb, 2974 union dmub_rb_cmd **cmd) 2975 { 2976 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2977 2978 if (dmub_rb_empty(rb)) 2979 return false; 2980 2981 *cmd = (union dmub_rb_cmd *)rb_cmd; 2982 2983 return true; 2984 } 2985 2986 /** 2987 * @brief Determines the next ringbuffer offset. 2988 * 2989 * @param rb DMUB inbox ringbuffer 2990 * @param num_cmds Number of commands 2991 * @param next_rptr The next offset in the ringbuffer 2992 */ 2993 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2994 uint32_t num_cmds, 2995 uint32_t *next_rptr) 2996 { 2997 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2998 2999 if (*next_rptr >= rb->capacity) 3000 *next_rptr %= rb->capacity; 3001 } 3002 3003 /** 3004 * @brief Returns a pointer to a command in the inbox. 3005 * 3006 * @param rb DMUB inbox ringbuffer 3007 * @param cmd The inbox command to return 3008 * @param rptr The ringbuffer offset 3009 * @return true if not empty 3010 * @return false otherwise 3011 */ 3012 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3013 union dmub_rb_cmd **cmd, 3014 uint32_t rptr) 3015 { 3016 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3017 3018 if (dmub_rb_empty(rb)) 3019 return false; 3020 3021 *cmd = (union dmub_rb_cmd *)rb_cmd; 3022 3023 return true; 3024 } 3025 3026 /** 3027 * @brief Returns the next unprocessed command in the outbox. 3028 * 3029 * @param rb DMUB outbox ringbuffer 3030 * @param cmd The outbox command to return 3031 * @return true if not empty 3032 * @return false otherwise 3033 */ 3034 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3035 union dmub_rb_out_cmd *cmd) 3036 { 3037 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3038 uint64_t *dst = (uint64_t *)cmd; 3039 uint8_t i; 3040 3041 if (dmub_rb_empty(rb)) 3042 return false; 3043 3044 // copying data 3045 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3046 *dst++ = *src++; 3047 3048 return true; 3049 } 3050 3051 /** 3052 * @brief Removes the front entry in the ringbuffer. 3053 * 3054 * @param rb DMUB ringbuffer 3055 * @return true if the command was removed 3056 * @return false if there were no commands 3057 */ 3058 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3059 { 3060 if (dmub_rb_empty(rb)) 3061 return false; 3062 3063 rb->rptr += DMUB_RB_CMD_SIZE; 3064 3065 if (rb->rptr >= rb->capacity) 3066 rb->rptr %= rb->capacity; 3067 3068 return true; 3069 } 3070 3071 /** 3072 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3073 * 3074 * Avoids a race condition where DMCUB accesses memory while 3075 * there are still writes in flight to framebuffer. 3076 * 3077 * @param rb DMUB ringbuffer 3078 */ 3079 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3080 { 3081 uint32_t rptr = rb->rptr; 3082 uint32_t wptr = rb->wrpt; 3083 3084 while (rptr != wptr) { 3085 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3086 uint8_t i; 3087 3088 /* Don't remove this. 3089 * The contents need to actually be read from the ring buffer 3090 * for this function to be effective. 3091 */ 3092 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3093 (void)READ_ONCE(*data++); 3094 3095 rptr += DMUB_RB_CMD_SIZE; 3096 if (rptr >= rb->capacity) 3097 rptr %= rb->capacity; 3098 } 3099 } 3100 3101 /** 3102 * @brief Initializes a DMCUB ringbuffer 3103 * 3104 * @param rb DMUB ringbuffer 3105 * @param init_params initial configuration for the ringbuffer 3106 */ 3107 static inline void dmub_rb_init(struct dmub_rb *rb, 3108 struct dmub_rb_init_params *init_params) 3109 { 3110 rb->base_address = init_params->base_address; 3111 rb->capacity = init_params->capacity; 3112 rb->rptr = init_params->read_ptr; 3113 rb->wrpt = init_params->write_ptr; 3114 } 3115 3116 /** 3117 * @brief Copies output data from in/out commands into the given command. 3118 * 3119 * @param rb DMUB ringbuffer 3120 * @param cmd Command to copy data into 3121 */ 3122 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3123 union dmub_rb_cmd *cmd) 3124 { 3125 // Copy rb entry back into command 3126 uint8_t *rd_ptr = (rb->rptr == 0) ? 3127 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3128 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3129 3130 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3131 } 3132 3133 #if defined(__cplusplus) 3134 } 3135 #endif 3136 3137 //============================================================================== 3138 //</DMUB_RB>==================================================================== 3139 //============================================================================== 3140 3141 #endif /* _DMUB_CMD_H_ */ 3142