1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0x992f4893d 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 66 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 #define DMUB_MAX_SUBVP_STREAMS 2 121 122 /* Trace buffer offset for entry */ 123 #define TRACE_BUFFER_ENTRY_OFFSET 16 124 125 /** 126 * ABM control version legacy 127 */ 128 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 129 130 /** 131 * ABM control version with multi edp support 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 134 135 /** 136 * Physical framebuffer address location, 64-bit. 137 */ 138 #ifndef PHYSICAL_ADDRESS_LOC 139 #define PHYSICAL_ADDRESS_LOC union large_integer 140 #endif 141 142 /** 143 * OS/FW agnostic memcpy 144 */ 145 #ifndef dmub_memcpy 146 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 147 #endif 148 149 /** 150 * OS/FW agnostic memset 151 */ 152 #ifndef dmub_memset 153 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 154 #endif 155 156 #if defined(__cplusplus) 157 extern "C" { 158 #endif 159 160 /** 161 * OS/FW agnostic udelay 162 */ 163 #ifndef dmub_udelay 164 #define dmub_udelay(microseconds) udelay(microseconds) 165 #endif 166 167 /** 168 * Number of nanoseconds per DMUB tick. 169 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 170 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 171 */ 172 #define NS_PER_DMUB_TICK 10 173 174 /** 175 * union dmub_addr - DMUB physical/virtual 64-bit address. 176 */ 177 union dmub_addr { 178 struct { 179 uint32_t low_part; /**< Lower 32 bits */ 180 uint32_t high_part; /**< Upper 32 bits */ 181 } u; /*<< Low/high bit access */ 182 uint64_t quad_part; /*<< 64 bit address */ 183 }; 184 185 /** 186 * Flags that can be set by driver to change some PSR behaviour. 187 */ 188 union dmub_psr_debug_flags { 189 /** 190 * Debug flags. 191 */ 192 struct { 193 /** 194 * Enable visual confirm in FW. 195 */ 196 uint32_t visual_confirm : 1; 197 /** 198 * Use HW Lock Mgr object to do HW locking in FW. 199 */ 200 uint32_t use_hw_lock_mgr : 1; 201 202 /** 203 * Unused. 204 * TODO: Remove. 205 */ 206 uint32_t log_line_nums : 1; 207 } bitfields; 208 209 /** 210 * Union for debug flags. 211 */ 212 uint32_t u32All; 213 }; 214 215 /** 216 * DMUB feature capabilities. 217 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 218 */ 219 struct dmub_feature_caps { 220 /** 221 * Max PSR version supported by FW. 222 */ 223 uint8_t psr; 224 uint8_t reserved[7]; 225 }; 226 227 #if defined(__cplusplus) 228 } 229 #endif 230 231 //============================================================================== 232 //</DMUB_TYPES>================================================================= 233 //============================================================================== 234 //< DMUB_META>================================================================== 235 //============================================================================== 236 #pragma pack(push, 1) 237 238 /* Magic value for identifying dmub_fw_meta_info */ 239 #define DMUB_FW_META_MAGIC 0x444D5542 240 241 /* Offset from the end of the file to the dmub_fw_meta_info */ 242 #define DMUB_FW_META_OFFSET 0x24 243 244 /** 245 * struct dmub_fw_meta_info - metadata associated with fw binary 246 * 247 * NOTE: This should be considered a stable API. Fields should 248 * not be repurposed or reordered. New fields should be 249 * added instead to extend the structure. 250 * 251 * @magic_value: magic value identifying DMUB firmware meta info 252 * @fw_region_size: size of the firmware state region 253 * @trace_buffer_size: size of the tracebuffer region 254 * @fw_version: the firmware version information 255 * @dal_fw: 1 if the firmware is DAL 256 */ 257 struct dmub_fw_meta_info { 258 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 259 uint32_t fw_region_size; /**< size of the firmware state region */ 260 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 261 uint32_t fw_version; /**< the firmware version information */ 262 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 263 uint8_t reserved[3]; /**< padding bits */ 264 }; 265 266 /** 267 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 268 */ 269 union dmub_fw_meta { 270 struct dmub_fw_meta_info info; /**< metadata info */ 271 uint8_t reserved[64]; /**< padding bits */ 272 }; 273 274 #pragma pack(pop) 275 276 //============================================================================== 277 //< DMUB Trace Buffer>================================================================ 278 //============================================================================== 279 /** 280 * dmub_trace_code_t - firmware trace code, 32-bits 281 */ 282 typedef uint32_t dmub_trace_code_t; 283 284 /** 285 * struct dmcub_trace_buf_entry - Firmware trace entry 286 */ 287 struct dmcub_trace_buf_entry { 288 dmub_trace_code_t trace_code; /**< trace code for the event */ 289 uint32_t tick_count; /**< the tick count at time of trace */ 290 uint32_t param0; /**< trace defined parameter 0 */ 291 uint32_t param1; /**< trace defined parameter 1 */ 292 }; 293 294 //============================================================================== 295 //< DMUB_STATUS>================================================================ 296 //============================================================================== 297 298 /** 299 * DMCUB scratch registers can be used to determine firmware status. 300 * Current scratch register usage is as follows: 301 * 302 * SCRATCH0: FW Boot Status register 303 * SCRATCH15: FW Boot Options register 304 */ 305 306 /** 307 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 308 */ 309 union dmub_fw_boot_status { 310 struct { 311 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 312 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 313 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 314 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 315 } bits; /**< status bits */ 316 uint32_t all; /**< 32-bit access to status bits */ 317 }; 318 319 /** 320 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 321 */ 322 enum dmub_fw_boot_status_bit { 323 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 324 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 325 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 326 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 327 }; 328 329 /** 330 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 331 */ 332 union dmub_fw_boot_options { 333 struct { 334 uint32_t pemu_env : 1; /**< 1 if PEMU */ 335 uint32_t fpga_env : 1; /**< 1 if FPGA */ 336 uint32_t optimized_init : 1; /**< 1 if optimized init */ 337 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 338 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 339 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 340 uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */ 341 uint32_t reserved : 25; /**< reserved */ 342 } bits; /**< boot bits */ 343 uint32_t all; /**< 32-bit access to bits */ 344 }; 345 346 enum dmub_fw_boot_options_bit { 347 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 348 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 349 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 350 }; 351 352 //============================================================================== 353 //</DMUB_STATUS>================================================================ 354 //============================================================================== 355 //< DMUB_VBIOS>================================================================= 356 //============================================================================== 357 358 /* 359 * enum dmub_cmd_vbios_type - VBIOS commands. 360 * 361 * Command IDs should be treated as stable ABI. 362 * Do not reuse or modify IDs. 363 */ 364 enum dmub_cmd_vbios_type { 365 /** 366 * Configures the DIG encoder. 367 */ 368 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 369 /** 370 * Controls the PHY. 371 */ 372 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 373 /** 374 * Sets the pixel clock/symbol clock. 375 */ 376 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 377 /** 378 * Enables or disables power gating. 379 */ 380 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 381 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 382 }; 383 384 //============================================================================== 385 //</DMUB_VBIOS>================================================================= 386 //============================================================================== 387 //< DMUB_GPINT>================================================================= 388 //============================================================================== 389 390 /** 391 * The shifts and masks below may alternatively be used to format and read 392 * the command register bits. 393 */ 394 395 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 396 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 397 398 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 399 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 400 401 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 402 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 403 404 /** 405 * Command responses. 406 */ 407 408 /** 409 * Return response for DMUB_GPINT__STOP_FW command. 410 */ 411 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 412 413 /** 414 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 415 */ 416 union dmub_gpint_data_register { 417 struct { 418 uint32_t param : 16; /**< 16-bit parameter */ 419 uint32_t command_code : 12; /**< GPINT command */ 420 uint32_t status : 4; /**< Command status bit */ 421 } bits; /**< GPINT bit access */ 422 uint32_t all; /**< GPINT 32-bit access */ 423 }; 424 425 /* 426 * enum dmub_gpint_command - GPINT command to DMCUB FW 427 * 428 * Command IDs should be treated as stable ABI. 429 * Do not reuse or modify IDs. 430 */ 431 enum dmub_gpint_command { 432 /** 433 * Invalid command, ignored. 434 */ 435 DMUB_GPINT__INVALID_COMMAND = 0, 436 /** 437 * DESC: Queries the firmware version. 438 * RETURN: Firmware version. 439 */ 440 DMUB_GPINT__GET_FW_VERSION = 1, 441 /** 442 * DESC: Halts the firmware. 443 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 444 */ 445 DMUB_GPINT__STOP_FW = 2, 446 /** 447 * DESC: Get PSR state from FW. 448 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 449 */ 450 DMUB_GPINT__GET_PSR_STATE = 7, 451 /** 452 * DESC: Notifies DMCUB of the currently active streams. 453 * ARGS: Stream mask, 1 bit per active stream index. 454 */ 455 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 456 /** 457 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 458 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 459 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 460 * RETURN: PSR residency in milli-percent. 461 */ 462 DMUB_GPINT__PSR_RESIDENCY = 9, 463 }; 464 465 /** 466 * INBOX0 generic command definition 467 */ 468 union dmub_inbox0_cmd_common { 469 struct { 470 uint32_t command_code: 8; /**< INBOX0 command code */ 471 uint32_t param: 24; /**< 24-bit parameter */ 472 } bits; 473 uint32_t all; 474 }; 475 476 /** 477 * INBOX0 hw_lock command definition 478 */ 479 union dmub_inbox0_cmd_lock_hw { 480 struct { 481 uint32_t command_code: 8; 482 483 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 484 uint32_t hw_lock_client: 1; 485 486 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 487 uint32_t otg_inst: 3; 488 uint32_t opp_inst: 3; 489 uint32_t dig_inst: 3; 490 491 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 492 uint32_t lock_pipe: 1; 493 uint32_t lock_cursor: 1; 494 uint32_t lock_dig: 1; 495 uint32_t triple_buffer_lock: 1; 496 497 uint32_t lock: 1; /**< Lock */ 498 uint32_t should_release: 1; /**< Release */ 499 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 500 } bits; 501 uint32_t all; 502 }; 503 504 union dmub_inbox0_data_register { 505 union dmub_inbox0_cmd_common inbox0_cmd_common; 506 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 507 }; 508 509 enum dmub_inbox0_command { 510 /** 511 * DESC: Invalid command, ignored. 512 */ 513 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 514 /** 515 * DESC: Notification to acquire/release HW lock 516 * ARGS: 517 */ 518 DMUB_INBOX0_CMD__HW_LOCK = 1, 519 }; 520 //============================================================================== 521 //</DMUB_GPINT>================================================================= 522 //============================================================================== 523 //< DMUB_CMD>=================================================================== 524 //============================================================================== 525 526 /** 527 * Size in bytes of each DMUB command. 528 */ 529 #define DMUB_RB_CMD_SIZE 64 530 531 /** 532 * Maximum number of items in the DMUB ringbuffer. 533 */ 534 #define DMUB_RB_MAX_ENTRY 128 535 536 /** 537 * Ringbuffer size in bytes. 538 */ 539 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 540 541 /** 542 * REG_SET mask for reg offload. 543 */ 544 #define REG_SET_MASK 0xFFFF 545 546 /* 547 * enum dmub_cmd_type - DMUB inbox command. 548 * 549 * Command IDs should be treated as stable ABI. 550 * Do not reuse or modify IDs. 551 */ 552 enum dmub_cmd_type { 553 /** 554 * Invalid command. 555 */ 556 DMUB_CMD__NULL = 0, 557 /** 558 * Read modify write register sequence offload. 559 */ 560 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 561 /** 562 * Field update register sequence offload. 563 */ 564 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 565 /** 566 * Burst write sequence offload. 567 */ 568 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 569 /** 570 * Reg wait sequence offload. 571 */ 572 DMUB_CMD__REG_REG_WAIT = 4, 573 /** 574 * Workaround to avoid HUBP underflow during NV12 playback. 575 */ 576 DMUB_CMD__PLAT_54186_WA = 5, 577 /** 578 * Command type used to query FW feature caps. 579 */ 580 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 581 /** 582 * Command type used for all PSR commands. 583 */ 584 DMUB_CMD__PSR = 64, 585 /** 586 * Command type used for all MALL commands. 587 */ 588 DMUB_CMD__MALL = 65, 589 /** 590 * Command type used for all ABM commands. 591 */ 592 DMUB_CMD__ABM = 66, 593 /** 594 * Command type used for HW locking in FW. 595 */ 596 DMUB_CMD__HW_LOCK = 69, 597 /** 598 * Command type used to access DP AUX. 599 */ 600 DMUB_CMD__DP_AUX_ACCESS = 70, 601 /** 602 * Command type used for OUTBOX1 notification enable 603 */ 604 DMUB_CMD__OUTBOX1_ENABLE = 71, 605 /** 606 * Command type used for all VBIOS interface commands. 607 */ 608 DMUB_CMD__VBIOS = 128, 609 }; 610 611 /** 612 * enum dmub_out_cmd_type - DMUB outbox commands. 613 */ 614 enum dmub_out_cmd_type { 615 /** 616 * Invalid outbox command, ignored. 617 */ 618 DMUB_OUT_CMD__NULL = 0, 619 /** 620 * Command type used for DP AUX Reply data notification 621 */ 622 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 623 /** 624 * Command type used for DP HPD event notification 625 */ 626 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 627 }; 628 629 #pragma pack(push, 1) 630 631 /** 632 * struct dmub_cmd_header - Common command header fields. 633 */ 634 struct dmub_cmd_header { 635 unsigned int type : 8; /**< command type */ 636 unsigned int sub_type : 8; /**< command sub type */ 637 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 638 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 639 unsigned int reserved0 : 6; /**< reserved bits */ 640 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 641 unsigned int reserved1 : 2; /**< reserved bits */ 642 }; 643 644 /* 645 * struct dmub_cmd_read_modify_write_sequence - Read modify write 646 * 647 * 60 payload bytes can hold up to 5 sets of read modify writes, 648 * each take 3 dwords. 649 * 650 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 651 * 652 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 653 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 654 */ 655 struct dmub_cmd_read_modify_write_sequence { 656 uint32_t addr; /**< register address */ 657 uint32_t modify_mask; /**< modify mask */ 658 uint32_t modify_value; /**< modify value */ 659 }; 660 661 /** 662 * Maximum number of ops in read modify write sequence. 663 */ 664 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 665 666 /** 667 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 668 */ 669 struct dmub_rb_cmd_read_modify_write { 670 struct dmub_cmd_header header; /**< command header */ 671 /** 672 * Read modify write sequence. 673 */ 674 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 675 }; 676 677 /* 678 * Update a register with specified masks and values sequeunce 679 * 680 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 681 * 682 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 683 * 684 * 685 * USE CASE: 686 * 1. auto-increment register where additional read would update pointer and produce wrong result 687 * 2. toggle a bit without read in the middle 688 */ 689 690 struct dmub_cmd_reg_field_update_sequence { 691 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 692 uint32_t modify_value; /**< value to update with */ 693 }; 694 695 /** 696 * Maximum number of ops in field update sequence. 697 */ 698 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 699 700 /** 701 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 702 */ 703 struct dmub_rb_cmd_reg_field_update_sequence { 704 struct dmub_cmd_header header; /**< command header */ 705 uint32_t addr; /**< register address */ 706 /** 707 * Field update sequence. 708 */ 709 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 710 }; 711 712 713 /** 714 * Maximum number of burst write values. 715 */ 716 #define DMUB_BURST_WRITE_VALUES__MAX 14 717 718 /* 719 * struct dmub_rb_cmd_burst_write - Burst write 720 * 721 * support use case such as writing out LUTs. 722 * 723 * 60 payload bytes can hold up to 14 values to write to given address 724 * 725 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 726 */ 727 struct dmub_rb_cmd_burst_write { 728 struct dmub_cmd_header header; /**< command header */ 729 uint32_t addr; /**< register start address */ 730 /** 731 * Burst write register values. 732 */ 733 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 734 }; 735 736 /** 737 * struct dmub_rb_cmd_common - Common command header 738 */ 739 struct dmub_rb_cmd_common { 740 struct dmub_cmd_header header; /**< command header */ 741 /** 742 * Padding to RB_CMD_SIZE 743 */ 744 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 745 }; 746 747 /** 748 * struct dmub_cmd_reg_wait_data - Register wait data 749 */ 750 struct dmub_cmd_reg_wait_data { 751 uint32_t addr; /**< Register address */ 752 uint32_t mask; /**< Mask for register bits */ 753 uint32_t condition_field_value; /**< Value to wait for */ 754 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 755 }; 756 757 /** 758 * struct dmub_rb_cmd_reg_wait - Register wait command 759 */ 760 struct dmub_rb_cmd_reg_wait { 761 struct dmub_cmd_header header; /**< Command header */ 762 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 763 }; 764 765 /** 766 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 767 * 768 * Reprograms surface parameters to avoid underflow. 769 */ 770 struct dmub_cmd_PLAT_54186_wa { 771 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 772 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 773 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 774 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 775 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 776 struct { 777 uint8_t hubp_inst : 4; /**< HUBP instance */ 778 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 779 uint8_t immediate :1; /**< Immediate flip */ 780 uint8_t vmid : 4; /**< VMID */ 781 uint8_t grph_stereo : 1; /**< 1 if stereo */ 782 uint32_t reserved : 21; /**< Reserved */ 783 } flip_params; /**< Pageflip parameters */ 784 uint32_t reserved[9]; /**< Reserved bits */ 785 }; 786 787 /** 788 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 789 */ 790 struct dmub_rb_cmd_PLAT_54186_wa { 791 struct dmub_cmd_header header; /**< Command header */ 792 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 793 }; 794 795 /** 796 * struct dmub_rb_cmd_mall - MALL command data. 797 */ 798 struct dmub_rb_cmd_mall { 799 struct dmub_cmd_header header; /**< Common command header */ 800 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 801 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 802 uint32_t tmr_delay; /**< Timer delay */ 803 uint32_t tmr_scale; /**< Timer scale */ 804 uint16_t cursor_width; /**< Cursor width in pixels */ 805 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 806 uint16_t cursor_height; /**< Cursor height in pixels */ 807 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 808 uint8_t debug_bits; /**< Debug bits */ 809 810 uint8_t reserved1; /**< Reserved bits */ 811 uint8_t reserved2; /**< Reserved bits */ 812 }; 813 814 /** 815 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 816 */ 817 struct dmub_cmd_digx_encoder_control_data { 818 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 819 }; 820 821 /** 822 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 823 */ 824 struct dmub_rb_cmd_digx_encoder_control { 825 struct dmub_cmd_header header; /**< header */ 826 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 827 }; 828 829 /** 830 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 831 */ 832 struct dmub_cmd_set_pixel_clock_data { 833 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 834 }; 835 836 /** 837 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 838 */ 839 struct dmub_rb_cmd_set_pixel_clock { 840 struct dmub_cmd_header header; /**< header */ 841 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 842 }; 843 844 /** 845 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 846 */ 847 struct dmub_cmd_enable_disp_power_gating_data { 848 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 849 }; 850 851 /** 852 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 853 */ 854 struct dmub_rb_cmd_enable_disp_power_gating { 855 struct dmub_cmd_header header; /**< header */ 856 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 857 }; 858 859 /** 860 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 861 */ 862 struct dmub_dig_transmitter_control_data_v1_7 { 863 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 864 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 865 union { 866 uint8_t digmode; /**< enum atom_encode_mode_def */ 867 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 868 } mode_laneset; 869 uint8_t lanenum; /**< Number of lanes */ 870 union { 871 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 872 } symclk_units; 873 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 874 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 875 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 876 uint8_t reserved0; /**< For future use */ 877 uint8_t reserved1; /**< For future use */ 878 uint8_t reserved2[3]; /**< For future use */ 879 uint32_t reserved3[11]; /**< For future use */ 880 }; 881 882 /** 883 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 884 */ 885 union dmub_cmd_dig1_transmitter_control_data { 886 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 887 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 888 }; 889 890 /** 891 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 892 */ 893 struct dmub_rb_cmd_dig1_transmitter_control { 894 struct dmub_cmd_header header; /**< header */ 895 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 896 }; 897 898 /** 899 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 900 */ 901 struct dmub_rb_cmd_dpphy_init { 902 struct dmub_cmd_header header; /**< header */ 903 uint8_t reserved[60]; /**< reserved bits */ 904 }; 905 906 /** 907 * enum dp_aux_request_action - DP AUX request command listing. 908 * 909 * 4 AUX request command bits are shifted to high nibble. 910 */ 911 enum dp_aux_request_action { 912 /** I2C-over-AUX write request */ 913 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 914 /** I2C-over-AUX read request */ 915 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 916 /** I2C-over-AUX write status request */ 917 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 918 /** I2C-over-AUX write request with MOT=1 */ 919 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 920 /** I2C-over-AUX read request with MOT=1 */ 921 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 922 /** I2C-over-AUX write status request with MOT=1 */ 923 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 924 /** Native AUX write request */ 925 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 926 /** Native AUX read request */ 927 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 928 }; 929 930 /** 931 * enum aux_return_code_type - DP AUX process return code listing. 932 */ 933 enum aux_return_code_type { 934 /** AUX process succeeded */ 935 AUX_RET_SUCCESS = 0, 936 /** AUX process failed with unknown reason */ 937 AUX_RET_ERROR_UNKNOWN, 938 /** AUX process completed with invalid reply */ 939 AUX_RET_ERROR_INVALID_REPLY, 940 /** AUX process timed out */ 941 AUX_RET_ERROR_TIMEOUT, 942 /** HPD was low during AUX process */ 943 AUX_RET_ERROR_HPD_DISCON, 944 /** Failed to acquire AUX engine */ 945 AUX_RET_ERROR_ENGINE_ACQUIRE, 946 /** AUX request not supported */ 947 AUX_RET_ERROR_INVALID_OPERATION, 948 /** AUX process not available */ 949 AUX_RET_ERROR_PROTOCOL_ERROR, 950 }; 951 952 /** 953 * enum aux_channel_type - DP AUX channel type listing. 954 */ 955 enum aux_channel_type { 956 /** AUX thru Legacy DP AUX */ 957 AUX_CHANNEL_LEGACY_DDC, 958 /** AUX thru DPIA DP tunneling */ 959 AUX_CHANNEL_DPIA 960 }; 961 962 /** 963 * struct aux_transaction_parameters - DP AUX request transaction data 964 */ 965 struct aux_transaction_parameters { 966 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 967 uint8_t action; /**< enum dp_aux_request_action */ 968 uint8_t length; /**< DP AUX request data length */ 969 uint8_t reserved; /**< For future use */ 970 uint32_t address; /**< DP AUX address */ 971 uint8_t data[16]; /**< DP AUX write data */ 972 }; 973 974 /** 975 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 976 */ 977 struct dmub_cmd_dp_aux_control_data { 978 uint8_t instance; /**< AUX instance or DPIA instance */ 979 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 980 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 981 uint8_t reserved0; /**< For future use */ 982 uint16_t timeout; /**< timeout time in us */ 983 uint16_t reserved1; /**< For future use */ 984 enum aux_channel_type type; /**< enum aux_channel_type */ 985 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 986 }; 987 988 /** 989 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 990 */ 991 struct dmub_rb_cmd_dp_aux_access { 992 /** 993 * Command header. 994 */ 995 struct dmub_cmd_header header; 996 /** 997 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 998 */ 999 struct dmub_cmd_dp_aux_control_data aux_control; 1000 }; 1001 1002 /** 1003 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1004 */ 1005 struct dmub_rb_cmd_outbox1_enable { 1006 /** 1007 * Command header. 1008 */ 1009 struct dmub_cmd_header header; 1010 /** 1011 * enable: 0x0 -> disable outbox1 notification (default value) 1012 * 0x1 -> enable outbox1 notification 1013 */ 1014 uint32_t enable; 1015 }; 1016 1017 /* DP AUX Reply command - OutBox Cmd */ 1018 /** 1019 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1020 */ 1021 struct aux_reply_data { 1022 /** 1023 * Aux cmd 1024 */ 1025 uint8_t command; 1026 /** 1027 * Aux reply data length (max: 16 bytes) 1028 */ 1029 uint8_t length; 1030 /** 1031 * Alignment only 1032 */ 1033 uint8_t pad[2]; 1034 /** 1035 * Aux reply data 1036 */ 1037 uint8_t data[16]; 1038 }; 1039 1040 /** 1041 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1042 */ 1043 struct aux_reply_control_data { 1044 /** 1045 * Reserved for future use 1046 */ 1047 uint32_t handle; 1048 /** 1049 * Aux Instance 1050 */ 1051 uint8_t instance; 1052 /** 1053 * Aux transaction result: definition in enum aux_return_code_type 1054 */ 1055 uint8_t result; 1056 /** 1057 * Alignment only 1058 */ 1059 uint16_t pad; 1060 }; 1061 1062 /** 1063 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1064 */ 1065 struct dmub_rb_cmd_dp_aux_reply { 1066 /** 1067 * Command header. 1068 */ 1069 struct dmub_cmd_header header; 1070 /** 1071 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1072 */ 1073 struct aux_reply_control_data control; 1074 /** 1075 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1076 */ 1077 struct aux_reply_data reply_data; 1078 }; 1079 1080 /* DP HPD Notify command - OutBox Cmd */ 1081 /** 1082 * DP HPD Type 1083 */ 1084 enum dp_hpd_type { 1085 /** 1086 * Normal DP HPD 1087 */ 1088 DP_HPD = 0, 1089 /** 1090 * DP HPD short pulse 1091 */ 1092 DP_IRQ 1093 }; 1094 1095 /** 1096 * DP HPD Status 1097 */ 1098 enum dp_hpd_status { 1099 /** 1100 * DP_HPD status low 1101 */ 1102 DP_HPD_UNPLUG = 0, 1103 /** 1104 * DP_HPD status high 1105 */ 1106 DP_HPD_PLUG 1107 }; 1108 1109 /** 1110 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1111 */ 1112 struct dp_hpd_data { 1113 /** 1114 * DP HPD instance 1115 */ 1116 uint8_t instance; 1117 /** 1118 * HPD type 1119 */ 1120 uint8_t hpd_type; 1121 /** 1122 * HPD status: only for type: DP_HPD to indicate status 1123 */ 1124 uint8_t hpd_status; 1125 /** 1126 * Alignment only 1127 */ 1128 uint8_t pad; 1129 }; 1130 1131 /** 1132 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1133 */ 1134 struct dmub_rb_cmd_dp_hpd_notify { 1135 /** 1136 * Command header. 1137 */ 1138 struct dmub_cmd_header header; 1139 /** 1140 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1141 */ 1142 struct dp_hpd_data hpd_data; 1143 }; 1144 1145 /* 1146 * Command IDs should be treated as stable ABI. 1147 * Do not reuse or modify IDs. 1148 */ 1149 1150 /** 1151 * PSR command sub-types. 1152 */ 1153 enum dmub_cmd_psr_type { 1154 /** 1155 * Set PSR version support. 1156 */ 1157 DMUB_CMD__PSR_SET_VERSION = 0, 1158 /** 1159 * Copy driver-calculated parameters to PSR state. 1160 */ 1161 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1162 /** 1163 * Enable PSR. 1164 */ 1165 DMUB_CMD__PSR_ENABLE = 2, 1166 1167 /** 1168 * Disable PSR. 1169 */ 1170 DMUB_CMD__PSR_DISABLE = 3, 1171 1172 /** 1173 * Set PSR level. 1174 * PSR level is a 16-bit value dicated by driver that 1175 * will enable/disable different functionality. 1176 */ 1177 DMUB_CMD__PSR_SET_LEVEL = 4, 1178 1179 /** 1180 * Forces PSR enabled until an explicit PSR disable call. 1181 */ 1182 DMUB_CMD__PSR_FORCE_STATIC = 5, 1183 }; 1184 1185 /** 1186 * PSR versions. 1187 */ 1188 enum psr_version { 1189 /** 1190 * PSR version 1. 1191 */ 1192 PSR_VERSION_1 = 0, 1193 /** 1194 * PSR not supported. 1195 */ 1196 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1197 }; 1198 1199 /** 1200 * enum dmub_cmd_mall_type - MALL commands 1201 */ 1202 enum dmub_cmd_mall_type { 1203 /** 1204 * Allows display refresh from MALL. 1205 */ 1206 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1207 /** 1208 * Disallows display refresh from MALL. 1209 */ 1210 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1211 /** 1212 * Cursor copy for MALL. 1213 */ 1214 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1215 /** 1216 * Controls DF requests. 1217 */ 1218 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1219 }; 1220 1221 1222 /** 1223 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1224 */ 1225 struct dmub_cmd_psr_copy_settings_data { 1226 /** 1227 * Flags that can be set by driver to change some PSR behaviour. 1228 */ 1229 union dmub_psr_debug_flags debug; 1230 /** 1231 * 16-bit value dicated by driver that will enable/disable different functionality. 1232 */ 1233 uint16_t psr_level; 1234 /** 1235 * DPP HW instance. 1236 */ 1237 uint8_t dpp_inst; 1238 /** 1239 * MPCC HW instance. 1240 * Not used in dmub fw, 1241 * dmub fw will get active opp by reading odm registers. 1242 */ 1243 uint8_t mpcc_inst; 1244 /** 1245 * OPP HW instance. 1246 * Not used in dmub fw, 1247 * dmub fw will get active opp by reading odm registers. 1248 */ 1249 uint8_t opp_inst; 1250 /** 1251 * OTG HW instance. 1252 */ 1253 uint8_t otg_inst; 1254 /** 1255 * DIG FE HW instance. 1256 */ 1257 uint8_t digfe_inst; 1258 /** 1259 * DIG BE HW instance. 1260 */ 1261 uint8_t digbe_inst; 1262 /** 1263 * DP PHY HW instance. 1264 */ 1265 uint8_t dpphy_inst; 1266 /** 1267 * AUX HW instance. 1268 */ 1269 uint8_t aux_inst; 1270 /** 1271 * Determines if SMU optimzations are enabled/disabled. 1272 */ 1273 uint8_t smu_optimizations_en; 1274 /** 1275 * Unused. 1276 * TODO: Remove. 1277 */ 1278 uint8_t frame_delay; 1279 /** 1280 * If RFB setup time is greater than the total VBLANK time, 1281 * it is not possible for the sink to capture the video frame 1282 * in the same frame the SDP is sent. In this case, 1283 * the frame capture indication bit should be set and an extra 1284 * static frame should be transmitted to the sink. 1285 */ 1286 uint8_t frame_cap_ind; 1287 /** 1288 * Explicit padding to 4 byte boundary. 1289 */ 1290 uint8_t pad[2]; 1291 /** 1292 * Multi-display optimizations are implemented on certain ASICs. 1293 */ 1294 uint8_t multi_disp_optimizations_en; 1295 /** 1296 * The last possible line SDP may be transmitted without violating 1297 * the RFB setup time or entering the active video frame. 1298 */ 1299 uint16_t init_sdp_deadline; 1300 /** 1301 * Explicit padding to 4 byte boundary. 1302 */ 1303 uint16_t pad2; 1304 /** 1305 * Length of each horizontal line in us. 1306 */ 1307 uint32_t line_time_in_us; 1308 /** 1309 * FEC enable status in driver 1310 */ 1311 uint8_t fec_enable_status; 1312 /** 1313 * FEC re-enable delay when PSR exit. 1314 * unit is 100us, range form 0~255(0xFF). 1315 */ 1316 uint8_t fec_enable_delay_in100us; 1317 /** 1318 * Explicit padding to 4 byte boundary. 1319 */ 1320 uint8_t pad3[2]; 1321 }; 1322 1323 /** 1324 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1325 */ 1326 struct dmub_rb_cmd_psr_copy_settings { 1327 /** 1328 * Command header. 1329 */ 1330 struct dmub_cmd_header header; 1331 /** 1332 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1333 */ 1334 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1335 }; 1336 1337 /** 1338 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1339 */ 1340 struct dmub_cmd_psr_set_level_data { 1341 /** 1342 * 16-bit value dicated by driver that will enable/disable different functionality. 1343 */ 1344 uint16_t psr_level; 1345 /** 1346 * Explicit padding to 4 byte boundary. 1347 */ 1348 uint8_t pad[2]; 1349 }; 1350 1351 /** 1352 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1353 */ 1354 struct dmub_rb_cmd_psr_set_level { 1355 /** 1356 * Command header. 1357 */ 1358 struct dmub_cmd_header header; 1359 /** 1360 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1361 */ 1362 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1363 }; 1364 1365 /** 1366 * Definition of a DMUB_CMD__PSR_ENABLE command. 1367 * PSR enable/disable is controlled using the sub_type. 1368 */ 1369 struct dmub_rb_cmd_psr_enable { 1370 /** 1371 * Command header. 1372 */ 1373 struct dmub_cmd_header header; 1374 }; 1375 1376 /** 1377 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1378 */ 1379 struct dmub_cmd_psr_set_version_data { 1380 /** 1381 * PSR version that FW should implement. 1382 */ 1383 enum psr_version version; 1384 }; 1385 1386 /** 1387 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1388 */ 1389 struct dmub_rb_cmd_psr_set_version { 1390 /** 1391 * Command header. 1392 */ 1393 struct dmub_cmd_header header; 1394 /** 1395 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1396 */ 1397 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1398 }; 1399 1400 /** 1401 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1402 */ 1403 struct dmub_rb_cmd_psr_force_static { 1404 /** 1405 * Command header. 1406 */ 1407 struct dmub_cmd_header header; 1408 }; 1409 1410 /** 1411 * Set of HW components that can be locked. 1412 * 1413 * Note: If updating with more HW components, fields 1414 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1415 */ 1416 union dmub_hw_lock_flags { 1417 /** 1418 * Set of HW components that can be locked. 1419 */ 1420 struct { 1421 /** 1422 * Lock/unlock OTG master update lock. 1423 */ 1424 uint8_t lock_pipe : 1; 1425 /** 1426 * Lock/unlock cursor. 1427 */ 1428 uint8_t lock_cursor : 1; 1429 /** 1430 * Lock/unlock global update lock. 1431 */ 1432 uint8_t lock_dig : 1; 1433 /** 1434 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1435 */ 1436 uint8_t triple_buffer_lock : 1; 1437 } bits; 1438 1439 /** 1440 * Union for HW Lock flags. 1441 */ 1442 uint8_t u8All; 1443 }; 1444 1445 /** 1446 * Instances of HW to be locked. 1447 * 1448 * Note: If updating with more HW components, fields 1449 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1450 */ 1451 struct dmub_hw_lock_inst_flags { 1452 /** 1453 * OTG HW instance for OTG master update lock. 1454 */ 1455 uint8_t otg_inst; 1456 /** 1457 * OPP instance for cursor lock. 1458 */ 1459 uint8_t opp_inst; 1460 /** 1461 * OTG HW instance for global update lock. 1462 * TODO: Remove, and re-use otg_inst. 1463 */ 1464 uint8_t dig_inst; 1465 /** 1466 * Explicit pad to 4 byte boundary. 1467 */ 1468 uint8_t pad; 1469 }; 1470 1471 /** 1472 * Clients that can acquire the HW Lock Manager. 1473 * 1474 * Note: If updating with more clients, fields in 1475 * dmub_inbox0_cmd_lock_hw must be updated to match. 1476 */ 1477 enum hw_lock_client { 1478 /** 1479 * Driver is the client of HW Lock Manager. 1480 */ 1481 HW_LOCK_CLIENT_DRIVER = 0, 1482 HW_LOCK_CLIENT_SUBVP = 3, 1483 /** 1484 * Invalid client. 1485 */ 1486 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1487 }; 1488 1489 /** 1490 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1491 */ 1492 struct dmub_cmd_lock_hw_data { 1493 /** 1494 * Specifies the client accessing HW Lock Manager. 1495 */ 1496 enum hw_lock_client client; 1497 /** 1498 * HW instances to be locked. 1499 */ 1500 struct dmub_hw_lock_inst_flags inst_flags; 1501 /** 1502 * Which components to be locked. 1503 */ 1504 union dmub_hw_lock_flags hw_locks; 1505 /** 1506 * Specifies lock/unlock. 1507 */ 1508 uint8_t lock; 1509 /** 1510 * HW can be unlocked separately from releasing the HW Lock Mgr. 1511 * This flag is set if the client wishes to release the object. 1512 */ 1513 uint8_t should_release; 1514 /** 1515 * Explicit padding to 4 byte boundary. 1516 */ 1517 uint8_t pad; 1518 }; 1519 1520 /** 1521 * Definition of a DMUB_CMD__HW_LOCK command. 1522 * Command is used by driver and FW. 1523 */ 1524 struct dmub_rb_cmd_lock_hw { 1525 /** 1526 * Command header. 1527 */ 1528 struct dmub_cmd_header header; 1529 /** 1530 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1531 */ 1532 struct dmub_cmd_lock_hw_data lock_hw_data; 1533 }; 1534 1535 /** 1536 * ABM command sub-types. 1537 */ 1538 enum dmub_cmd_abm_type { 1539 /** 1540 * Initialize parameters for ABM algorithm. 1541 * Data is passed through an indirect buffer. 1542 */ 1543 DMUB_CMD__ABM_INIT_CONFIG = 0, 1544 /** 1545 * Set OTG and panel HW instance. 1546 */ 1547 DMUB_CMD__ABM_SET_PIPE = 1, 1548 /** 1549 * Set user requested backklight level. 1550 */ 1551 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1552 /** 1553 * Set ABM operating/aggression level. 1554 */ 1555 DMUB_CMD__ABM_SET_LEVEL = 3, 1556 /** 1557 * Set ambient light level. 1558 */ 1559 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1560 /** 1561 * Enable/disable fractional duty cycle for backlight PWM. 1562 */ 1563 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1564 }; 1565 1566 /** 1567 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1568 * Requirements: 1569 * - Padded explicitly to 32-bit boundary. 1570 * - Must ensure this structure matches the one on driver-side, 1571 * otherwise it won't be aligned. 1572 */ 1573 struct abm_config_table { 1574 /** 1575 * Gamma curve thresholds, used for crgb conversion. 1576 */ 1577 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1578 /** 1579 * Gamma curve offsets, used for crgb conversion. 1580 */ 1581 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1582 /** 1583 * Gamma curve slopes, used for crgb conversion. 1584 */ 1585 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1586 /** 1587 * Custom backlight curve thresholds. 1588 */ 1589 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1590 /** 1591 * Custom backlight curve offsets. 1592 */ 1593 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1594 /** 1595 * Ambient light thresholds. 1596 */ 1597 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1598 /** 1599 * Minimum programmable backlight. 1600 */ 1601 uint16_t min_abm_backlight; // 122B 1602 /** 1603 * Minimum reduction values. 1604 */ 1605 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1606 /** 1607 * Maximum reduction values. 1608 */ 1609 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1610 /** 1611 * Bright positive gain. 1612 */ 1613 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1614 /** 1615 * Dark negative gain. 1616 */ 1617 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1618 /** 1619 * Hybrid factor. 1620 */ 1621 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1622 /** 1623 * Contrast factor. 1624 */ 1625 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1626 /** 1627 * Deviation gain. 1628 */ 1629 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1630 /** 1631 * Minimum knee. 1632 */ 1633 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1634 /** 1635 * Maximum knee. 1636 */ 1637 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1638 /** 1639 * Unused. 1640 */ 1641 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1642 /** 1643 * Explicit padding to 4 byte boundary. 1644 */ 1645 uint8_t pad3[3]; // 229B 1646 /** 1647 * Backlight ramp reduction. 1648 */ 1649 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1650 /** 1651 * Backlight ramp start. 1652 */ 1653 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1654 }; 1655 1656 /** 1657 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1658 */ 1659 struct dmub_cmd_abm_set_pipe_data { 1660 /** 1661 * OTG HW instance. 1662 */ 1663 uint8_t otg_inst; 1664 1665 /** 1666 * Panel Control HW instance. 1667 */ 1668 uint8_t panel_inst; 1669 1670 /** 1671 * Controls how ABM will interpret a set pipe or set level command. 1672 */ 1673 uint8_t set_pipe_option; 1674 1675 /** 1676 * Unused. 1677 * TODO: Remove. 1678 */ 1679 uint8_t ramping_boundary; 1680 }; 1681 1682 /** 1683 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1684 */ 1685 struct dmub_rb_cmd_abm_set_pipe { 1686 /** 1687 * Command header. 1688 */ 1689 struct dmub_cmd_header header; 1690 1691 /** 1692 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1693 */ 1694 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1695 }; 1696 1697 /** 1698 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1699 */ 1700 struct dmub_cmd_abm_set_backlight_data { 1701 /** 1702 * Number of frames to ramp to backlight user level. 1703 */ 1704 uint32_t frame_ramp; 1705 1706 /** 1707 * Requested backlight level from user. 1708 */ 1709 uint32_t backlight_user_level; 1710 1711 /** 1712 * ABM control version. 1713 */ 1714 uint8_t version; 1715 1716 /** 1717 * Panel Control HW instance mask. 1718 * Bit 0 is Panel Control HW instance 0. 1719 * Bit 1 is Panel Control HW instance 1. 1720 */ 1721 uint8_t panel_mask; 1722 1723 /** 1724 * Explicit padding to 4 byte boundary. 1725 */ 1726 uint8_t pad[2]; 1727 }; 1728 1729 /** 1730 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1731 */ 1732 struct dmub_rb_cmd_abm_set_backlight { 1733 /** 1734 * Command header. 1735 */ 1736 struct dmub_cmd_header header; 1737 1738 /** 1739 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1740 */ 1741 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1742 }; 1743 1744 /** 1745 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1746 */ 1747 struct dmub_cmd_abm_set_level_data { 1748 /** 1749 * Set current ABM operating/aggression level. 1750 */ 1751 uint32_t level; 1752 1753 /** 1754 * ABM control version. 1755 */ 1756 uint8_t version; 1757 1758 /** 1759 * Panel Control HW instance mask. 1760 * Bit 0 is Panel Control HW instance 0. 1761 * Bit 1 is Panel Control HW instance 1. 1762 */ 1763 uint8_t panel_mask; 1764 1765 /** 1766 * Explicit padding to 4 byte boundary. 1767 */ 1768 uint8_t pad[2]; 1769 }; 1770 1771 /** 1772 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1773 */ 1774 struct dmub_rb_cmd_abm_set_level { 1775 /** 1776 * Command header. 1777 */ 1778 struct dmub_cmd_header header; 1779 1780 /** 1781 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1782 */ 1783 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1784 }; 1785 1786 /** 1787 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1788 */ 1789 struct dmub_cmd_abm_set_ambient_level_data { 1790 /** 1791 * Ambient light sensor reading from OS. 1792 */ 1793 uint32_t ambient_lux; 1794 1795 /** 1796 * ABM control version. 1797 */ 1798 uint8_t version; 1799 1800 /** 1801 * Panel Control HW instance mask. 1802 * Bit 0 is Panel Control HW instance 0. 1803 * Bit 1 is Panel Control HW instance 1. 1804 */ 1805 uint8_t panel_mask; 1806 1807 /** 1808 * Explicit padding to 4 byte boundary. 1809 */ 1810 uint8_t pad[2]; 1811 }; 1812 1813 /** 1814 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1815 */ 1816 struct dmub_rb_cmd_abm_set_ambient_level { 1817 /** 1818 * Command header. 1819 */ 1820 struct dmub_cmd_header header; 1821 1822 /** 1823 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1824 */ 1825 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1826 }; 1827 1828 /** 1829 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1830 */ 1831 struct dmub_cmd_abm_set_pwm_frac_data { 1832 /** 1833 * Enable/disable fractional duty cycle for backlight PWM. 1834 * TODO: Convert to uint8_t. 1835 */ 1836 uint32_t fractional_pwm; 1837 1838 /** 1839 * ABM control version. 1840 */ 1841 uint8_t version; 1842 1843 /** 1844 * Panel Control HW instance mask. 1845 * Bit 0 is Panel Control HW instance 0. 1846 * Bit 1 is Panel Control HW instance 1. 1847 */ 1848 uint8_t panel_mask; 1849 1850 /** 1851 * Explicit padding to 4 byte boundary. 1852 */ 1853 uint8_t pad[2]; 1854 }; 1855 1856 /** 1857 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 1858 */ 1859 struct dmub_rb_cmd_abm_set_pwm_frac { 1860 /** 1861 * Command header. 1862 */ 1863 struct dmub_cmd_header header; 1864 1865 /** 1866 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1867 */ 1868 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 1869 }; 1870 1871 /** 1872 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1873 */ 1874 struct dmub_cmd_abm_init_config_data { 1875 /** 1876 * Location of indirect buffer used to pass init data to ABM. 1877 */ 1878 union dmub_addr src; 1879 1880 /** 1881 * Indirect buffer length. 1882 */ 1883 uint16_t bytes; 1884 1885 1886 /** 1887 * ABM control version. 1888 */ 1889 uint8_t version; 1890 1891 /** 1892 * Panel Control HW instance mask. 1893 * Bit 0 is Panel Control HW instance 0. 1894 * Bit 1 is Panel Control HW instance 1. 1895 */ 1896 uint8_t panel_mask; 1897 1898 /** 1899 * Explicit padding to 4 byte boundary. 1900 */ 1901 uint8_t pad[2]; 1902 }; 1903 1904 /** 1905 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 1906 */ 1907 struct dmub_rb_cmd_abm_init_config { 1908 /** 1909 * Command header. 1910 */ 1911 struct dmub_cmd_header header; 1912 1913 /** 1914 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1915 */ 1916 struct dmub_cmd_abm_init_config_data abm_init_config_data; 1917 }; 1918 1919 /** 1920 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1921 */ 1922 struct dmub_cmd_query_feature_caps_data { 1923 /** 1924 * DMUB feature capabilities. 1925 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 1926 */ 1927 struct dmub_feature_caps feature_caps; 1928 }; 1929 1930 /** 1931 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 1932 */ 1933 struct dmub_rb_cmd_query_feature_caps { 1934 /** 1935 * Command header. 1936 */ 1937 struct dmub_cmd_header header; 1938 /** 1939 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1940 */ 1941 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 1942 }; 1943 1944 struct dmub_optc_state { 1945 uint32_t v_total_max; 1946 uint32_t v_total_min; 1947 uint32_t v_total_mid; 1948 uint32_t v_total_mid_frame_num; 1949 uint32_t tg_inst; 1950 uint32_t enable_manual_trigger; 1951 uint32_t clear_force_vsync; 1952 }; 1953 1954 struct dmub_rb_cmd_drr_update { 1955 struct dmub_cmd_header header; 1956 struct dmub_optc_state dmub_optc_state_req; 1957 }; 1958 1959 /** 1960 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1961 */ 1962 struct dmub_cmd_lvtma_control_data { 1963 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 1964 uint8_t reserved_0[3]; /**< For future use */ 1965 uint8_t panel_inst; /**< LVTMA control instance */ 1966 uint8_t reserved_1[3]; /**< For future use */ 1967 }; 1968 1969 /** 1970 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1971 */ 1972 struct dmub_rb_cmd_lvtma_control { 1973 /** 1974 * Command header. 1975 */ 1976 struct dmub_cmd_header header; 1977 /** 1978 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1979 */ 1980 struct dmub_cmd_lvtma_control_data data; 1981 }; 1982 1983 /** 1984 * union dmub_rb_cmd - DMUB inbox command. 1985 */ 1986 union dmub_rb_cmd { 1987 struct dmub_rb_cmd_lock_hw lock_hw; 1988 /** 1989 * Elements shared with all commands. 1990 */ 1991 struct dmub_rb_cmd_common cmd_common; 1992 /** 1993 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 1994 */ 1995 struct dmub_rb_cmd_read_modify_write read_modify_write; 1996 /** 1997 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 1998 */ 1999 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2000 /** 2001 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2002 */ 2003 struct dmub_rb_cmd_burst_write burst_write; 2004 /** 2005 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2006 */ 2007 struct dmub_rb_cmd_reg_wait reg_wait; 2008 /** 2009 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2010 */ 2011 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2012 /** 2013 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2014 */ 2015 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2016 /** 2017 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2018 */ 2019 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2020 /** 2021 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2022 */ 2023 struct dmub_rb_cmd_dpphy_init dpphy_init; 2024 /** 2025 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2026 */ 2027 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2028 /** 2029 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2030 */ 2031 struct dmub_rb_cmd_psr_set_version psr_set_version; 2032 /** 2033 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2034 */ 2035 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2036 /** 2037 * Definition of a DMUB_CMD__PSR_ENABLE command. 2038 */ 2039 struct dmub_rb_cmd_psr_enable psr_enable; 2040 /** 2041 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2042 */ 2043 struct dmub_rb_cmd_psr_set_level psr_set_level; 2044 /** 2045 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2046 */ 2047 struct dmub_rb_cmd_psr_force_static psr_force_static; 2048 /** 2049 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2050 */ 2051 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2052 /** 2053 * Definition of a DMUB_CMD__MALL command. 2054 */ 2055 struct dmub_rb_cmd_mall mall; 2056 /** 2057 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2058 */ 2059 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2060 2061 /** 2062 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2063 */ 2064 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2065 2066 /** 2067 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2068 */ 2069 struct dmub_rb_cmd_abm_set_level abm_set_level; 2070 2071 /** 2072 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2073 */ 2074 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2075 2076 /** 2077 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2078 */ 2079 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2080 2081 /** 2082 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2083 */ 2084 struct dmub_rb_cmd_abm_init_config abm_init_config; 2085 2086 /** 2087 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2088 */ 2089 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2090 2091 /** 2092 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2093 */ 2094 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2095 2096 /** 2097 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2098 */ 2099 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2100 struct dmub_rb_cmd_drr_update drr_update; 2101 /** 2102 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2103 */ 2104 struct dmub_rb_cmd_lvtma_control lvtma_control; 2105 }; 2106 2107 /** 2108 * union dmub_rb_out_cmd - Outbox command 2109 */ 2110 union dmub_rb_out_cmd { 2111 /** 2112 * Parameters common to every command. 2113 */ 2114 struct dmub_rb_cmd_common cmd_common; 2115 /** 2116 * AUX reply command. 2117 */ 2118 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2119 /** 2120 * HPD notify command. 2121 */ 2122 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2123 }; 2124 #pragma pack(pop) 2125 2126 2127 //============================================================================== 2128 //</DMUB_CMD>=================================================================== 2129 //============================================================================== 2130 //< DMUB_RB>==================================================================== 2131 //============================================================================== 2132 2133 #if defined(__cplusplus) 2134 extern "C" { 2135 #endif 2136 2137 /** 2138 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2139 */ 2140 struct dmub_rb_init_params { 2141 void *ctx; /**< Caller provided context pointer */ 2142 void *base_address; /**< CPU base address for ring's data */ 2143 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2144 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2145 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2146 }; 2147 2148 /** 2149 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2150 */ 2151 struct dmub_rb { 2152 void *base_address; /**< CPU address for the ring's data */ 2153 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2154 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2155 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2156 2157 void *ctx; /**< Caller provided context pointer */ 2158 void *dmub; /**< Pointer to the DMUB interface */ 2159 }; 2160 2161 /** 2162 * @brief Checks if the ringbuffer is empty. 2163 * 2164 * @param rb DMUB Ringbuffer 2165 * @return true if empty 2166 * @return false otherwise 2167 */ 2168 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2169 { 2170 return (rb->wrpt == rb->rptr); 2171 } 2172 2173 /** 2174 * @brief Checks if the ringbuffer is full 2175 * 2176 * @param rb DMUB Ringbuffer 2177 * @return true if full 2178 * @return false otherwise 2179 */ 2180 static inline bool dmub_rb_full(struct dmub_rb *rb) 2181 { 2182 uint32_t data_count; 2183 2184 if (rb->wrpt >= rb->rptr) 2185 data_count = rb->wrpt - rb->rptr; 2186 else 2187 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2188 2189 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2190 } 2191 2192 /** 2193 * @brief Pushes a command into the ringbuffer 2194 * 2195 * @param rb DMUB ringbuffer 2196 * @param cmd The command to push 2197 * @return true if the ringbuffer was not full 2198 * @return false otherwise 2199 */ 2200 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2201 const union dmub_rb_cmd *cmd) 2202 { 2203 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2204 const uint64_t *src = (const uint64_t *)cmd; 2205 uint8_t i; 2206 2207 if (dmub_rb_full(rb)) 2208 return false; 2209 2210 // copying data 2211 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2212 *dst++ = *src++; 2213 2214 rb->wrpt += DMUB_RB_CMD_SIZE; 2215 2216 if (rb->wrpt >= rb->capacity) 2217 rb->wrpt %= rb->capacity; 2218 2219 return true; 2220 } 2221 2222 /** 2223 * @brief Pushes a command into the DMUB outbox ringbuffer 2224 * 2225 * @param rb DMUB outbox ringbuffer 2226 * @param cmd Outbox command 2227 * @return true if not full 2228 * @return false otherwise 2229 */ 2230 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2231 const union dmub_rb_out_cmd *cmd) 2232 { 2233 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2234 const uint8_t *src = (uint8_t *)cmd; 2235 2236 if (dmub_rb_full(rb)) 2237 return false; 2238 2239 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2240 2241 rb->wrpt += DMUB_RB_CMD_SIZE; 2242 2243 if (rb->wrpt >= rb->capacity) 2244 rb->wrpt %= rb->capacity; 2245 2246 return true; 2247 } 2248 2249 /** 2250 * @brief Returns the next unprocessed command in the ringbuffer. 2251 * 2252 * @param rb DMUB ringbuffer 2253 * @param cmd The command to return 2254 * @return true if not empty 2255 * @return false otherwise 2256 */ 2257 static inline bool dmub_rb_front(struct dmub_rb *rb, 2258 union dmub_rb_cmd **cmd) 2259 { 2260 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2261 2262 if (dmub_rb_empty(rb)) 2263 return false; 2264 2265 *cmd = (union dmub_rb_cmd *)rb_cmd; 2266 2267 return true; 2268 } 2269 2270 /** 2271 * @brief Determines the next ringbuffer offset. 2272 * 2273 * @param rb DMUB inbox ringbuffer 2274 * @param num_cmds Number of commands 2275 * @param next_rptr The next offset in the ringbuffer 2276 */ 2277 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2278 uint32_t num_cmds, 2279 uint32_t *next_rptr) 2280 { 2281 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2282 2283 if (*next_rptr >= rb->capacity) 2284 *next_rptr %= rb->capacity; 2285 } 2286 2287 /** 2288 * @brief Returns a pointer to a command in the inbox. 2289 * 2290 * @param rb DMUB inbox ringbuffer 2291 * @param cmd The inbox command to return 2292 * @param rptr The ringbuffer offset 2293 * @return true if not empty 2294 * @return false otherwise 2295 */ 2296 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2297 union dmub_rb_cmd **cmd, 2298 uint32_t rptr) 2299 { 2300 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2301 2302 if (dmub_rb_empty(rb)) 2303 return false; 2304 2305 *cmd = (union dmub_rb_cmd *)rb_cmd; 2306 2307 return true; 2308 } 2309 2310 /** 2311 * @brief Returns the next unprocessed command in the outbox. 2312 * 2313 * @param rb DMUB outbox ringbuffer 2314 * @param cmd The outbox command to return 2315 * @return true if not empty 2316 * @return false otherwise 2317 */ 2318 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2319 union dmub_rb_out_cmd *cmd) 2320 { 2321 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2322 uint64_t *dst = (uint64_t *)cmd; 2323 uint8_t i; 2324 2325 if (dmub_rb_empty(rb)) 2326 return false; 2327 2328 // copying data 2329 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2330 *dst++ = *src++; 2331 2332 return true; 2333 } 2334 2335 /** 2336 * @brief Removes the front entry in the ringbuffer. 2337 * 2338 * @param rb DMUB ringbuffer 2339 * @return true if the command was removed 2340 * @return false if there were no commands 2341 */ 2342 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2343 { 2344 if (dmub_rb_empty(rb)) 2345 return false; 2346 2347 rb->rptr += DMUB_RB_CMD_SIZE; 2348 2349 if (rb->rptr >= rb->capacity) 2350 rb->rptr %= rb->capacity; 2351 2352 return true; 2353 } 2354 2355 /** 2356 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2357 * 2358 * Avoids a race condition where DMCUB accesses memory while 2359 * there are still writes in flight to framebuffer. 2360 * 2361 * @param rb DMUB ringbuffer 2362 */ 2363 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2364 { 2365 uint32_t rptr = rb->rptr; 2366 uint32_t wptr = rb->wrpt; 2367 2368 while (rptr != wptr) { 2369 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2370 uint8_t i; 2371 2372 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2373 *data++; 2374 2375 rptr += DMUB_RB_CMD_SIZE; 2376 if (rptr >= rb->capacity) 2377 rptr %= rb->capacity; 2378 } 2379 } 2380 2381 /** 2382 * @brief Initializes a DMCUB ringbuffer 2383 * 2384 * @param rb DMUB ringbuffer 2385 * @param init_params initial configuration for the ringbuffer 2386 */ 2387 static inline void dmub_rb_init(struct dmub_rb *rb, 2388 struct dmub_rb_init_params *init_params) 2389 { 2390 rb->base_address = init_params->base_address; 2391 rb->capacity = init_params->capacity; 2392 rb->rptr = init_params->read_ptr; 2393 rb->wrpt = init_params->write_ptr; 2394 } 2395 2396 /** 2397 * @brief Copies output data from in/out commands into the given command. 2398 * 2399 * @param rb DMUB ringbuffer 2400 * @param cmd Command to copy data into 2401 */ 2402 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2403 union dmub_rb_cmd *cmd) 2404 { 2405 // Copy rb entry back into command 2406 uint8_t *rd_ptr = (rb->rptr == 0) ? 2407 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2408 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2409 2410 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2411 } 2412 2413 #if defined(__cplusplus) 2414 } 2415 #endif 2416 2417 //============================================================================== 2418 //</DMUB_RB>==================================================================== 2419 //============================================================================== 2420 2421 #endif /* _DMUB_CMD_H_ */ 2422