1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0x6444c02e7 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 51 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 72 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 73 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 74 #define SET_ABM_PIPE_NORMAL 1 75 76 /* Maximum number of streams on any ASIC. */ 77 #define DMUB_MAX_STREAMS 6 78 79 /* Maximum number of planes on any ASIC. */ 80 #define DMUB_MAX_PLANES 6 81 82 #ifndef PHYSICAL_ADDRESS_LOC 83 #define PHYSICAL_ADDRESS_LOC union large_integer 84 #endif 85 86 #ifndef dmub_memcpy 87 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 88 #endif 89 90 #ifndef dmub_memset 91 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 92 #endif 93 94 #if defined(__cplusplus) 95 extern "C" { 96 #endif 97 98 #ifndef dmub_udelay 99 #define dmub_udelay(microseconds) udelay(microseconds) 100 #endif 101 102 union dmub_addr { 103 struct { 104 uint32_t low_part; 105 uint32_t high_part; 106 } u; 107 uint64_t quad_part; 108 }; 109 110 union dmub_psr_debug_flags { 111 struct { 112 uint32_t visual_confirm : 1; 113 uint32_t use_hw_lock_mgr : 1; 114 uint32_t log_line_nums : 1; 115 } bitfields; 116 117 uint32_t u32All; 118 }; 119 120 struct dmub_feature_caps { 121 uint8_t psr; 122 uint8_t reserved[7]; 123 }; 124 125 #if defined(__cplusplus) 126 } 127 #endif 128 129 //============================================================================== 130 //</DMUB_TYPES>================================================================= 131 //============================================================================== 132 //< DMUB_META>================================================================== 133 //============================================================================== 134 #pragma pack(push, 1) 135 136 /* Magic value for identifying dmub_fw_meta_info */ 137 #define DMUB_FW_META_MAGIC 0x444D5542 138 139 /* Offset from the end of the file to the dmub_fw_meta_info */ 140 #define DMUB_FW_META_OFFSET 0x24 141 142 /** 143 * struct dmub_fw_meta_info - metadata associated with fw binary 144 * 145 * NOTE: This should be considered a stable API. Fields should 146 * not be repurposed or reordered. New fields should be 147 * added instead to extend the structure. 148 * 149 * @magic_value: magic value identifying DMUB firmware meta info 150 * @fw_region_size: size of the firmware state region 151 * @trace_buffer_size: size of the tracebuffer region 152 * @fw_version: the firmware version information 153 * @dal_fw: 1 if the firmware is DAL 154 */ 155 struct dmub_fw_meta_info { 156 uint32_t magic_value; 157 uint32_t fw_region_size; 158 uint32_t trace_buffer_size; 159 uint32_t fw_version; 160 uint8_t dal_fw; 161 uint8_t reserved[3]; 162 }; 163 164 /* Ensure that the structure remains 64 bytes. */ 165 union dmub_fw_meta { 166 struct dmub_fw_meta_info info; 167 uint8_t reserved[64]; 168 }; 169 170 #pragma pack(pop) 171 172 //============================================================================== 173 //< DMUB_STATUS>================================================================ 174 //============================================================================== 175 176 /** 177 * DMCUB scratch registers can be used to determine firmware status. 178 * Current scratch register usage is as follows: 179 * 180 * SCRATCH0: FW Boot Status register 181 * SCRATCH15: FW Boot Options register 182 */ 183 184 /* Register bit definition for SCRATCH0 */ 185 union dmub_fw_boot_status { 186 struct { 187 uint32_t dal_fw : 1; 188 uint32_t mailbox_rdy : 1; 189 uint32_t optimized_init_done : 1; 190 uint32_t restore_required : 1; 191 } bits; 192 uint32_t all; 193 }; 194 195 enum dmub_fw_boot_status_bit { 196 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 197 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 198 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 199 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 200 }; 201 202 /* Register bit definition for SCRATCH15 */ 203 union dmub_fw_boot_options { 204 struct { 205 uint32_t pemu_env : 1; 206 uint32_t fpga_env : 1; 207 uint32_t optimized_init : 1; 208 uint32_t skip_phy_access : 1; 209 uint32_t disable_clk_gate: 1; 210 uint32_t skip_phy_init_panel_sequence: 1; 211 uint32_t reserved : 26; 212 } bits; 213 uint32_t all; 214 }; 215 216 enum dmub_fw_boot_options_bit { 217 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 218 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 219 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 220 }; 221 222 //============================================================================== 223 //</DMUB_STATUS>================================================================ 224 //============================================================================== 225 //< DMUB_VBIOS>================================================================= 226 //============================================================================== 227 228 /* 229 * Command IDs should be treated as stable ABI. 230 * Do not reuse or modify IDs. 231 */ 232 233 enum dmub_cmd_vbios_type { 234 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 235 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 236 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 237 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 238 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 239 }; 240 241 //============================================================================== 242 //</DMUB_VBIOS>================================================================= 243 //============================================================================== 244 //< DMUB_GPINT>================================================================= 245 //============================================================================== 246 247 /** 248 * The shifts and masks below may alternatively be used to format and read 249 * the command register bits. 250 */ 251 252 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 253 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 254 255 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 256 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 257 258 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 259 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 260 261 /** 262 * Command responses. 263 */ 264 265 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 266 267 /** 268 * The register format for sending a command via the GPINT. 269 */ 270 union dmub_gpint_data_register { 271 struct { 272 uint32_t param : 16; 273 uint32_t command_code : 12; 274 uint32_t status : 4; 275 } bits; 276 uint32_t all; 277 }; 278 279 /* 280 * Command IDs should be treated as stable ABI. 281 * Do not reuse or modify IDs. 282 */ 283 284 enum dmub_gpint_command { 285 DMUB_GPINT__INVALID_COMMAND = 0, 286 DMUB_GPINT__GET_FW_VERSION = 1, 287 DMUB_GPINT__STOP_FW = 2, 288 DMUB_GPINT__GET_PSR_STATE = 7, 289 /** 290 * DESC: Notifies DMCUB of the currently active streams. 291 * ARGS: Stream mask, 1 bit per active stream index. 292 */ 293 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 294 DMUB_GPINT__PSR_RESIDENCY = 9, 295 }; 296 297 //============================================================================== 298 //</DMUB_GPINT>================================================================= 299 //============================================================================== 300 //< DMUB_CMD>=================================================================== 301 //============================================================================== 302 303 #define DMUB_RB_CMD_SIZE 64 304 #define DMUB_RB_MAX_ENTRY 128 305 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 306 #define REG_SET_MASK 0xFFFF 307 308 /* 309 * Command IDs should be treated as stable ABI. 310 * Do not reuse or modify IDs. 311 */ 312 313 enum dmub_cmd_type { 314 DMUB_CMD__NULL = 0, 315 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 316 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 317 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 318 DMUB_CMD__REG_REG_WAIT = 4, 319 DMUB_CMD__PLAT_54186_WA = 5, 320 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 321 DMUB_CMD__PSR = 64, 322 DMUB_CMD__MALL = 65, 323 DMUB_CMD__ABM = 66, 324 DMUB_CMD__HW_LOCK = 69, 325 DMUB_CMD__DP_AUX_ACCESS = 70, 326 DMUB_CMD__OUTBOX1_ENABLE = 71, 327 DMUB_CMD__VBIOS = 128, 328 }; 329 330 enum dmub_out_cmd_type { 331 DMUB_OUT_CMD__NULL = 0, 332 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 333 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 334 }; 335 336 #pragma pack(push, 1) 337 338 struct dmub_cmd_header { 339 unsigned int type : 8; 340 unsigned int sub_type : 8; 341 unsigned int ret_status : 1; 342 unsigned int reserved0 : 7; 343 unsigned int payload_bytes : 6; /* up to 60 bytes */ 344 unsigned int reserved1 : 2; 345 }; 346 347 /* 348 * Read modify write 349 * 350 * 60 payload bytes can hold up to 5 sets of read modify writes, 351 * each take 3 dwords. 352 * 353 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 354 * 355 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 356 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 357 */ 358 struct dmub_cmd_read_modify_write_sequence { 359 uint32_t addr; 360 uint32_t modify_mask; 361 uint32_t modify_value; 362 }; 363 364 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 365 struct dmub_rb_cmd_read_modify_write { 366 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 367 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 368 }; 369 370 /* 371 * Update a register with specified masks and values sequeunce 372 * 373 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 374 * 375 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 376 * 377 * 378 * USE CASE: 379 * 1. auto-increment register where additional read would update pointer and produce wrong result 380 * 2. toggle a bit without read in the middle 381 */ 382 383 struct dmub_cmd_reg_field_update_sequence { 384 uint32_t modify_mask; // 0xffff'ffff to skip initial read 385 uint32_t modify_value; 386 }; 387 388 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 389 struct dmub_rb_cmd_reg_field_update_sequence { 390 struct dmub_cmd_header header; 391 uint32_t addr; 392 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 393 }; 394 395 /* 396 * Burst write 397 * 398 * support use case such as writing out LUTs. 399 * 400 * 60 payload bytes can hold up to 14 values to write to given address 401 * 402 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 403 */ 404 #define DMUB_BURST_WRITE_VALUES__MAX 14 405 struct dmub_rb_cmd_burst_write { 406 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 407 uint32_t addr; 408 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 409 }; 410 411 412 struct dmub_rb_cmd_common { 413 struct dmub_cmd_header header; 414 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 415 }; 416 417 struct dmub_cmd_reg_wait_data { 418 uint32_t addr; 419 uint32_t mask; 420 uint32_t condition_field_value; 421 uint32_t time_out_us; 422 }; 423 424 struct dmub_rb_cmd_reg_wait { 425 struct dmub_cmd_header header; 426 struct dmub_cmd_reg_wait_data reg_wait; 427 }; 428 429 struct dmub_cmd_PLAT_54186_wa { 430 uint32_t DCSURF_SURFACE_CONTROL; 431 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 432 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 433 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 434 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 435 struct { 436 uint8_t hubp_inst : 4; 437 uint8_t tmz_surface : 1; 438 uint8_t immediate :1; 439 uint8_t vmid : 4; 440 uint8_t grph_stereo : 1; 441 uint32_t reserved : 21; 442 } flip_params; 443 uint32_t reserved[9]; 444 }; 445 446 struct dmub_rb_cmd_PLAT_54186_wa { 447 struct dmub_cmd_header header; 448 struct dmub_cmd_PLAT_54186_wa flip; 449 }; 450 451 struct dmub_rb_cmd_mall { 452 struct dmub_cmd_header header; 453 union dmub_addr cursor_copy_src; 454 union dmub_addr cursor_copy_dst; 455 uint32_t tmr_delay; 456 uint32_t tmr_scale; 457 uint16_t cursor_width; 458 uint16_t cursor_pitch; 459 uint16_t cursor_height; 460 uint8_t cursor_bpp; 461 uint8_t debug_bits; 462 463 uint8_t reserved1; 464 uint8_t reserved2; 465 }; 466 467 struct dmub_cmd_digx_encoder_control_data { 468 union dig_encoder_control_parameters_v1_5 dig; 469 }; 470 471 struct dmub_rb_cmd_digx_encoder_control { 472 struct dmub_cmd_header header; 473 struct dmub_cmd_digx_encoder_control_data encoder_control; 474 }; 475 476 struct dmub_cmd_set_pixel_clock_data { 477 struct set_pixel_clock_parameter_v1_7 clk; 478 }; 479 480 struct dmub_rb_cmd_set_pixel_clock { 481 struct dmub_cmd_header header; 482 struct dmub_cmd_set_pixel_clock_data pixel_clock; 483 }; 484 485 struct dmub_cmd_enable_disp_power_gating_data { 486 struct enable_disp_power_gating_parameters_v2_1 pwr; 487 }; 488 489 struct dmub_rb_cmd_enable_disp_power_gating { 490 struct dmub_cmd_header header; 491 struct dmub_cmd_enable_disp_power_gating_data power_gating; 492 }; 493 494 struct dmub_dig_transmitter_control_data_v1_7 { 495 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 496 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 497 union { 498 uint8_t digmode; /**< enum atom_encode_mode_def */ 499 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 500 } mode_laneset; 501 uint8_t lanenum; /**< Number of lanes */ 502 union { 503 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 504 } symclk_units; 505 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 506 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 507 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 508 uint8_t reserved0; /**< For future use */ 509 uint8_t reserved1; /**< For future use */ 510 uint8_t reserved2[3]; /**< For future use */ 511 uint32_t reserved3[11]; /**< For future use */ 512 }; 513 514 union dmub_cmd_dig1_transmitter_control_data { 515 struct dig_transmitter_control_parameters_v1_6 dig; 516 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; 517 }; 518 519 struct dmub_rb_cmd_dig1_transmitter_control { 520 struct dmub_cmd_header header; 521 union dmub_cmd_dig1_transmitter_control_data transmitter_control; 522 }; 523 524 struct dmub_rb_cmd_dpphy_init { 525 struct dmub_cmd_header header; 526 uint8_t reserved[60]; 527 }; 528 529 enum dp_aux_request_action { 530 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 531 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 532 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 533 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 534 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 535 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 536 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 537 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 538 }; 539 540 enum aux_return_code_type { 541 AUX_RET_SUCCESS = 0, 542 AUX_RET_ERROR_UNKNOWN, 543 AUX_RET_ERROR_INVALID_REPLY, 544 AUX_RET_ERROR_TIMEOUT, 545 AUX_RET_ERROR_HPD_DISCON, 546 AUX_RET_ERROR_ENGINE_ACQUIRE, 547 AUX_RET_ERROR_INVALID_OPERATION, 548 AUX_RET_ERROR_PROTOCOL_ERROR, 549 }; 550 551 enum aux_channel_type { 552 AUX_CHANNEL_LEGACY_DDC, 553 AUX_CHANNEL_DPIA 554 }; 555 556 /* DP AUX command */ 557 struct aux_transaction_parameters { 558 uint8_t is_i2c_over_aux; 559 uint8_t action; 560 uint8_t length; 561 uint8_t pad; 562 uint32_t address; 563 uint8_t data[16]; 564 }; 565 566 struct dmub_cmd_dp_aux_control_data { 567 uint32_t handle; 568 uint8_t instance; 569 uint8_t sw_crc_enabled; 570 uint16_t timeout; 571 enum aux_channel_type type; 572 struct aux_transaction_parameters dpaux; 573 }; 574 575 struct dmub_rb_cmd_dp_aux_access { 576 struct dmub_cmd_header header; 577 struct dmub_cmd_dp_aux_control_data aux_control; 578 }; 579 580 struct dmub_rb_cmd_outbox1_enable { 581 struct dmub_cmd_header header; 582 uint32_t enable; 583 }; 584 585 /* DP AUX Reply command - OutBox Cmd */ 586 struct aux_reply_data { 587 uint8_t command; 588 uint8_t length; 589 uint8_t pad[2]; 590 uint8_t data[16]; 591 }; 592 593 struct aux_reply_control_data { 594 uint32_t handle; 595 uint8_t instance; 596 uint8_t result; 597 uint16_t pad; 598 }; 599 600 struct dmub_rb_cmd_dp_aux_reply { 601 struct dmub_cmd_header header; 602 struct aux_reply_control_data control; 603 struct aux_reply_data reply_data; 604 }; 605 606 /* DP HPD Notify command - OutBox Cmd */ 607 enum dp_hpd_type { 608 DP_HPD = 0, 609 DP_IRQ 610 }; 611 612 enum dp_hpd_status { 613 DP_HPD_UNPLUG = 0, 614 DP_HPD_PLUG 615 }; 616 617 struct dp_hpd_data { 618 uint8_t instance; 619 uint8_t hpd_type; 620 uint8_t hpd_status; 621 uint8_t pad; 622 }; 623 624 struct dmub_rb_cmd_dp_hpd_notify { 625 struct dmub_cmd_header header; 626 struct dp_hpd_data hpd_data; 627 }; 628 629 /* 630 * Command IDs should be treated as stable ABI. 631 * Do not reuse or modify IDs. 632 */ 633 634 enum dmub_cmd_psr_type { 635 DMUB_CMD__PSR_SET_VERSION = 0, 636 DMUB_CMD__PSR_COPY_SETTINGS = 1, 637 DMUB_CMD__PSR_ENABLE = 2, 638 DMUB_CMD__PSR_DISABLE = 3, 639 DMUB_CMD__PSR_SET_LEVEL = 4, 640 DMUB_CMD__PSR_FORCE_STATIC = 5, 641 }; 642 643 enum psr_version { 644 PSR_VERSION_1 = 0, 645 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 646 }; 647 648 enum dmub_cmd_mall_type { 649 DMUB_CMD__MALL_ACTION_ALLOW = 0, 650 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 651 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 652 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 653 }; 654 655 struct dmub_cmd_psr_copy_settings_data { 656 union dmub_psr_debug_flags debug; 657 uint16_t psr_level; 658 uint8_t dpp_inst; 659 /* opp_inst and mpcc_inst will not be used in dmub fw, 660 * dmub fw will get active opp by reading odm registers. 661 */ 662 uint8_t mpcc_inst; 663 uint8_t opp_inst; 664 665 uint8_t otg_inst; 666 uint8_t digfe_inst; 667 uint8_t digbe_inst; 668 uint8_t dpphy_inst; 669 uint8_t aux_inst; 670 uint8_t smu_optimizations_en; 671 uint8_t frame_delay; 672 uint8_t frame_cap_ind; 673 uint8_t pad[2]; 674 uint8_t multi_disp_optimizations_en; 675 uint16_t init_sdp_deadline; 676 uint16_t pad2; 677 uint32_t line_time_in_us; 678 }; 679 680 struct dmub_rb_cmd_psr_copy_settings { 681 struct dmub_cmd_header header; 682 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 683 }; 684 685 struct dmub_cmd_psr_set_level_data { 686 uint16_t psr_level; 687 uint8_t pad[2]; 688 }; 689 690 struct dmub_rb_cmd_psr_set_level { 691 struct dmub_cmd_header header; 692 struct dmub_cmd_psr_set_level_data psr_set_level_data; 693 }; 694 695 struct dmub_rb_cmd_psr_enable { 696 struct dmub_cmd_header header; 697 }; 698 699 struct dmub_cmd_psr_set_version_data { 700 enum psr_version version; // PSR version 1 or 2 701 }; 702 703 struct dmub_rb_cmd_psr_set_version { 704 struct dmub_cmd_header header; 705 struct dmub_cmd_psr_set_version_data psr_set_version_data; 706 }; 707 708 struct dmub_rb_cmd_psr_force_static { 709 struct dmub_cmd_header header; 710 }; 711 712 union dmub_hw_lock_flags { 713 struct { 714 uint8_t lock_pipe : 1; 715 uint8_t lock_cursor : 1; 716 uint8_t lock_dig : 1; 717 uint8_t triple_buffer_lock : 1; 718 } bits; 719 720 uint8_t u8All; 721 }; 722 723 struct dmub_hw_lock_inst_flags { 724 uint8_t otg_inst; 725 uint8_t opp_inst; 726 uint8_t dig_inst; 727 uint8_t pad; 728 }; 729 730 enum hw_lock_client { 731 HW_LOCK_CLIENT_DRIVER = 0, 732 HW_LOCK_CLIENT_FW, 733 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 734 }; 735 736 struct dmub_cmd_lock_hw_data { 737 enum hw_lock_client client; 738 struct dmub_hw_lock_inst_flags inst_flags; 739 union dmub_hw_lock_flags hw_locks; 740 uint8_t lock; 741 uint8_t should_release; 742 uint8_t pad; 743 }; 744 745 struct dmub_rb_cmd_lock_hw { 746 struct dmub_cmd_header header; 747 struct dmub_cmd_lock_hw_data lock_hw_data; 748 }; 749 750 enum dmub_cmd_abm_type { 751 DMUB_CMD__ABM_INIT_CONFIG = 0, 752 DMUB_CMD__ABM_SET_PIPE = 1, 753 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 754 DMUB_CMD__ABM_SET_LEVEL = 3, 755 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 756 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 757 }; 758 759 #define NUM_AMBI_LEVEL 5 760 #define NUM_AGGR_LEVEL 4 761 #define NUM_POWER_FN_SEGS 8 762 #define NUM_BL_CURVE_SEGS 16 763 764 /* 765 * Parameters for ABM2.4 algorithm. 766 * Padded explicitly to 32-bit boundary. 767 */ 768 struct abm_config_table { 769 /* Parameters for crgb conversion */ 770 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 771 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 772 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 773 774 /* Parameters for custom curve */ 775 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 776 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 777 778 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 779 uint16_t min_abm_backlight; // 122B 780 781 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 782 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 783 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 784 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 785 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 786 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 787 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 788 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 789 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 790 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 791 uint8_t pad3[3]; // 229B 792 793 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 794 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 795 }; 796 797 struct dmub_cmd_abm_set_pipe_data { 798 uint8_t otg_inst; 799 uint8_t panel_inst; 800 uint8_t set_pipe_option; 801 uint8_t ramping_boundary; // TODO: Remove this 802 }; 803 804 struct dmub_rb_cmd_abm_set_pipe { 805 struct dmub_cmd_header header; 806 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 807 }; 808 809 struct dmub_cmd_abm_set_backlight_data { 810 uint32_t frame_ramp; 811 uint32_t backlight_user_level; 812 }; 813 814 struct dmub_rb_cmd_abm_set_backlight { 815 struct dmub_cmd_header header; 816 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 817 }; 818 819 struct dmub_cmd_abm_set_level_data { 820 uint32_t level; 821 }; 822 823 struct dmub_rb_cmd_abm_set_level { 824 struct dmub_cmd_header header; 825 struct dmub_cmd_abm_set_level_data abm_set_level_data; 826 }; 827 828 struct dmub_cmd_abm_set_ambient_level_data { 829 uint32_t ambient_lux; 830 }; 831 832 struct dmub_rb_cmd_abm_set_ambient_level { 833 struct dmub_cmd_header header; 834 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 835 }; 836 837 struct dmub_cmd_abm_set_pwm_frac_data { 838 uint32_t fractional_pwm; 839 }; 840 841 struct dmub_rb_cmd_abm_set_pwm_frac { 842 struct dmub_cmd_header header; 843 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 844 }; 845 846 struct dmub_cmd_abm_init_config_data { 847 union dmub_addr src; 848 uint16_t bytes; 849 }; 850 851 struct dmub_rb_cmd_abm_init_config { 852 struct dmub_cmd_header header; 853 struct dmub_cmd_abm_init_config_data abm_init_config_data; 854 }; 855 856 struct dmub_cmd_query_feature_caps_data { 857 struct dmub_feature_caps feature_caps; 858 }; 859 860 struct dmub_rb_cmd_query_feature_caps { 861 struct dmub_cmd_header header; 862 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 863 }; 864 865 union dmub_rb_cmd { 866 struct dmub_rb_cmd_lock_hw lock_hw; 867 struct dmub_rb_cmd_read_modify_write read_modify_write; 868 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 869 struct dmub_rb_cmd_burst_write burst_write; 870 struct dmub_rb_cmd_reg_wait reg_wait; 871 struct dmub_rb_cmd_common cmd_common; 872 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 873 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 874 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 875 struct dmub_rb_cmd_dpphy_init dpphy_init; 876 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 877 struct dmub_rb_cmd_psr_set_version psr_set_version; 878 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 879 struct dmub_rb_cmd_psr_enable psr_enable; 880 struct dmub_rb_cmd_psr_set_level psr_set_level; 881 struct dmub_rb_cmd_psr_force_static psr_force_static; 882 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 883 struct dmub_rb_cmd_mall mall; 884 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 885 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 886 struct dmub_rb_cmd_abm_set_level abm_set_level; 887 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 888 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 889 struct dmub_rb_cmd_abm_init_config abm_init_config; 890 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 891 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 892 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 893 }; 894 895 union dmub_rb_out_cmd { 896 struct dmub_rb_cmd_common cmd_common; 897 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 898 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 899 }; 900 #pragma pack(pop) 901 902 903 //============================================================================== 904 //</DMUB_CMD>=================================================================== 905 //============================================================================== 906 //< DMUB_RB>==================================================================== 907 //============================================================================== 908 909 #if defined(__cplusplus) 910 extern "C" { 911 #endif 912 913 struct dmub_rb_init_params { 914 void *ctx; 915 void *base_address; 916 uint32_t capacity; 917 uint32_t read_ptr; 918 uint32_t write_ptr; 919 }; 920 921 struct dmub_rb { 922 void *base_address; 923 uint32_t data_count; 924 uint32_t rptr; 925 uint32_t wrpt; 926 uint32_t capacity; 927 928 void *ctx; 929 void *dmub; 930 }; 931 932 933 static inline bool dmub_rb_empty(struct dmub_rb *rb) 934 { 935 return (rb->wrpt == rb->rptr); 936 } 937 938 static inline bool dmub_rb_full(struct dmub_rb *rb) 939 { 940 uint32_t data_count; 941 942 if (rb->wrpt >= rb->rptr) 943 data_count = rb->wrpt - rb->rptr; 944 else 945 data_count = rb->capacity - (rb->rptr - rb->wrpt); 946 947 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 948 } 949 950 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 951 const union dmub_rb_cmd *cmd) 952 { 953 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 954 const uint64_t *src = (const uint64_t *)cmd; 955 uint8_t i; 956 957 if (dmub_rb_full(rb)) 958 return false; 959 960 // copying data 961 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 962 *dst++ = *src++; 963 964 rb->wrpt += DMUB_RB_CMD_SIZE; 965 966 if (rb->wrpt >= rb->capacity) 967 rb->wrpt %= rb->capacity; 968 969 return true; 970 } 971 972 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 973 const union dmub_rb_out_cmd *cmd) 974 { 975 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 976 const uint8_t *src = (uint8_t *)cmd; 977 978 if (dmub_rb_full(rb)) 979 return false; 980 981 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 982 983 rb->wrpt += DMUB_RB_CMD_SIZE; 984 985 if (rb->wrpt >= rb->capacity) 986 rb->wrpt %= rb->capacity; 987 988 return true; 989 } 990 991 static inline bool dmub_rb_front(struct dmub_rb *rb, 992 union dmub_rb_cmd **cmd) 993 { 994 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 995 996 if (dmub_rb_empty(rb)) 997 return false; 998 999 *cmd = (union dmub_rb_cmd *)rb_cmd; 1000 1001 return true; 1002 } 1003 1004 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 1005 union dmub_rb_out_cmd *cmd) 1006 { 1007 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1008 uint64_t *dst = (uint64_t *)cmd; 1009 uint8_t i; 1010 1011 if (dmub_rb_empty(rb)) 1012 return false; 1013 1014 // copying data 1015 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 1016 *dst++ = *src++; 1017 1018 return true; 1019 } 1020 1021 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 1022 { 1023 if (dmub_rb_empty(rb)) 1024 return false; 1025 1026 rb->rptr += DMUB_RB_CMD_SIZE; 1027 1028 if (rb->rptr >= rb->capacity) 1029 rb->rptr %= rb->capacity; 1030 1031 return true; 1032 } 1033 1034 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 1035 { 1036 uint32_t rptr = rb->rptr; 1037 uint32_t wptr = rb->wrpt; 1038 1039 while (rptr != wptr) { 1040 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 1041 uint8_t i; 1042 1043 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 1044 *data++; 1045 1046 rptr += DMUB_RB_CMD_SIZE; 1047 if (rptr >= rb->capacity) 1048 rptr %= rb->capacity; 1049 } 1050 } 1051 1052 static inline void dmub_rb_init(struct dmub_rb *rb, 1053 struct dmub_rb_init_params *init_params) 1054 { 1055 rb->base_address = init_params->base_address; 1056 rb->capacity = init_params->capacity; 1057 rb->rptr = init_params->read_ptr; 1058 rb->wrpt = init_params->write_ptr; 1059 } 1060 1061 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 1062 union dmub_rb_cmd *cmd) 1063 { 1064 // Copy rb entry back into command 1065 uint8_t *rd_ptr = (rb->rptr == 0) ? 1066 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 1067 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 1068 1069 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 1070 } 1071 1072 #if defined(__cplusplus) 1073 } 1074 #endif 1075 1076 //============================================================================== 1077 //</DMUB_RB>==================================================================== 1078 //============================================================================== 1079 1080 #endif /* _DMUB_CMD_H_ */ 1081